Renesas 7542 User manual

DESCRIPTION
The 7542 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7542 Group has serial I/Os, 8-bit timers, 16-bit timers, and an
A/D converter, and is useful for control of home electric appliances
and office automation equipment.
FEATURES
•Basic machine-language instructions ...................................... 71
• The minimum instruction execution time ............................. 0.25 µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
•Memory size
Flash memory version: ROM ..................... 16 to 32K + 4K bytes
RAM ..................................... 1024 bytes
Mask ROM version: ROM............................. 8K to 16K bytes
RAM ............................ 384 to 512 bytes
RSS version RAM ..................................... 1024 bytes
•Programmable I/O ports
29 (25 in 32-pin version and PWQN0036KA-A package version)
•Interrupts ................................................. 18 sources, 16 vectors
•Timers............................................................................. 8-bit ✕2
...................................................................................... 16-bit ✕2
•Output compare............................................................ 4-channel
•Input capture ................................................................ 2-channel
•Serial I/O...................... 8-bit ✕2 (UART or Clock-synchronized)
•A/D converter ............................................... 10-bit ✕8 channels
..... (6 channels in 32-pin version and PWQN0036KA-A package
version)
•Clock generating circuit............................................. Built-in type
(low-power dissipation by an on-chip oscillator)
(connected to external ceramic resonator or quartz-crystal
oscillator permitting RC oscillation)
•Watchdog timer ............................................................ 16-bit ✕1
•Power source voltage
X IN oscillation frequency at ceramic oscillation, in double-speed mode
At 8 MHz.................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz.................................................................... 4.0 to 5.5 V
At 4 MHz.................................................................... 2.4 to 5.5 V
At 2 MHz.................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz.................................................................... 4.0 to 5.5 V
At 2 MHz.................................................................... 2.4 to 5.5 V
At 1 MHz.................................................................... 2.2 to 5.5 V
•Power dissipation ................................................ 27.5 mW (Typ.)
•Operating temperature range...................................–20 to 85 °C
(–40 to 85 °C for extended operating temperature version)
(–40 to 125 °C for extended operating temperature 125 °C ver-
sion (Note))
Note: In this version, the operating temperature range and total time are
limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
APPLICATION
Office automation equipment, factory automation equipment, home
electric appliances, consumer electronics, car, etc.
Rev.3.02 Oct 31, 2006 Page 1 of 134
REJ03B0006-0302
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0006-0302
Rev.3.02
Oct 31, 2006

7542 Group
Rev.3.02 Oct 31, 2006 Page 2 of 134
REJ03B0006-0302
Fig. 2 Pin configuration (Package type: PRSP0036GA-A)
PIN CONFIGURATION (TOP VIEW)
Fig. 1 Pin configuration (Package type: PLQP0032GB-A)
Outline PLQP0032GB-A (32P6U-A)
P0 7 (LED 07 )/S RDY2
P1 0 /R X D 1 /CAP 0
P1 1 /T X D 1
P1 2 /S CLK1
P1 3 /S RDY1
P1 4 /CNTR 0
P2 0 /AN 0
P2 1 /AN 1
32
31
30
29
28
27
26
25
P3 4 (LED 14 )
P3
3 (LED 13 )/INT 1
P3 2 (LED 12 )/CMP 3
P3 1 (LED 11 )/CMP 2
P3 0 (LED 10 )/CAP 1
V SS
X OUT
X IN
9
10
11
12
13
14
15
16
8765314
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
20 1718192124
P0
2
(LED
02
)/CMP
1
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
6
(LED
06
)/S
CLK2
23 22
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
M37542Mx-XXXGP
M37542MxT-XXXGP
M37542MxV-XXXGP
M37542FxGP
M37542F8TGP
M37542F8VGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
2
Packa
g
e t
yp
e: PRSP0036GA-A
(
36P2R-A
)
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
CNVSS
XOUT
XIN
VSS
P04(LED04)/RxD2
P30(LED10)/CAP1
Vcc
VREF
P05(LED05)/TxD2
P10/RXD1/CAP0
P26/AN6
P27/AN7
P11/TXD1
P12/SCLK1
P13/SRDY1
P23/AN3
P22/AN2
P21/AN1
P20/AN0
P31(LED11)/CMP2
P36(LED16)/INT1
P24/AN4
P25/AN5
P06(LED06)/SCLK2
P07(LED07)/SRDY2
RESET
M37542Mx-XXXFP
M37542MxT-XXXFP
M37542MxV-XXXFP
M37542FxFP
M37542F8TFP
M37542F8VFP
P14/CNTR0
P35(LED15)
P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P37(LED17)/INT0
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT

7542 Group
Rev.3.02 Oct 31, 2006 Page 3 of 134
REJ03B0006-0302
Fig. 4 Pin configuration (Package type: PWQN0036KA-A)
Fig. 3 Pin configuration (Package type: PRDP0032BA-A)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CNV SS
P1 2 /S CLK1
P1 3 /S RDY1
P1 4 /CNTR 0
P2 0 /AN 0
P2 1 /AN 1
P2 2 /AN 2
P2 3 /AN 3
P2 4 /AN 4
V CC
X IN
X OUT
V SS
P1 1 /T X D 1
P1 0 /R X D 1 /CAP 0
P0 7 (LED 07 )/S RDY2
P0 6 (LED 06 )/S CLK2
P0 5 (LED 05 )/TxD 2
P0 4 (LED 04 )/RxD 2
P3 0 (LED 10 )/CAP 1
P2 5 /AN 5
V REF
RESET
P3
3 (LED 13 )/INT 1
P3 2 (LED 12 )/CMP 3
P3 1 (LED 11 )/CMP 2
M37542Mx-XXXSP
M37542FxSP
32
14
15
16
P3 4 (LED 14 )
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Package type: PRDP0032BA-A (32P4B)
P0 3 (LED 03 )/TX OUT
P0 2 (LED 02 )/CMP 1
P0 1 (LED 01 )/CMP 0
P0 0 (LED 00 )/CAP 0
P3 7 (LED 17 )/INT 0
Package type: PWQN0036KA-A (36PJW-A)
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN1
[N.C.]
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
P30(LED10)/CAP1
Vss
XOUT
XIN
[N.C.]
Vcc
CNVss
RESET
P06(LED06)/SCLK2
P3
4
(LED
14
)
M37542Mx-XXXHP
M37542F8HP(Note)
P2
5
/AN
5
V
REF
36
[N.C.] [N.C.]
P2
4
/AN
4
P2
3
/AN
3
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
2
(LED
02
)/CMP
1
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
27 26 25 20 192124 23 22
987653142
31
30
29
28
35
34
33
32
10
11
12
13
14
15
16
17
18
N.C.: Non Connection
Note: Only ES version
(MP: no plan)

7542 Group
Rev.3.02 Oct 31, 2006 Page 4 of 134
REJ03B0006-0302
Fig. 5 Pin configuration (Package type: 42S1M)
Packa
g
e t
yp
e 42S1M
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
32
27
29
28
19
20
21
42
41
40
39
37
38
CNV SS
X OUT
X IN
V SS
P0 4 (LED 04 )/RxD2
P3 0 (LED 10 )/CAP 1
Vcc
V
REF
P0 5 (LED 05 )/TxD2
P1 2 /SCLK1
P2 5 /AN 5
P2 6 /AN 6
P1 3 /SRDY1
P1 4 /CNTR0
NC
P2
2 /AN 2
NC
P2
1 /AN 1
P2 0 /AN 0
P3 1 (LED 11 )/CMP 2
P3 6 (LED 16 )/INT 1
P2 3 /AN 3
P2 4 /AN 4
P0 6 (LED 06 )/SCLK2
P0 7 (LED 07 )/SRDY2
RESET
M37542RSS
NC
P3 5 (LED 15 )
P3
4 (LED 14 )
P3
3 (LED 13 )/INT 1
P3 2 (LED 12 )/CMP 3
NC
P1
0 /R X D 1 /CAP 0
P1 1 /T X D 1
NC
NC
P2 7 /AN 7
P3 7 (LED 17 )/INT 0
P0 0 (LED 00 )/CAP 0
P0 1 (LED 01 )/CMP 0
P0 2 (LED 02 )/CMP 1
P0 3 (LED 03 )/TX OUT

7542 Group
Rev.3.02 Oct 31, 2006 Page 5 of 134
REJ03B0006-0302
Table 1 Performance overview Parameter 71
0.25 µs
(Minimum instruction, oscillation frequency 8 MHz: double-speed mode)
8 MHz (max.)
8 K to 16 K bytes
384 to 512 bytes
16 K to 32 K + 4 K bytes
1024 bytes
•8-bit ✕3, 5-bit ✕1 (8-bit ✕1, 6-bit ✕2, 5-bit ✕1 for 32-pin version and
PWQN0036KA-A package version)
18 sources, 16 vectors
•8-bit ✕2, 16-bit ✕2
4 channel
2 channel
8-bit ✕2 (UART or clock synchronous)
10-bit ✕8 channel
(6 channel for 32-pin version and PWQN0036KA-A package version)
16-bit ✕1
Built-in
(external ceramic resonator or quartz-crystal oscillator, RC oscillation available)
(Low consumption current by on-chip oscillator available)
4.0 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
4.5 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
27.5 mW (Typ.)
24.0 mW (Typ.)
-20 to 85 °C
-40 to 85 °C
-40 to 125 °C (Note 2)
CMOS sillicon gate
32-pin plastic molded SDIP/LQFP, 36-pin plastic molded SSOP/WQFN
Number of basic instructions
Instruction execution time
Oscillation frequency
Memory sizes Mask ROM ROM
RAM
FLASH ROM ROM
RAM
I/O port P0, P1, P2, P3
Interrupts
Timer
Output compare
Input capture
Serial interface
A/D converter
Watchdog timer
Clock generating circuit
Power source High-speed mode At 8MHz Mask ROM
voltage Middle-speed mode oscillation FLASH ROM
(at ceramic At 4MHz Mask ROM
resonance) oscillation FLASH ROM
At 2MHz Mask ROM
oscillation FLASH ROM
(Note 1)
Double-speed mode At 8MHz Mask ROM
oscillation FLASH ROM
At 6.5MHz Mask ROM
oscillation FLASH ROM
At 2MHz Mask ROM
oscillation FLASH ROM
At 1MHz Mask ROM
oscillation FLASH ROM
(Note 1)
Power source High-speed mode At 4MHz Mask ROM
voltage Middle-speed mode oscillation FLASH ROM
(at RC oscillation) At 2MHz Mask ROM
oscillation FLASH ROM
At 1MHz Mask ROM
oscillation FLASH ROM
(Note 1)
Power dissipation Mask ROM
FLASH ROM
Operating General purpose
temperature Extended operating temperature
range Extended operating temperature 125 °C version
Device structure
Package
Function
Notes 1: In the Extended operating temperature version and Extended operating temperature 125 °C version, these are not standardized.
2: In this version, the operating temperature range and total time are limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.

7542 Group
Rev.3.02 Oct 31, 2006 Page 6 of 134
REJ03B0006-0302
FUNCTIONAL BLOCK
Fig. 6 Functional block diagram (Package type: PLQP0032GB-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PLQP0032GB-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
87
CNV
SS
P1(5)
30 28 26
29 27
32 31
P2(6)
P3(6)
1215 13
5
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
910
42
31
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
14
INT
0
1617
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23 21 19
24 22 20 18
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
Input
Capture Output
Compare
INT
1

7542 Group
Rev.3.02 Oct 31, 2006 Page 7 of 134
REJ03B0006-0302
Fig. 7 Functional block diagram (Package type: PRSP0036GA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
18
RESET
13
V
CC
15 14
CNV
SS
P1(5)
31
35
236
76
P2(8)
P3(8)
2124 22
12
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
16 17
11 9
10 8
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
23
INT
0
2526
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
34 32 30 28
33 31 29 27
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
INT
1
1920 54
Input
Capture Output
Compare

7542 Group
Rev.3.02 Oct 31, 2006 Page 8 of 134
REJ03B0006-0302
Fig. 8 Functional block diagram (Package type: PRDP0032BA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PRDP0032BA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
16
RESET
11
V
CC
13 12
CNV
SS
P1(5)
3131
232
P2(6)
P3(6)
17
20 18
10
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
14 15
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
19
INT
0
2122
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23
24
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
INT
1
28 26
27
3029
4756
89
Input
Capture Output
Compare

7542 Group
Rev.3.02 Oct 31, 2006 Page 9 of 134
REJ03B0006-0302
Fig. 9 Functional block diagram (Package type: PWQN0036KA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PWQN0036KA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
13
RESET
6
V
CC
87
CNV
SS
P1(5)
34 32 30
33 31
36 35
P2(6)
P3(6)
1417 15
5
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
11 12
42
31
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
16
INT
0
2021
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23
24 22
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
Input
Capture Output
Compare
INT
1
29 27
28 26

7542 Group
Rev.3.02 Oct 31, 2006 Page 10 of 134
REJ03B0006-0302
PIN DESCRIPTION
Table 2 Pin description Function
Mask ROM version (Note 1) Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
FLASH ROM version Apply voltage of 2.7 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A/D converter.
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit.
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
• For using RC oscillator, short between the X IN and X OUT pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open.
Function expect a port function
Name
Power source
Analog refer-
ence voltage
CNVss
Reset input
Clock input
I/O port P0
I/O port P1
I/O port P2
(Note 2)
I/O port P3
(Note 3)
Pin
Vcc, Vss
VREF
CNVss
RESET
XIN
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
P04(LED04)/RxD2
P05(LED05)/TxD2
P06(LED06)/SCLK2
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0–P27/AN7
P30(LED10)/CAP1
P31(LED11)/CMP2
P32(LED12)/CMP3
P33(LED13)/INT1
P34(LED14)
P35(LED15)
P36(LED16)/INT1
P37(LED17)/INT0
Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version.
2: P26/AN6and P27/AN7do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P2 is a 6-bit I/O port.
3: P35and P36/INT1do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P3 is a 6-bit I/O port.
• Capture function pin
• Compare function pin
• Timer X function pin
• Serial I/O2 function pin
• Serial I/O1 function pin
• Capture function pin
• Serial I/O1 function pin
• Timer X function pin
• Input pins for A/D converter
• Capture function pin
• Compare function pin
• Interrupt input pin
• Interrupt input pin
•8-bit I/O port.
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
• High drive capacity for LED drive port can be selected by program.
•5-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12and P13
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched
for P36and P37).
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
• High drive capacity for LED drive port can be selected by program.
XOUT Clock output
• Key-input
(key-on
wake up
interrupt
input) pin

7542 Group
Rev.3.02 Oct 31, 2006 Page 11 of 134
REJ03B0006-0302
GROUP EXPANSION
Renesas plans to expand the 7542 group as follow:
Memory type
Support for Mask ROM version, Flash memory version, and Emu-
lator MCU .
Memory size
Flash memory size ...................................... 16 to 32 K + 4 K bytes
Mask ROM size ................................................... 8 K to 16 K bytes
RAM size ............................................................ 384 to 1024 bytes
Package
PRDP0032BA-A ..................................32-pin plastic molded SDIP
PLQP0032GB-A .......... 0.8 mm-pitch 32-pin plastic molded LQFP
PRSP0036GA-A .......... 0.8 mm-pitch 36-pin plastic molded SSOP
PWQN0036KA-A ........ 0.5 mm-pitch 36-pin plastic molded WQFN
42S1M....................................42-pin shrink ceramic PIGGY BACK
Fig. 10 Memory expansion plan
384
32K
+4K
ROM size
(bytes)
RAM size
(bytes)
512 1024
16K
0
M37542F8
M37542M4
M37542M4T
8K
M37542F8T
M37542F8V
M37542M2T
M37542M2
M37542M2V
M37542M4V
16K
+4K M37542F4

7542 Group
Rev.3.02 Oct 31, 2006 Page 12 of 134
REJ03B0006-0302
Currently supported products are listed below.
Table 3 List of supported products
Product ROM size (bytes)
ROM size for User ( )
8192
(8062)
16384
(16254)
16384 + 4096
(Note 2)
32768 + 4096
(Note 2)
RAM size
(bytes)
384
512
1024
1024
1024
Package
PRDP0032BA-A
PWQN0036KA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PWQN0036KA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PRSP0036GA-A
PLQP0032GB-A
PWQN0036KA-A
42S1M
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Flash memory version (extended operating temperature version)
Flash memory version (extended operating temperature 125 °C version)
Flash memory version
Flash memory version (extended operating temperature version)
Flash memory version (extended operating temperature 125 °C version)
Flash memory version
Emulator MCU
M37542M2-XXXSP
M37542M2-XXXHP
M37542M2-XXXFP
M37542M2T-XXXFP
M37542M2V-XXXFP
M37542M2-XXXGP
M37542M2T-XXXGP
M37542M2V-XXXGP
M37542M4-XXXSP
M37542M4-XXXHP
M37542M4-XXXFP
M37542M4T-XXXFP
M37542M4V-XXXFP
M37542M4-XXXGP
M37542M4T-XXXGP
M37542M4V-XXXGP
M37542F4SP
M37542F4FP
M37542F4GP
M37542F8SP
M37542F8FP
M37542F8TFP
M37542F8VFP
M37542F8GP
M37542F8TGP
M37542F8VGP
M37542F8HP
(Note)
M37542RSS
Notes 1: Only ES version (MP: no plan)
2: ROM size includes the ID code area.

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REJ03B0006-0302
b7 b0
X
b7 b0
S
b7 b0
Y
b7 b0
PCL
Processor Status Register (PS)
Carry Flag
b7 b0
b7 b0
A
b15 PCH
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
CZIDBTVN
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing reg-
ister contents onto the stack and popping them from the stack are
shown in Fig. 12.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit
registers PCHand PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 11 740 Family CPU register structure

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REJ03B0006-0302
Execute JSR
On-going Routine
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
Execute RTS
(PCL)M(S)
(S) (S – 1)
(S) (S + 1)
(S) (S + 1)
(PCH)M(S)
Subroutine
Restore Return
Address
Store Return Address
on Stack M (S) (PS)
Execute RTI
(PS) M (S)
(S) (S – 1)
(S) (S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
(PCL)M(S)
(S) (S + 1)
(S) (S + 1)
(PCH)M(S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 12 Register push and pop at interrupt generation and subroutine call

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REJ03B0006-0302
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data trans-
fers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory lo-
cation 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal ad-
dressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location oper-
ated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–

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REJ03B0006-0302
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit, etc..
This register is allocated at address 003B16.
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program af-
ter releasing Reset in the following method.
Fig. 14 Switching method of CPU mode register
Fig. 13 Structure of CPU mode register
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
CPU mode register
(CPUM: address 003B
16 , initial value: 80 16 )
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
IN )/2 (High-speed mode)
0 1 : f(φ) = f(X
IN )/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(φ) = f(X
IN ) (Double-speed mode)(Note 2)
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
X
IN oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1
Not available
b7 b0
2: These bits are used only when a ceramic oscillation is selected.
Note 1: These bits can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to bits. However, by reset bits are
initialized and can be rewritten, again.
(It is not disable to write any data to bits for emulator MCU
“M37542RSS”.)
Do not use these when an RC oscillation is selected.
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Start with an on-chip oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
Select 1/1, 1/2, 1/8 or on-chip oscillator.
Wait by on-chip oscillator operation
until establishment of oscillator clock
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from an on-chip oscillator meets the
requirement).
Note: After system is released from reset, an on-chip oscillator turns active automatically
and system operation is started.

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REJ03B0006-0302
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
The reserved ROM area can program/erase in the flash memory
version.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 15 Memory map diagram
0100 16
0000 16
0040 16
0440 16
FF00 16
FFDC 16
FFFE 16
FFFF 16
384
512
1024
XXXX
16
01BF16
023F 16
043F 16
8192
16384
32768
E00016
C000 16
8000 16
E08016
C080 16
8080 16
YYYY 16
ZZZZ 16
RAM
ROM
Reserved area
SFR area
Not used
Interrupt vector area
ROM area
Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM capacity
(bytes) address
XXXX16
ROM capacity
(bytes) address
YYYY16
Reserved ROM area
address
ZZZZ16
Not used
SFR area (Note 1)
0FE0
16
0FFF 16
Notes 1: Only flash memory version has this SFR area.
2: The reserved ROM area can program/erase in the flash memory version.
Note the difference of the mask version.

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REJ03B0006-0302
Fig. 16 Memory map of special function register (SFR)
Notes 1: Do not access to the SFR area including nothing.
2: Only flash memory version has this SFR area.
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control register (PULL)
Transmit 1 /Receive 1 buffer register (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Port P1P3 control register (P1P3C)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer count source set register (TCSS)
A/D conversion register (low-order) (ADL)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer X mode register
(TXM)
Prescaler X
(PREX)
Timer X
(TX)
Serial I/O2 control register (SIO2CON)
UART2 control register (UART2CON)
A/D control register (ADCON)
A/D conversion register (high-order) (ADH)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Timer A, B mode register (TABM)
Capture/compare port register (CCPR)
Timer source selection register (TMSR)
Capture mode register (CAPM)
Compare output mode register (CMOM)
Capture/compare status register (CCSR)
Compare interrupt source set register (CISR)
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
On-chip oscillation division ratio selection register (RODR)
Baud rate generator 2 (BRG2)
Timer A (low-order) (TAL)
Timer A (high-order) (TAH)
Timer B (low-order) (TBL)
Timer B (high-order) (TBH)
Transmit 2 / Receive 2 buffer register (TB2/RB2)
Serial I/O2 status register (SIO2STS)
Port P0P3 drive capacity control register (DCCR)
Compare register re-load register (CMPR)
Capture software trigger register (CSTR)
Capture/compare register R/W pointer (CCRP)
Compare register (high-order) (CMPH)
Compare register (low-order) (CMPL)
Capture register 1 (high-order) (CAP1H)
Capture register 1 (low-order) (CAP1L)
Capture register 0 (high-order) (CAP0H)
Capture register 0 (low-order) (CAP0L)
Interrupt source set register (INTSET)
Interrupt source discrimination register (INTDIS)
Reserved
Reserved
Reserved
0FE016
0FE116
Flash memory control register 0 (FMCR0) (Note 2)
Flash memory control register 1 (FMCR1) (Note 2)
0FE216 Flash memory control register 2 (FMCR2) (Note 2)

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REJ03B0006-0302
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
Note: P26/AN6, P27/AN7, P35and P36do not exist for the 32-pin version
and PWQN0036KA-A package.
Accordingly, the following settings are required;
• Select P33for the INT1function.
• Set direction registers of ports P26and P27to output.
• Set direction registers of ports P35and P36to output.
[Port P0P3 drive capacity control register] DCCR
By setting the Port P0P3 drive capacity control register (address
001516), the drive capacity of the N-channel output transistor for
the port P0 and port P3 can be selected.
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P13, P36, and P37by program.
Fig. 19 Structure of port P1P3 control register
Fig. 18 Structure of pull-up control register
Port P1P3 control register
(P1P3C: address 0017
16 , initial value: 00 16 )
b7 b0
Note: Keep setting the P3 6 /INT 1 input level selection bit
to “0” (initial value) for 32-pin version and 36PJW-A package.
Not used
1 : TTL level
0 : CMOS level
P1
0 ,P1 2 ,P1 3 input level selection bit
1 : TTL level
0 : CMOS level
P3
6 /INT 1 input level selection bit
1 : TTL level
0 : CMOS level
P3
7 /INT 0 input level selection bit
Pull-up control register
(PULL: address 001616, initial value: 0016)
P
00
p u
l
l
- u p c o n t r o
l
b
i
t
P 01,
P 02 p u l l - u p c o n t r o l b i t
P 03–P
07 p u l l - u p c o n t r o l b i t
P 30 p
u l l - u p c o n t r o l b i t
P 31,
P 32 p u l l - u p c o n t r o l b i t
P 33 p
u l l - u p c o n t r o l b i t
P 34,
P 35 p u l l - u p c o n t r o l b i t
P 36,
P 37 p u l l - u p c o n t r o l b i t
b
7 b 0
0
: P u l l - u p O f f
1 : P u l l - u p O n
N
o t e : P i n s s e t t o o u t p u t p o r t s a r e d i s c o n n e c t e d f r o m p u l l - u p c o n t r o l .
P
o r t P 0 P 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r
( D C C R : a d d r e s s 0 0 1 5
1 6 , i n i t i a l v a l u e : 0 0 1 6 )
P
o r t
P
0
0
d
r
i
v e c a p a c
i
t y
b
i
t
P o r t s P 0
1 , P 0 2 d r i v e c a p a c i t y b i t
P o r t s P 0
3 –P 0 7 d r i v e c a p a c i t y b i t
P o r t P 3
0 d r i v e c a p a c i t y b i t
P o r t s P 3
1, P 3 2 d r i v e c a p a c i t y b i t
P o r t P 3
3 d r i v e c a p a c i t y b i t
P o r t s P 3
4 , P 3 5 d r i v e c a p a c i t y b i t
P o r t s P 3
6 , P 3 7 d r i v e c a p a c i t y b i t
b
7 b 0
0
: L o w
1 : H i g h
N
o t e : N u m b e r o f L E D d r i v e p o r t ( d r i v e c a p a c i t y i s H I G H ) i s 8 - p o r t .
Fig. 17 Structure of port P0P3 drive capacity control register

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REJ03B0006-0302
Table 6 I/O port function table
Pin
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
P04(LED04)/RxD2
P05(LED05)/TxD2
P06(LED06)/SCLK2
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0–P27/AN7
P30(LED10)/CAP1
P31(LED11)/CMP2
P32(LED12)/CMP3
P33(LED13)/INT1
P34(LED14)
P35(LED15)
P36(LED16)/INT1
P37(LED17)/INT0
I/O format
•CMOS compatible
input level (Note 1)
•CMOS 3-state output
Non-port function
• Capture function input
• Key input interrupt
• Compare function output
• Key input interrupt
• Timer X function output
• Key input interrupt
• Serial I/O2 function input/output
• Key input interrupt
• Serial I/O1 function input
• Capture function input
• Serial I/O1 function input/output
• Timer X function input/output
• External interrupt input
• A/D conversion input
• Capture function input
• Compare function output
• External interrupt input
• External interrupt input
SFRs related each pin
Capture/Compare port register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Timer X mode register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O1 control register
Capture/Compare port register
Port P1P3 control register
Serial I/O1 control register
Serial I/O1 control register
Port P1P3 control register
Serial I/O1 control register
Port P1P3 control register
Timer X mode register
A/D control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Pull-up control register
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Port P1P3 control register
Diagram
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
Notes 1: Ports P10, P12, P13, P36, and P37are CMOS/TTL level.
2: P26/AN6and P27/AN7do not exist for the 32-pin version and PWQN0036KA-A package.
3: P35and P36/INT1do not exist for the 32-pin version and PWQN0036KA-A package.
Name
I/O port P0
I/O port P1
I/O port P2
(Note 2)
I/O port P3
(Note 3)