Renesas DA1459 PRO Devkit Series User manual

User Manual
DA1459x PRO-Development Kit
UM-Β-167
Abstract
This is the description of the DA1459x Development Kit Pro hardware which provides a tested
reference platform, access to all signals for connecting peripherals and advanced debugging
features.

UM-Β-167
DA1459x PRO-Development Kit
User Manual
Revision 1.0
Nov 15, 2023
CFR0012
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© 2023 Renesas Electronics
Contents
Abstract................................................................................................................................................ 1
Contents............................................................................................................................................... 2
Figures.................................................................................................................................................. 3
Tables ................................................................................................................................................... 3
1 Terms and Definitions................................................................................................................... 5
2 References..................................................................................................................................... 5
3 Introduction.................................................................................................................................... 6
3.1 Features of DA1459x PRO-DB............................................................................................. 6
3.2 Features of DA1469x PRO-MB............................................................................................. 7
3.3 PRO Devkit hardware block diagram.................................................................................... 7
4 Getting to know DA1459x PRO Devkit ........................................................................................ 8
4.1 The Hardware components of the DA1459x PRO Devkit..................................................... 8
4.1.1 Hardware setup of DA1459x Devkit with PMM2 ................................................... 8
4.1.2 Hardware setup of DA1459x Devkit without PMM2 .............................................. 9
4.1.3 Jumper settings ................................................................................................... 10
4.2 DA14592 PRO-DB.............................................................................................................. 11
4.2.2 XTAL, 32 MHz (Y1)..............................................................................................16
4.2.3 XTAL, 32 kHz (Y2)............................................................................................... 16
4.2.4 Debugging connector (J4) ................................................................................... 16
4.2.5 QSPI external memory (U2) ................................................................................ 17
4.2.6 General purpose LED (D1)..................................................................................18
4.2.7 The RESET on DA14592 PRO-Daughterboard ..................................................19
4.2.8 Power section of DA14592 PRO-Daughterboard................................................ 19
4.2.9 RF section............................................................................................................21
4.3 DA1459x PRO-MB..............................................................................................................21
4.3.1 DA1459x signals distribution on PRO-Motherboard............................................23
4.3.2 USB port (USB1) and USB HUB (U11) ............................................................... 25
4.3.3 USB to UART (U12)............................................................................................. 25
4.3.4 USB to SWD (U5)................................................................................................26
4.3.5 Debugging signals, DIP switch and Level translation..........................................27
4.3.6 Reset.................................................................................................................... 28
4.3.7 Push button (K1).................................................................................................. 29
4.3.8 MikroBUS and PMOD interface........................................................................... 29
4.3.9 Power section ...................................................................................................... 31
4.3.10 Measurements and software triggers .................................................................. 32
4.4 The Power measurement module 2 (PMM2), (500-29-x)...................................................36
4.4.1 Accuracy of Current Measurement for VBAT System (VLDO)............................ 39
5 Schematics................................................................................................................................... 41
A.1 DA1459x PRO-Motherboard schematic.............................................................................. 41
A.2 DA1459x_db_fcqfn52 schematic ........................................................................................ 46
A.3 DA1459x-db-wlcsp39 schematic.........................................................................................48
Revision History ................................................................................................................................ 50

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Figures
Figure 1. DA1459x PRO Devkit with PRO-MB and the PRO-DB.......................................................... 6
Figure 2. System block diagram............................................................................................................ 7
Figure 3. DA1459x PRO Devkit components........................................................................................ 8
Figure 4: Default hardware setup of DA1459x PRO-Devkit with PMM2............................................... 9
Figure 5. System block diagram of DA14592 PRO-DB (32 KHz only on FCQFN52)......................... 12
Figure 6. TOP side, WLCSP39 PRO-DB (left), FCQFN52 PRO-DB (right)........................................12
Figure 7. BOTTOM side, WLCSP39 PRO-DB (left), FCQFN52 PRO-DB (right)................................ 13
Figure 8. DA14592 Interface header of WLCSP39 to DA1459x PRO-Motherboard .......................... 14
Figure 9. DA1459x Interface header of FCQFN52 to DA1459x PRO-Motherboard...........................15
Figure 10. The debugging header, J4 .................................................................................................17
Figure 11. The External QSPI memory, (U2) place holder ................................................................. 18
Figure 12. External Memory placeholder and the components .......................................................... 18
Figure 13. Red LED (D1) circuitry ....................................................................................................... 19
Figure 14. Reset circuitry on PRO-Daughterboard .............................................................................19
Figure 15. DA14592 SoC, power pins................................................................................................. 20
Figure 16. SW1 (left), available battery sockets on the bottom side of the daughterboards (right)....20
Figure 17. RF section of DA14592 PRO-DB.......................................................................................21
Figure 18. DA1459x PRO-Motherboard block diagram ...................................................................... 22
Figure 19. DA1459x PRO-Motherboard, 469-16-x.............................................................................. 23
Figure 20. USB HUB circuitry of DA14531 PRO-MB .......................................................................... 25
Figure 21. USB to UART (U12)...........................................................................................................26
Figure 22. USB to SWD (U4)............................................................................................................... 27
Figure 23. Voltage level translation circuit...........................................................................................28
Figure 24. RESET circuit on DA1459x PRO-MB ................................................................................29
Figure 25. General purpose Push button K1....................................................................................... 29
Figure 26. MikroBus and PMOD ......................................................................................................... 30
Figure 27. DA1459x PRO MB Power section block diagram block..................................................... 31
Figure 28. DA14592x PRO-Motherboard Power section .................................................................... 32
Figure 29. Power measurement module (PMM2) block diagram........................................................33
Figure 30. Current measurement socket (M2) ....................................................................................34
Figure 31. Selection jumper block (J24) and Buffer MOSFETS for I/O levels compatibility ...............35
Figure 32. DA1459x waveforms, captured from Power profiler of SmartSnippet Toolbox ................. 36
Figure 33. PMM2 current measurement circuit PMM2........................................................................ 37
Figure 34. PMM2 on board peripherals (power supply, memory and so on)...................................... 38
Figure 35. Current measurement unit PCBA (TOP)............................................................................ 39
Figure 36. Normal mode (1 μA to 640 mA at 3.3 V) data after offset calibration................................ 40
Figure 37. Hibernation mode (100 nA to 60 μA at 3.3 V) data after offset calibration ........................40
Figure 38. DA1459x PRO-Motherboard schematic, modification history page................................... 41
Figure 39. DA1459x PRO-Motherboard schematic, connectivity, and level translators .....................42
Figure 40. DA1459x PRO-Motherboard schematic, SWD implementation.........................................43
Figure 41. DA1459x PRO-Motherboard schematic, PMM2 interface and software trigger buffers .... 44
Figure 42. DA1459x PRO-Motherboard schematic, USB Hub, UART to USB and power supply...... 45
Figure 43. DA1459x_db_fcqfn52, modification history page...............................................................46
Figure 44. DA1459x_db_fcqfn52, the circuit ....................................................................................... 47
Figure 45. DA1459x-db-wlcsp39, modification history page...............................................................48
Figure 46. DA1459x-db-wlcsp39, the circuit........................................................................................ 49
Tables
Table 1. Headers and Jumper settings of DA1459x PRO-Devkit ....................................................... 10
Table 2. DA14592 ordering information ..............................................................................................11
Table 3. DA14592 WLCSP39 pins assignment...................................................................................14
Table 4: DA1459x FCQFN52 pins assignment ................................................................................... 15
Table 5. Crystal specification............................................................................................................... 16

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Table 6. Debugging header –pins assignment...................................................................................17
Table 7. DA1459x signal connectivity on PRO-Motherboard..............................................................24
Table 8. Signal mapping on DIP switch (S1)....................................................................................... 27
Table 9. MikroBUS and PMOD signals ...............................................................................................31
Table 10. Monitored power sources....................................................................................................34
Table 11. Accuracy of the current measurement circuit...................................................................... 40

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1 Terms and Definitions
PCB Printed Circuit Board
SDK Software Development Kit
DK Development Kit
SWD Serial Wire Debug
PRO Devkit Professional Development Kit
PRO-MB Professional Motherboard
PRO-DB Professional Daughterboard
SoC System on Chip
2 References
[1] DA1459x, Datasheet, Renesas Electronics.
Note 1 References are for the latest published version, unless otherwise indicated.

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3 Introduction
This document describes the hardware of DA1459x PRO development kit (DK). The DA1459x Pro
DK is available as a motherboard, two variants of a daughterboard (FCQFN52/WLCSP39) and the
power measurement module PMM2, Figure 1.
The PRO development kit when combined with the DA1459x SDK and Smart Snippets tools,
provides an easy to use and complete platform for software/hardware development.
Figure 1. DA1459x PRO Devkit with PRO-MB and the PRO-DB
3.1 Features of DA1459x PRO-DB
●Embedded printed antenna
●Coaxial switch for conducted RF measurements
●Option for QSPI-Flash memory or PSRAM
●Reset button
●LED
●Flexible battery options
●Crystals 32 MHz, 32.768 KHz (optional –only for FCQFN52 package)
●Support for coin cell battery

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3.2 Features of DA1469x PRO-MB
●Mating connectors for connecting a DA1459x PRO-DB which hosts either DA1459x FCQFN52 or
WLCSP39 SoC
●Headers for I/O monitoring and expandability
●Option to support MikroBUS click boards
●Provisions for automated test
●On-board basic peripherals for demo and development
●JTAG(SWD) debugger and connectivity to PC
3.3 PRO Devkit hardware block diagram
USB
HUB
(U11)
J-Link
(U25)
Dip Switch
(S1)
FTDI
(U12)
Breakout Headers
(J3, J4)
MicroBus
(J17, J18)
USB
CON
LDO
(U5)PMM2
Daughterboard
500-29-E
Level Translator
Level Translator
User
Button
POD
(J20)
z
CIB
DA1459x
Reset
PWR DA1459x PRO-
Daughterboard
LED
Antenna
DA1459x PRO-Motherboard
469-16-x
Trigger
selection
Figure 2. System block diagram

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4 Getting to know DA1459x PRO Devkit
4.1 The Hardware components of the DA1459x PRO Devkit
In this document we focus on the DA1459x DK PRO which consists of the following parts:
●PRO-Motherboard, DA1459x PRO-MB: PCBA reference number 469-16-D
●PRO-Daughterboard (two options, interchangeable)
○FCQFN52 PRO-DB: it uses DA1459x -FCQFN52. PCBA reference number 469-08-B
○WLCSP39 PRO-DB: it uses DA1459x-WLCSP39. PCBA reference number 469-07-B
●Power measurement module, PMM2. PCBA reference number 500-29-E
Figure 3. DA1459x PRO Devkit components
4.1.1 Hardware setup of DA1459x Devkit with PMM2
●Mount PRO-Daughterboard (469-08-x or 469-07-x). Please ensure the proper orientation, by
checking the alignment marks of the two PCBAs
●Mount PMM2 as it is shown below. The mounting screw (M2x4, D5x0.5 or similar) must be also
applied.
●Mount two jumpers on J9, between pins 1 and 2 and 3 and 4.

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Figure 4: Default hardware setup of DA1459x PRO-Devkit with PMM2
4.1.2 Hardware setup of DA1459x Devkit without PMM2
●Mount PRO-Daughterboard (469-08-x or 469-07-x). Ensure the proper orientation by checking
the alignment marks of the two PCBAs.
●Mount one jumper on J9, between pins 2 and 3.

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User Manual
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Figure 5. Hardware setup of DA1459x PRO-Devkit without PMM2
4.1.3 Jumper settings
Table 1. Headers and Jumper settings of DA1459x PRO-Devkit
HDR
Function of headers
Jumper Options
Default Jumper
setting
J5
DA1459x input voltage,
generated from LDO (U5)
1.8 V
Mount pos. 1-2
Or
No mount 1-2
Mounted 2-3
3.0 V
Mount pos. 2-3
J8
K1, general purpose push
button and (pins 1-2)
Force enable
Power_Enable (3-4), for
supplying PRO-Devkit with
a power source without
USB data connection
Enable K1
Mount pos. 1-2
Mounted 1-2
Force Power_Enable
Mount pos. 3-4
No mounted 3-4
J9
Power Measurement
Module PMM2
PMM2 Bypass
Mount pos. 2-3
PMM2 mounted:
Mounted 1-2
Mounted 3-4
PMM2 no mounted:
Mounted 2-3
PMM2 Enable
Mount pos.1-2
Mount pos. 3-4
J10
Reset source options
Activate Reset driven from
Debugger (T_Reset)
Mount pos.1-2
Mounted 1-2

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HDR
Function of headers
Jumper Options
Default Jumper
setting
Activate Reset driven from
serial interface (U_RSTn)
Mount pos. 3-4
No mounted 3-4
J15
Enable Pullups of I2C for
PMOD and MikroBUS
Disable I2C
No jumper Mount
Power Pull-ups with 3.3 V
Mount pos.1-2
No mounted 1-2
Power Pull-ups with 5 V
Mount pos.2-3
No mounted 3-4
J16
Enable I2C signals for
PMOD and MikroBUS
Enable SDA
Mount pos.1-2
No mounted 1-2
Enable SCL
Mount pos.3-4
No mounted 3-4
J24
Software Trigger activation
TRIG_0 mapped to P0_10
TRIG_1 mapped to P0_08
TRIG_2 mapped to P1_01
TRIG_3 mapped to P1_02
TRIG_4 mapped to P0_12
TRIG_5 mapped to P0_01
TRIG_6 mapped to P0_14
TRIG_7 mapped to P1_04
Mount pos.1-2
Mount pos.3-4
Mount pos.5-6
Mount pos.7-8
Mount pos. 9-10
Mount pos.11-12
Mount pos.13-14
Mount pos.15-16
Mounted 1-2
For enabling I2C for MikroBUS or PMOD, both J15 and J16 must be set.
4.2 DA14592 PRO-DB
On PRO-daughterboard, system consists of DA14592 SoC, crystals 32 MHz and 32 kHz (for
FCQFN52 package only)), Switch SW1 for power source selection, radio section (printed antenna
and RF connector), LED and RESET button (Figure 5). There are two versions of the DA14592 SoC,
WLCSP39 and FCQFN52 with the ordering information in Table 2.
Table 2. DA14592 ordering information
Part Number
Package
Size (mm)
DA14592-01000O92
WLCSP39
3.32 x 2.48 x 0.37
DA14592-010006F2
FCQFN52
5.1 x 4.3 x 0.78
There two variants of PRO-daughterboard are (Figure 6):
●for the FCQFN52 package (469-08-x), and
●for the WLCSP39 package (469-07-x).
The differences between the two daughterboards, apart from layout differences, is that the FCQFN52
daughterboard exposes more GPIOs to the motherboard and provides a place holder for a 32 kHz
crystal. Both variants provide a place holder for external Flash.
On power section, both variants provide a place holder for a coin cell battery. DA1459x SoC can be
supplied from the battery through switch SW1.

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DA14592
J1 J2
J4
Y1
32MHz
Y2–No Pop
32.768KHz
(FCQFN52)
QSPI Ext.
Memory
U2 -NoPop
GPIO
QSPI
Coin cell
3.0V
BAT1
VLDO
VBAT
SW1
Debug
M33/CMAC
Reset
Circuit
K2
VDD,Vdcdc,
Vddio
Printed
Antenna
D1
LED
L1
Figure 5. System block diagram of DA14592 PRO-DB (32 kHz only on FCQFN52)
1
233
4
5
6
7
89
11 11 11 11
6
7
89
1
21245
10
10
Figure 6. TOP side, WLCSP39 PRO-DB (left), FCQFN52 PRO-DB (right)

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13
14 14
15
16
13
14 14
16
15
Figure 7. BOTTOM side, WLCSP39 PRO-DB (left), FCQFN52 PRO-DB (right)
1. DA1459x SoC
2. Power Switch, (SW1)
3. 32 MHz crystal (Y1)
4. External QSPI memory (U2)
5. Reset push button (K2)
6. Debugging connector (J4)
7. Printed antenna
8. RF electromechanical switch (J7)
9. LED (D1)
10. Power inductor (L1)
11. Mounting marking
12. 32 kHz crystal (Y2) –applied (not populated) only for FCQFN52 package.
13. Place holder for Coin cell Battery (BT1)
14. Mating connectors to PRO-MB (J1, J2)
15. Place holder for 2-pins battery connector (J6)
16. ESD diode for Debugging connector.
4.2.1.1 WLCSP39 based PRO-Daughterboard
Signals of DA14592 WLCSP39 (da1459x-db-wlcsp39_469-07-x) are routed to J1, J2 interface board
(mating) connectors on the DA1459x Daughterboard. See Figure 8.

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Figure 8. DA14592 Interface header of WLCSP39 to DA1459x PRO-Motherboard
Signals of DA1459x WLCSP39 are mapped to PRO-Motherboard.
Table 3describes the mapping of the signals.
Table 3. DA14592 WLCSP39 pins assignment
GPIO
GPIO multiplexing
Devkit Function
MikroBUS
PMOD
P0_0
QSPI_CLK
SCK
SCK
P0_1
QSPI_CS
TRIG_5
CS1#
P0_2
QSPI _D0
MOSI
MOSI
P0_3
QSPI _D1
MISO
MISO
P0_4
QSPI _D2
INT1
P0_5
QSPI _D3
RST1#
P0_6
M33_SWDIO
SWDIO
P0_7
M33_SWCLK
SWCLK
P0_8
CMAC_SWDIO/DIVN
TRIG_1
INT2
P0_9
CMAC_SWCLK
RST2#
P0_10
PWM_2/GPADC_2/SDADC_2
BUTTON/DTRIG_0
AN
P0_11
XTAL32M
UCTS
CS1#
P0_12
LPCLK/PWM_1
TRIG_4
PWM
P0_13
BOOT_UART_TX
UTX
P0_14
WAKEUP_1
TRIG_6
SCL
SCL
P0_15
BOOT_UART_RX
URX
RX
P1_0
PGA_INp/GPADC_0/SDADC_0
URTS
TX
P1_1
PGA_INn/GPADC_1/SDADC_1
TRIG_2
P1_2
RC32M/GPADC_3/SDADC_3
TRIG_3
SDA
SDA
4.2.1.2 FCQFN52 based PRO-Daughterboard
Signals of DA1459x FCQFN52 (da1459x_db_fcqfn52_469-08-x) are routed to J1, J2 interface board
(mating) connectors on the DA1459x Daughterboard. See Figure 9.

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Figure 9. DA1459x Interface header of FCQFN52 to DA1459x PRO-Motherboard
Signals of DA1459x FCQFN52 are mapped to DA1459x PRO-Motherboard. Table 4 describes the
mapping of the signals.
Table 4: DA1459x FCQFN52 pins assignment
GPIO
GPIO multiplexing
Devkit
Function
MikroBUS
PMOD
DBs Mating
Headers J1 and
J2 (Note 2)
P0_0
QSPI_CLK
SCK
SCK
J1.31
P0_1
QSPI_CS
TRIG_5
CS1#
J1.41
P0_2
QSPI _D0
MOSI
MOSI
J1.34
P0_3
QSPI _D1
MISO
MISO
J1.37
P0_4
QSPI _D2
INT1
J1.39
P0_5
QSPI _D3
RST1#
J1.33
P0_6
M33_SWDIO
SWDIO
J1.4
P0_7
M33_SWCLK
SWCLK
J1.6
P0_8
CMAC_SWDIO/DIVN
TRIG_1
INT2
J1.47
P0_9
CMAC_SWCLK
RST2#
J1.5
P0_10
PWM_2/GPADC_2/SDADC_2
BUTTON /
TRIG_0
AN
J1.32
P0_11
XTAL32M
UCTS
CS1#
J1.12
P0_12
LPCLK/PWM_1
TRIG_4
PWM
J1.3
P0_13
BOOT_UART_TX
UTX
J1.09
P0_14
WAKEUP_1
TRIG_6
SCL
SCL
J1.45
P0_15
BOOT_UART_RX
URX
RX
J1.10
P1_0
PGA_INp/GPADC_0/SDADC_0
URTS
TX
J2.15
P1_1
PGA_INn/GPADC_1/SDADC_1
TRIG_2
J2.18
P1_2
RC32M/GPADC_3/SDADC_3
TRIG_3
SDA
SDA
J2.13
P1_3
J2.16
P1_4
WAKEUP_2
TRIG_7
J2.5

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GPIO
GPIO multiplexing
Devkit
Function
MikroBUS
PMOD
DBs Mating
Headers J1 and
J2 (Note 2)
P1_5
GPADC_4 / SDADC_4 /
SDADC_REFp/ SDADC_INT_REF
J2.14
P1_6
GPADC_5/SDADC_5/SDADC_REFn
J2.23
P1_7
J2.20
P1_8
J2.41
P1_9
GPADC_6/SDADC_6
J2.26
P1_10
J2.24
P1_11
GPADC_7/SDADC_7
J2.36
P1_12
J2.28
P1_13
XTAL32km
J2.30
P1_14
XTAL32kp
J2.34
P1_15
J2.43
Note 2 QSPI (GPIO) pads input voltage must not exceed VDDIO voltage level since there is no backdrive
protection on those pads.
4.2.2 XTAL, 32 MHz (Y1)
The main clock of the system is generated from a 32 MHz crystal which is connected to the internal
crystal oscillator of DA1459x SoC.
The crystal used is the Murata XRCGB32M000F1H00R0 or XRCGB32M000F1S1AR0.
Table 5. Crystal specification
Item
Specification
Nominal Frequency
32.0000 MHz
Frequency Tolerance
±10 ppm max.
Frequency Shift by Temperature
±10 ppm/max. from initial value (-30 to +85°C)
Frequency Aging
±2 ppm max/year
Equivalent Series Resistance
60 Ω max. or 50 Ω max (1)
Load Capacitance
6.0±0.1 pF
Operating Temperature Range
-30 to +85°C
Size
2.0 x 1.6 mm
Note 1 60 Ω for XRCGB32M000F1H00R0
50 Ωfor XRCGB32M000F1S1AR0
4.2.3 XTAL, 32 kHz (Y2)
An optional 32kHz external crystal can be placed on the daughterboard. This crystal is not mandatory
as there is an internal RCX oscillator in DA1459x that can be used instead. In WLCSP PRO-
daughterboard this crystal is not placed, while in FCQFN daughterboard there is a placeholder, but
crystal is not populated.
4.2.4 Debugging connector (J4)
On both daughterboards there is an optional JTAG connector that can be used for debugging via
SWD or for communication via UART.

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Figure 10. The debugging header, J4
As described in the datasheet, DA1459x contains two processors, an ARM Cortex-M33TM and an
ARM Cortex-M0+TM. Both processors can be accessed from J4, through their SWD bus. By default,
the SWD of M33 is enabled. For enabling SWD bus of M0+, two resistors must be removed (R10,
R15) and two others to be mounted (R11, R13).
Table 6. Debugging header –pins assignment
Pin
No
Pin
Function
Default
Signals
Optional
Signals
Comments
1
UTX
P0_13
Through 100 Ω
2
URX
P0_15
Through 100 Ω
3
SWCLK
P0_7
(SWCLK_M33)
P0_9
(SWCLK_M0+)
To Enable optional signal:
solder R11/remove R15
4
SWDIO
P0_6
(SWDIO_M33)
P0_8
(SWDIO_M0+)
To Enable optional signal:
solder R13/remove R10
5
VPP
No Connect
6
RST
RST
Driven to DA14592 through
inverter
7
VDD
VBAT_IN
8
GND
GND
9
No
Connect
No Connect
10
GND
GND
SWD of M33 is also connected to the PRO-Motherboard onboard J-Link debugger. Consequently, by
enabling the SWD of M0+ connectivity on J4, you can access both processors (M33 and M0+) of
DA14592.
4.2.5 QSPI external memory (U2)
On both daughterboards an optional external QSPI memory place holder, U2 is applied. This is a
footprint for a SOP-8, 150 mils. By default, it is not populated as DA1459x contains an embedded
flash memory.

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Figure 11. The External QSPI memory, (U2) place holder
On the Software Development Kit (SDK) the following components are supported:
•Macronix MX25U3235, 32 MBit
•Winbond W25Q32JWIM, 32 MBit
•Winbond W25Q32JWIQ, 32 MBit
For enabling the external memory option, user can populate U2, C8 (=1 μF) and remove resistors
R1, R2 and R6 to R9 (=36 Ω) for isolating memory from PRO-Motherboard.
Figure 12. External Memory placeholder and the components
4.2.6 General purpose LED (D1)
On both daughterboards there is one red led (D1) that can be used for optical indications. LED is
driven from P1_1 through a N-FET.

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Figure 13. Red LED (D1) circuitry
4.2.7 The RESET on DA14592 PRO-Daughterboard
Reset is active low. If it is not driven low, nRst pin of DA14592 is set high by an internal pull up, 25 K,
to VBAT_IN.
On DA1459x PRO Devkit, there are four ways for activating Reset.
●By pressing button (K2).
●Through Debugger connector J4. As Reset signal of J4 is active high, a nFET is added.
●Through T-Reset signal on DA1459x PRO-Motherboard, see Section 4.3.6. This connected
directly (wired-OR) to DA1459x chip pin.
●Through U_RSTn signal on DA1459x PRO-Motherboard, see Section 4.3.6. This signal is tied
together with T_Reset and connected directly (wired-OR) to DA1459x chip pin. This option
requires additional software. By default, it is not enabled.
Figure 14. Reset circuitry on PRO-Daughterboard
4.2.8 Power section of DA14592 PRO-Daughterboard
The DA14592 has a complete integrated Power Management Unit (PMU). This includes a buck DC-
DC converter and several LDOs for the different power rails of the system. Voltage rails are:

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●VBAT: input voltage of the DA14592 SoC. VBAT is provided either from PRO-Motherboard or a
battery. Selection is done from SW1.
●VDCDC: produced from internal synchronous Single Inductance (L1) Single Output Buck DC-DC
converter with programmable output 1.1 V to 1.4 VDCDC.
●VDD: LDO (active and retention) for the digital core with 20 mA (2 mA on retention) driving
capability.
●VDDIO: LDO (active and retention) for the I/O-s with bypass functionality of 1.8 V voltage range.
Figure 15 shows the configuration of PMU on daughterboard.
The power section consists of a Switch (SW1) that can be used for selecting a power supply source
for the chip.
Figure 15. DA14592 SoC, power pins
There are two options available:
1. supply from LDO on PRO motherboard by setting SW1 to MB, see Figure 16,
2. supply directly from Battery by setting SW1 to Bat see Figure 16
Two Battery options are available:
a. Place holder for a Coin cell 2016 lithium battery socket (BT1) on the bottom layer of each
daughterboard. (Figure 16)
b. Place holder for a two pins Battery connector (J6).
Notice: Do not use a LiPo battery or DA1459x SoC is damaged. Absolute maximum voltage of
VBAT pin of DA14592 is 3.6 V.
Figure 16. SW1 (left), available battery sockets on the bottom side of the daughterboards
(right)