
Renesas RA Family RA4 Quick Design Guide
R01AN5988EU0100 Rev.1.00 Page 2 of 51
Jul.21.21
5.10 External Clock Input ..............................................................................................................................20
6. Reset Requirements and the Reset Circuit............................................................................21
6.1 Pin Reset...............................................................................................................................................22
6.2 Power-On Reset....................................................................................................................................22
6.3 VBATT-Selected Voltage Power-On Reset...........................................................................................22
6.4 Independent Watchdog Timer Reset.....................................................................................................23
6.5 Watchdog Timer Reset..........................................................................................................................23
6.6 Voltage-Monitoring Resets....................................................................................................................23
6.7 Deep Software Standby Reset..............................................................................................................23
6.8 Software Reset......................................................................................................................................23
6.9 Other Resets .........................................................................................................................................23
6.10 Determination of Cold/Warm Start ........................................................................................................23
6.11 Determining the Reset Source..............................................................................................................24
7. TrustZone Support.................................................................................................................24
7.1 Implementation of Arm TrustZone Technology.....................................................................................24
7.2 Emulator Support for TrustZone............................................................................................................26
7.2.1 Device Lifecycle Management ............................................................................................................28
8. Memory .................................................................................................................................29
8.1 SRAM ....................................................................................................................................................30
8.2 Standby SRAM......................................................................................................................................30
8.3 Peripheral I/O Registers........................................................................................................................31
8.4 On-Chip Flash Memory.........................................................................................................................31
8.4.1 Background Operation ........................................................................................................................32
8.4.2 ID Code Protection..............................................................................................................................32
8.4.3 Flash Block Protection.........................................................................................................................33
8.4.4 Memory Protection Unit.......................................................................................................................33
8.5 Restriction on Endianness.....................................................................................................................34
9. Register Write Protection.......................................................................................................34
10. I/O Port Configuration ...........................................................................................................35
10.1 Multifunction Pin Selection Design Strategies.......................................................................................35
10.2 Setting Up and Using a Pin as GPIO ....................................................................................................36
10.2.1 Internal Pull-Ups..................................................................................................................................37
10.2.2 Open-Drain Output..............................................................................................................................37
10.2.3 Drive Capacity.....................................................................................................................................37
10.3 Setting Up and Using Port Peripheral Functions...................................................................................38
10.4 Setting Up and Using IRQ Pins.............................................................................................................39
10.5 Unused Pins ..........................................................................................................................................40
10.6 Nonexistent Pins....................................................................................................................................41