Renesas V850 Series User manual

User’s Manual
www.renesas.com
V850E2/PG4-L
User’s Manual: Hardware
Renesas microcomputers
V850 Series
Jul 2014
32
Rev.1.02
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
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Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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(2012.4)

Notes for CMOS devices
(1) Voltage
application
wafeform at input
pin:
Waveform distortion due to input noise or a reflected wave may cause
malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through
the area between VIL (MAX) and VIH (MIN).
(2) Handling of
unused input pins: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due
to noise, etc., causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or
low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an
output pin. All handling related to unused pins must be judged separately for
each device and according to related specifications governing the device.
(3) Precaution
against ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it when it has occurred. Environmental control must be adequate.
When it is dry, a humidifier should be used. It is recommended to avoid using
insulators that easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands.
Similar precautions need to be taken for PW boards with mounted
semiconductor devices.
(4) Status before
initialization: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions
have not yet been initialized. Hence, power-on does not guarantee output pin
levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after
power-on for devices with reset functions.
(5) Power ON/OFF
sequence: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply
after switching on the internal power supply. When switching the power supply
off, as a rule, switch off the external power supply and then the internal power
supply. Use of the reverse power on/off sequences may result in the
application of an overvoltage to the internal elements of the device, causing
malfunction and degradation of internal elements due to the passage of an
abnormal current. The correct power on/off sequence must be judged
separately for each device and according to related specifications governing
the device.
(6) Input of signal
during power off
state:
Do not input signals or an I/O pull-up power supply while the device is not
powered. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that
passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each
device and according to related specifications governing the device.

How to Use This Manual
Readers This manual is intended for users who wish to understand the functions of the
V850E2/PG4-L and design application systems using the following V850E2/
PG4-L microcontrollers:
Purpose This manual is intended to give users an understanding of the hardware
functions of the V850E2/PG4-L shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture
(V850E2M Architecture User’s Manual).
How to read this
manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850E2/PG4-L.
Read this manual according to the Contents.
To understand the details of an instruction function
See V850E2M Architecture User’s Manual available separately.
All trademarks and registered trademarks are the property of their respective
owners.
Hardware Architecture
Pin functions
CPU function
On-chip peripheral functions
Flash memory programming
Data types
Register set
Instruction format and instruction set
Interrupts and exceptions
Pipeline operation

Table of Contents
Section 1 Introduction....................................................................................................21
1.1 Overview....................................................................................................................................... 21
1.2 Characteristics.............................................................................................................................. 22
1.3 List of Functions............................................................................................................................ 25
1.4 Field of Application ....................................................................................................................... 27
1.5 Information for Ordering................................................................................................................ 27
1.6 Pin Connection Diagram (Top View) ............................................................................................28
1.7 Configuration of Functional Blocks............................................................................................... 34
1.7.1 Internal Block Diagram....................................................................................................... 34
1.7.2 Internal Units ...................................................................................................................... 35
Section 2 Port Functions................................................................................................38
2.1 Port Functions............................................................................................................................... 38
2.2 Overview....................................................................................................................................... 39
2.2.1 Terms ................................................................................................................................. 39
2.2.2 Pin Function Configuration.................................................................................................40
2.2.3 Pin Data Input/Output......................................................................................................... 43
2.2.4 Port Control Logic Diagram................................................................................................45
2.3 Port Group Configuration Registers.............................................................................................. 46
2.3.1 Overview............................................................................................................................. 46
2.3.2 Pin Function Configuration Registers................................................................................. 48
2.3.3 Pin Data Input/Output Registers......................................................................................... 55
2.3.4 Configuration of Electrical Characteristics Registers.......................................................... 59
2.3.5 Port Register Protection ..................................................................................................... 61
2.4 Port Group Configuration.............................................................................................................. 63
2.4.1 List of Ports and Pins.......................................................................................................... 64
2.5 Functions of Pull-Up and Pull-Down Resistors............................................................................. 84
2.5.1 Details of Pull-Up and Pull-Down Resistors ....................................................................... 84
2.6 Port 0............................................................................................................................................ 89
2.6.1 Alternative Functions.......................................................................................................... 89
2.6.2 List of Control Registers..................................................................................................... 90
2.7 Port 1............................................................................................................................................ 91
2.7.1 Alternative Functions.......................................................................................................... 91
2.7.2 List of Control Registers..................................................................................................... 92
2.8 Port 2............................................................................................................................................ 93
2.8.1 Alternative Functions.......................................................................................................... 93
2.8.2 List of Control Registers..................................................................................................... 94
2.9 Port 3............................................................................................................................................ 95
2.9.1 Alternative Functions.......................................................................................................... 95

2.9.2 List of Control Registers..................................................................................................... 96
2.10 Port 4............................................................................................................................................ 97
2.10.1 Alternative Functions.......................................................................................................... 97
2.10.2 List of Control Registers..................................................................................................... 98
2.11 Port 5............................................................................................................................................ 99
2.11.1 Alternative Functions.......................................................................................................... 99
2.11.2 List of Control Registers................................................................................................... 100
2.12 Port 8.......................................................................................................................................... 101
2.12.1 Alternative Functions........................................................................................................ 101
2.12.2 List of Control Registers................................................................................................... 101
2.13 JTAG Port 0................................................................................................................................ 102
2.13.1 Alternative Functions........................................................................................................ 102
2.13.2 List of Control Registers................................................................................................... 102
2.14 Cancelling Noise on Pins............................................................................................................ 103
2.14.1 Details of Noise Cancellation............................................................................................103
2.14.2 Control Registers.............................................................................................................. 109
2.15 Edge Detection........................................................................................................................... 116
2.15.1 Details of Edge Detection................................................................................................. 116
2.15.2 Control Register................................................................................................................ 117
Section 3 CPU System Function..................................................................................118
3.1 Overview..................................................................................................................................... 118
3.1.1 Peripheral Protection Unit................................................................................................. 120
3.1.2 Important Reminders........................................................................................................ 124
3.1.3 Timing Supervision Unit.................................................................................................... 124
3.2 Operation Modes........................................................................................................................ 125
3.2.1 Normal Operation Mode................................................................................................... 125
3.2.2 Flash Programming Mode................................................................................................ 125
3.2.3 HALT Mode ...................................................................................................................... 126
3.3 Address Space ........................................................................................................................... 127
3.3.1 CPU Data Address and Physical Program Address Space.............................................. 127
3.3.2 Program and Data Space................................................................................................. 127
3.4 Conditions for Boundary Operations........................................................................................... 129
3.4.1 Program Space................................................................................................................. 129
3.4.2 Data Space....................................................................................................................... 129
3.5 Memory Mapping........................................................................................................................ 130
3.5.1 Memory Map for DMA Access.......................................................................................... 130
3.5.2 Memory Map..................................................................................................................... 131
3.6 CPU-Related Registers .............................................................................................................. 132
3.6.1 Overview of CPU-Related Registers................................................................................ 132
3.6.2 CPU-Related Registers in Detail...................................................................................... 133
3.7 System Error Notification Function............................................................................................. 134
3.7.1 Overview of System Error Notification Registers.............................................................. 134

3.7.2 System Error Notification Function Registers in Detail..................................................... 135
Section 4 Interrupt Functions.......................................................................................139
4.1 Features...................................................................................................................................... 139
4.2 List of Interrupt Sources.............................................................................................................. 141
4.3 Interrupt Controller Control Registers......................................................................................... 149
4.3.1 ICxx: EI Level Interrupt Control Register.......................................................................... 149
4.3.2 IMRm (m = 0 to 13): EI Level Interrupt Mask Register..................................................... 156
4.3.3 ISPR – In-Service Priority Register .................................................................................. 164
4.3.4 PMR – Priority Mask Register .......................................................................................... 165
4.3.5 ISPC – In-Service Priority Clear Register......................................................................... 166
4.3.6 SCR – Selected Channel Hold Register........................................................................... 167
4.3.7 ICSR – Interrupt Controller Status Register ..................................................................... 168
4.3.8 FNC – FE Level NMI Status Register............................................................................... 169
4.3.9 FIC – FE Level INT Status Register ................................................................................. 170
4.3.10 INTCFGB – FE level Interrupt Switch Register ................................................................ 171
4.3.11 INTSTR0B – Error Interrupt Source Storage Register ..................................................... 172
4.3.12 INTSTC0B – Interrupt Request Flag Clearing Register.................................................... 173
4.3.13 INTSTS0B – Interrupt Request Flag Setting Register...................................................... 174
4.4 Interrupt Acknowledgment and Restoring................................................................................... 175
4.4.1 FE Level Non-Maskable Interrupt Caused by FENMI Interrupt Request.......................... 175
4.4.2 Restore from FE Level Non-Maskable Interrupt (FENMI) ................................................ 177
4.4.3 FE Level Maskable Interrupt Caused by FEINT Interrupt Request.................................. 177
4.4.4 Restore from FE Level Maskable Interrupt (FEINT) Servicing......................................... 179
4.4.5 EI Level Maskable Interrupt Caused by EIINT Interrupt Request..................................... 180
4.4.6 Restore from EI Level Maskable Interrupt (EIINT) ........................................................... 182
4.5 Interrupt Operation...................................................................................................................... 183
4.5.1 Mask Function of EI Level Maskable Interrupt (EIINT)..................................................... 183
4.5.2 Interrupt Priority Level Judgment...................................................................................... 183
4.5.3 Priority Mask Function...................................................................................................... 189
4.5.4 Pending Interrupt Report Function ................................................................................... 190
4.5.5 In-Service Priority Clear Function..................................................................................... 190
4.6 Exception Handler Address Switching Function......................................................................... 191
4.7 Interrupt Response Times .......................................................................................................... 191
Section 5 DMA Module................................................................................................192
5.1 DMA in Overview........................................................................................................................ 192
5.2 Definitions................................................................................................................................... 196
5.3 Overview..................................................................................................................................... 197
5.3.1 Functions of the DMA Controller (DMAC) ........................................................................ 197
5.3.2 Function of the DMA Trigger Factor Register (DTFR)...................................................... 197
5.3.3 Memory Map for DMA Access.......................................................................................... 199
5.3.4 Channel Priority................................................................................................................ 199
5.4 DMAC Function .......................................................................................................................... 200

5.4.1 Characteristics.................................................................................................................. 200
5.4.2 Setting Registers.............................................................................................................. 202
5.4.3 Availability of Writing to Control Registers........................................................................ 207
5.5 DMAC Control Registers ............................................................................................................ 208
5.5.1 DTRC0: DMA Transfer Request Control Register 0......................................................... 208
5.5.2 DTRSn (n = 0 to 7): DMA Transfer Request Select Register........................................... 209
5.5.3 DSAnL (n = 0 to 7): DMA Source Address Register L...................................................... 210
5.5.4 DSAnH (n = 0 to 7): DMA Source Address Register H .................................................... 211
5.5.5 DSCn (n = 0 to 7): DMA Source Chip Select Register ..................................................... 212
5.5.6 DNSAnL (n = 0 to 7): DMA Next Source Address Register L........................................... 213
5.5.7 DNSAnH (n = 0 to 7): DMA Next Source Address Register H ......................................... 214
5.5.8 DNSCn (n = 0 to 7): DMA Next Source Chip Select Register .......................................... 215
5.5.9 DDAnL (n = 0 to 7): DMA Destination Address Register L............................................... 216
5.5.10 DDAnH (n = 0 to 7): DMA Destination Address Register H.............................................. 217
5.5.11 DDCn (n = 0 to 7): DMA Destination Chip Select Register .............................................. 218
5.5.12 DNDAnL (n = 0 to 7): DMA Next Destination Address Register L.................................... 219
5.5.13 DNDAnH (n = 0 to 7): DMA Next Destination Address Register H................................... 220
5.5.14 DNDCn (n = 0 to 7): DMA Next Destination Chip Select Register ................................... 221
5.5.15 DTCn (n = 0 to 7): DMA Transfer Count Register ............................................................ 222
5.5.16 DNTCn (n = 0 to 7): DMA Next Transfer Count Register ................................................. 223
5.5.17 DTCCn (n =0 to 7): DMA Transfer Count Compare Register........................................... 224
5.5.18 DTCTn (n = 0 to 7): DMA Transfer Control Register........................................................ 225
5.5.19 DTSn (n = 0 to 7): DMA Transfer Status Register............................................................ 227
5.6 DMAC Function Details .............................................................................................................. 229
5.6.1 DMAC Transfer Setting Flow............................................................................................ 229
5.6.2 DMAC Transfer Modes..................................................................................................... 230
5.6.3 DMAC Channel Priority Control........................................................................................ 233
5.6.4 Conditions for Validity of DMA Transfer Requests........................................................... 234
5.6.5 Next Address Function..................................................................................................... 235
5.6.6 Suspending/Resuming DMA Transfer.............................................................................. 236
5.6.7 Error Responses............................................................................................................... 237
5.7 DTFR Functions.......................................................................................................................... 238
5.7.1 Features ........................................................................................................................... 238
5.8 DTFR Control Registers ............................................................................................................. 239
5.8.1 DTFRn (n = 0 to 7): DMA Trigger Factor Register ........................................................... 239
5.8.2 DRQCLR: DMA Request Clear Register.......................................................................... 240
5.8.3 DRQSTR: DMA Request Check Register ........................................................................ 241
Section 6 Memory Modules .........................................................................................242
6.1 Features...................................................................................................................................... 243
6.1.1 Code Flash Memory......................................................................................................... 243
6.1.2 Data Flash Memory.......................................................................................................... 244
6.1.3 On-Chip RAM................................................................................................................... 244
6.2 Programming Environment......................................................................................................... 245
6.3 Communications Methods.......................................................................................................... 245

6.4 Handling of Pins.......................................................................................................................... 246
6.4.1 Power Supply ................................................................................................................... 246
6.4.2 Pins................................................................................................................................... 246
6.4.3 Reset Pin.......................................................................................................................... 246
6.4.4 FLMD0 Pin........................................................................................................................ 247
6.4.5 Port Pins........................................................................................................................... 247
6.5 Option-Setting Bytes................................................................................................................... 248
6.5.1 OPBT0 - Option Byte Verification Register....................................................................... 249
6.6 Product Identification.................................................................................................................. 250
6.7 Setting the FLMD Pin.................................................................................................................. 253
6.7.1 Registers .......................................................................................................................... 253
6.7.2 Setting the FLMDCNT Register........................................................................................ 255
Section 7 Clock Generation.........................................................................................256
7.1 Overview of Clock Generation.................................................................................................... 257
7.2 Configuration .............................................................................................................................. 258
7.3 Selecting the Input Clock Signal................................................................................................. 259
7.4 Clock Generating Circuit............................................................................................................. 260
7.5 Clock Output Function (CLKOUT) .............................................................................................. 261
7.5.1 Baud-Rate Generator for CLKOUT Function (BRGA)...................................................... 261
7.5.2 BRGA Registers for CLKOUT Function............................................................................ 263
7.6 Single-Pin Debugging Clock (LPDCLK)...................................................................................... 267
7.7 WDTA0 Count Clock (WDTCLKI)............................................................................................... 267
7.8 Clock Monitor A (CLMAn) Function............................................................................................ 268
7.8.1 Features of the Clock Monitors (CLMAn; n = 0, 1, 2)....................................................... 268
7.8.2 CLMA Enable and Start-Up Options................................................................................. 270
7.8.3 Functional Overview......................................................................................................... 270
7.8.4 Functional Description...................................................................................................... 271
7.8.5 Clock Monitor A Registers................................................................................................ 277
Section 8 Reset Controller...........................................................................................282
8.1 Functional Overview................................................................................................................... 282
8.2 Functional Description................................................................................................................ 285
8.2.1 Reset Flags ...................................................................................................................... 285
8.2.2 Low-Voltage Indicator (LVI).............................................................................................. 286
8.2.3 External RESET ............................................................................................................... 287
8.2.4 Watchdog Timer Reset..................................................................................................... 288
8.2.5 Software Reset................................................................................................................. 288
8.2.6 Clock Monitor Reset......................................................................................................... 289
8.2.7 Self-Diagnostic BIST Reset.............................................................................................. 290
8.2.8 Safety Guardian Reset..................................................................................................... 290
8.2.9 Reset Flag Evaluation ...................................................................................................... 291
8.2.10 Protection for Registers of the Reset Controller............................................................... 292
8.3 Registers..................................................................................................................................... 293

8.3.1 Overview of Reset Controller Registers ........................................................................... 293
8.3.2 Details of Reset Controller Registers ............................................................................... 294
8.3.3 Details of Software Reset Control Registers.................................................................... 298
8.3.4 Details of Protection Command Registers........................................................................ 299
8.4 Power-on Flag/Low Voltage Indicator (POF/LVI)........................................................................ 300
8.4.1 Overview of the POF/LVI Function................................................................................... 300
8.4.2 Operation.......................................................................................................................... 301
8.4.3 Overview of POF/LVI Registers........................................................................................ 304
8.4.4 Details of POF / LVI Control Registers............................................................................. 305
Section 9 Safety Functions..........................................................................................308
9.1 Peripheral Bus Access Error Detection ...................................................................................... 308
9.2 Memory Access Protection......................................................................................................... 308
9.2.1 Memory Access Protection............................................................................................... 308
9.3 Registers Related to the Peripheral I/O Bus............................................................................... 309
9.3.1 Overview of Registers Related to the Peripheral I/O Bus................................................. 309
9.3.2 Details of Registers Related to the Peripheral I/O Bus..................................................... 310
9.4 Overview of Self-Diagnostic BIST............................................................................................... 315
9.4.1 Self-Diagnostic BIST Skip Function.................................................................................. 315
9.4.2 Output of a Toggled Signal during Execution of Self-Diagnostic BIST............................. 316
9.5 Self-Diagnostic BIST Related Registers..................................................................................... 318
9.5.1 Overview of Registers Related to Self-Diagnostic BIST................................................... 318
9.5.2 Details of Registers Related to Self-Diagnostic BIST....................................................... 319
9.5.3 Procedure for Setting the BSEQ0STCHBT Register........................................................ 329
9.6 ECC Related Registers............................................................................................................... 330
9.6.1 Overview of ECC Related Registers ................................................................................ 330
9.6.2 Details of ECC Related Registers .................................................................................... 331
9.7 Self-Diagnosis Method for a Compare Unit................................................................................ 341
9.8 Resources Required for Initialization.......................................................................................... 342
9.8.1 On-chip RAM.................................................................................................................... 342
9.8.2 Registers .......................................................................................................................... 342
Section 10 Safety Guardian (SGA)................................................................................346
10.1 SGA Features............................................................................................................................. 346
10.2 SGA Functional Overview........................................................................................................... 349
10.3 Functional Description................................................................................................................ 352
10.3.1 SGA Operating States...................................................................................................... 352
10.3.2 SGA Configuration Overview............................................................................................ 353
10.3.3 Operations for Error Output.............................................................................................. 354
10.3.4 Loop-Back Function.......................................................................................................... 355
10.3.5 Pseudo Error Generation.................................................................................................. 356
10.3.6 Error Status ...................................................................................................................... 357
10.3.7 Writing to Protected Registers.......................................................................................... 358
10.4 Registers..................................................................................................................................... 359