Renesas V850 Series User manual

User’s Manual
www.renesas.com
V850E2/PG4-L
User’s Manual: Hardware
Renesas microcomputers
V850 Series
Jul 2014
32
Rev.1.02
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
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Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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(2012.4)

Notes for CMOS devices
(1) Voltage
application
wafeform at input
pin:
Waveform distortion due to input noise or a reflected wave may cause
malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through
the area between VIL (MAX) and VIH (MIN).
(2) Handling of
unused input pins: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due
to noise, etc., causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or
low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an
output pin. All handling related to unused pins must be judged separately for
each device and according to related specifications governing the device.
(3) Precaution
against ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it when it has occurred. Environmental control must be adequate.
When it is dry, a humidifier should be used. It is recommended to avoid using
insulators that easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands.
Similar precautions need to be taken for PW boards with mounted
semiconductor devices.
(4) Status before
initialization: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions
have not yet been initialized. Hence, power-on does not guarantee output pin
levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after
power-on for devices with reset functions.
(5) Power ON/OFF
sequence: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply
after switching on the internal power supply. When switching the power supply
off, as a rule, switch off the external power supply and then the internal power
supply. Use of the reverse power on/off sequences may result in the
application of an overvoltage to the internal elements of the device, causing
malfunction and degradation of internal elements due to the passage of an
abnormal current. The correct power on/off sequence must be judged
separately for each device and according to related specifications governing
the device.
(6) Input of signal
during power off
state:
Do not input signals or an I/O pull-up power supply while the device is not
powered. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that
passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each
device and according to related specifications governing the device.

How to Use This Manual
Readers This manual is intended for users who wish to understand the functions of the
V850E2/PG4-L and design application systems using the following V850E2/
PG4-L microcontrollers:
Purpose This manual is intended to give users an understanding of the hardware
functions of the V850E2/PG4-L shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture
(V850E2M Architecture User’s Manual).
How to read this
manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850E2/PG4-L.
Read this manual according to the Contents.
To understand the details of an instruction function
See V850E2M Architecture User’s Manual available separately.
All trademarks and registered trademarks are the property of their respective
owners.
Hardware Architecture
Pin functions
CPU function
On-chip peripheral functions
Flash memory programming
Data types
Register set
Instruction format and instruction set
Interrupts and exceptions
Pipeline operation

Table of Contents
Section 1 Introduction....................................................................................................21
1.1 Overview....................................................................................................................................... 21
1.2 Characteristics.............................................................................................................................. 22
1.3 List of Functions............................................................................................................................ 25
1.4 Field of Application ....................................................................................................................... 27
1.5 Information for Ordering................................................................................................................ 27
1.6 Pin Connection Diagram (Top View) ............................................................................................28
1.7 Configuration of Functional Blocks............................................................................................... 34
1.7.1 Internal Block Diagram....................................................................................................... 34
1.7.2 Internal Units ...................................................................................................................... 35
Section 2 Port Functions................................................................................................38
2.1 Port Functions............................................................................................................................... 38
2.2 Overview....................................................................................................................................... 39
2.2.1 Terms ................................................................................................................................. 39
2.2.2 Pin Function Configuration.................................................................................................40
2.2.3 Pin Data Input/Output......................................................................................................... 43
2.2.4 Port Control Logic Diagram................................................................................................45
2.3 Port Group Configuration Registers.............................................................................................. 46
2.3.1 Overview............................................................................................................................. 46
2.3.2 Pin Function Configuration Registers................................................................................. 48
2.3.3 Pin Data Input/Output Registers......................................................................................... 55
2.3.4 Configuration of Electrical Characteristics Registers.......................................................... 59
2.3.5 Port Register Protection ..................................................................................................... 61
2.4 Port Group Configuration.............................................................................................................. 63
2.4.1 List of Ports and Pins.......................................................................................................... 64
2.5 Functions of Pull-Up and Pull-Down Resistors............................................................................. 84
2.5.1 Details of Pull-Up and Pull-Down Resistors ....................................................................... 84
2.6 Port 0............................................................................................................................................ 89
2.6.1 Alternative Functions.......................................................................................................... 89
2.6.2 List of Control Registers..................................................................................................... 90
2.7 Port 1............................................................................................................................................ 91
2.7.1 Alternative Functions.......................................................................................................... 91
2.7.2 List of Control Registers..................................................................................................... 92
2.8 Port 2............................................................................................................................................ 93
2.8.1 Alternative Functions.......................................................................................................... 93
2.8.2 List of Control Registers..................................................................................................... 94
2.9 Port 3............................................................................................................................................ 95
2.9.1 Alternative Functions.......................................................................................................... 95

2.9.2 List of Control Registers..................................................................................................... 96
2.10 Port 4............................................................................................................................................ 97
2.10.1 Alternative Functions.......................................................................................................... 97
2.10.2 List of Control Registers..................................................................................................... 98
2.11 Port 5............................................................................................................................................ 99
2.11.1 Alternative Functions.......................................................................................................... 99
2.11.2 List of Control Registers................................................................................................... 100
2.12 Port 8.......................................................................................................................................... 101
2.12.1 Alternative Functions........................................................................................................ 101
2.12.2 List of Control Registers................................................................................................... 101
2.13 JTAG Port 0................................................................................................................................ 102
2.13.1 Alternative Functions........................................................................................................ 102
2.13.2 List of Control Registers................................................................................................... 102
2.14 Cancelling Noise on Pins............................................................................................................ 103
2.14.1 Details of Noise Cancellation............................................................................................103
2.14.2 Control Registers.............................................................................................................. 109
2.15 Edge Detection........................................................................................................................... 116
2.15.1 Details of Edge Detection................................................................................................. 116
2.15.2 Control Register................................................................................................................ 117
Section 3 CPU System Function..................................................................................118
3.1 Overview..................................................................................................................................... 118
3.1.1 Peripheral Protection Unit................................................................................................. 120
3.1.2 Important Reminders........................................................................................................ 124
3.1.3 Timing Supervision Unit.................................................................................................... 124
3.2 Operation Modes........................................................................................................................ 125
3.2.1 Normal Operation Mode................................................................................................... 125
3.2.2 Flash Programming Mode................................................................................................ 125
3.2.3 HALT Mode ...................................................................................................................... 126
3.3 Address Space ........................................................................................................................... 127
3.3.1 CPU Data Address and Physical Program Address Space.............................................. 127
3.3.2 Program and Data Space................................................................................................. 127
3.4 Conditions for Boundary Operations........................................................................................... 129
3.4.1 Program Space................................................................................................................. 129
3.4.2 Data Space....................................................................................................................... 129
3.5 Memory Mapping........................................................................................................................ 130
3.5.1 Memory Map for DMA Access.......................................................................................... 130
3.5.2 Memory Map..................................................................................................................... 131
3.6 CPU-Related Registers .............................................................................................................. 132
3.6.1 Overview of CPU-Related Registers................................................................................ 132
3.6.2 CPU-Related Registers in Detail...................................................................................... 133
3.7 System Error Notification Function............................................................................................. 134
3.7.1 Overview of System Error Notification Registers.............................................................. 134

3.7.2 System Error Notification Function Registers in Detail..................................................... 135
Section 4 Interrupt Functions.......................................................................................139
4.1 Features...................................................................................................................................... 139
4.2 List of Interrupt Sources.............................................................................................................. 141
4.3 Interrupt Controller Control Registers......................................................................................... 149
4.3.1 ICxx: EI Level Interrupt Control Register.......................................................................... 149
4.3.2 IMRm (m = 0 to 13): EI Level Interrupt Mask Register..................................................... 156
4.3.3 ISPR – In-Service Priority Register .................................................................................. 164
4.3.4 PMR – Priority Mask Register .......................................................................................... 165
4.3.5 ISPC – In-Service Priority Clear Register......................................................................... 166
4.3.6 SCR – Selected Channel Hold Register........................................................................... 167
4.3.7 ICSR – Interrupt Controller Status Register ..................................................................... 168
4.3.8 FNC – FE Level NMI Status Register............................................................................... 169
4.3.9 FIC – FE Level INT Status Register ................................................................................. 170
4.3.10 INTCFGB – FE level Interrupt Switch Register ................................................................ 171
4.3.11 INTSTR0B – Error Interrupt Source Storage Register ..................................................... 172
4.3.12 INTSTC0B – Interrupt Request Flag Clearing Register.................................................... 173
4.3.13 INTSTS0B – Interrupt Request Flag Setting Register...................................................... 174
4.4 Interrupt Acknowledgment and Restoring................................................................................... 175
4.4.1 FE Level Non-Maskable Interrupt Caused by FENMI Interrupt Request.......................... 175
4.4.2 Restore from FE Level Non-Maskable Interrupt (FENMI) ................................................ 177
4.4.3 FE Level Maskable Interrupt Caused by FEINT Interrupt Request.................................. 177
4.4.4 Restore from FE Level Maskable Interrupt (FEINT) Servicing......................................... 179
4.4.5 EI Level Maskable Interrupt Caused by EIINT Interrupt Request..................................... 180
4.4.6 Restore from EI Level Maskable Interrupt (EIINT) ........................................................... 182
4.5 Interrupt Operation...................................................................................................................... 183
4.5.1 Mask Function of EI Level Maskable Interrupt (EIINT)..................................................... 183
4.5.2 Interrupt Priority Level Judgment...................................................................................... 183
4.5.3 Priority Mask Function...................................................................................................... 189
4.5.4 Pending Interrupt Report Function ................................................................................... 190
4.5.5 In-Service Priority Clear Function..................................................................................... 190
4.6 Exception Handler Address Switching Function......................................................................... 191
4.7 Interrupt Response Times .......................................................................................................... 191
Section 5 DMA Module................................................................................................192
5.1 DMA in Overview........................................................................................................................ 192
5.2 Definitions................................................................................................................................... 196
5.3 Overview..................................................................................................................................... 197
5.3.1 Functions of the DMA Controller (DMAC) ........................................................................ 197
5.3.2 Function of the DMA Trigger Factor Register (DTFR)...................................................... 197
5.3.3 Memory Map for DMA Access.......................................................................................... 199
5.3.4 Channel Priority................................................................................................................ 199
5.4 DMAC Function .......................................................................................................................... 200

5.4.1 Characteristics.................................................................................................................. 200
5.4.2 Setting Registers.............................................................................................................. 202
5.4.3 Availability of Writing to Control Registers........................................................................ 207
5.5 DMAC Control Registers ............................................................................................................ 208
5.5.1 DTRC0: DMA Transfer Request Control Register 0......................................................... 208
5.5.2 DTRSn (n = 0 to 7): DMA Transfer Request Select Register........................................... 209
5.5.3 DSAnL (n = 0 to 7): DMA Source Address Register L...................................................... 210
5.5.4 DSAnH (n = 0 to 7): DMA Source Address Register H .................................................... 211
5.5.5 DSCn (n = 0 to 7): DMA Source Chip Select Register ..................................................... 212
5.5.6 DNSAnL (n = 0 to 7): DMA Next Source Address Register L........................................... 213
5.5.7 DNSAnH (n = 0 to 7): DMA Next Source Address Register H ......................................... 214
5.5.8 DNSCn (n = 0 to 7): DMA Next Source Chip Select Register .......................................... 215
5.5.9 DDAnL (n = 0 to 7): DMA Destination Address Register L............................................... 216
5.5.10 DDAnH (n = 0 to 7): DMA Destination Address Register H.............................................. 217
5.5.11 DDCn (n = 0 to 7): DMA Destination Chip Select Register .............................................. 218
5.5.12 DNDAnL (n = 0 to 7): DMA Next Destination Address Register L.................................... 219
5.5.13 DNDAnH (n = 0 to 7): DMA Next Destination Address Register H................................... 220
5.5.14 DNDCn (n = 0 to 7): DMA Next Destination Chip Select Register ................................... 221
5.5.15 DTCn (n = 0 to 7): DMA Transfer Count Register ............................................................ 222
5.5.16 DNTCn (n = 0 to 7): DMA Next Transfer Count Register ................................................. 223
5.5.17 DTCCn (n =0 to 7): DMA Transfer Count Compare Register........................................... 224
5.5.18 DTCTn (n = 0 to 7): DMA Transfer Control Register........................................................ 225
5.5.19 DTSn (n = 0 to 7): DMA Transfer Status Register............................................................ 227
5.6 DMAC Function Details .............................................................................................................. 229
5.6.1 DMAC Transfer Setting Flow............................................................................................ 229
5.6.2 DMAC Transfer Modes..................................................................................................... 230
5.6.3 DMAC Channel Priority Control........................................................................................ 233
5.6.4 Conditions for Validity of DMA Transfer Requests........................................................... 234
5.6.5 Next Address Function..................................................................................................... 235
5.6.6 Suspending/Resuming DMA Transfer.............................................................................. 236
5.6.7 Error Responses............................................................................................................... 237
5.7 DTFR Functions.......................................................................................................................... 238
5.7.1 Features ........................................................................................................................... 238
5.8 DTFR Control Registers ............................................................................................................. 239
5.8.1 DTFRn (n = 0 to 7): DMA Trigger Factor Register ........................................................... 239
5.8.2 DRQCLR: DMA Request Clear Register.......................................................................... 240
5.8.3 DRQSTR: DMA Request Check Register ........................................................................ 241
Section 6 Memory Modules .........................................................................................242
6.1 Features...................................................................................................................................... 243
6.1.1 Code Flash Memory......................................................................................................... 243
6.1.2 Data Flash Memory.......................................................................................................... 244
6.1.3 On-Chip RAM................................................................................................................... 244
6.2 Programming Environment......................................................................................................... 245
6.3 Communications Methods.......................................................................................................... 245

6.4 Handling of Pins.......................................................................................................................... 246
6.4.1 Power Supply ................................................................................................................... 246
6.4.2 Pins................................................................................................................................... 246
6.4.3 Reset Pin.......................................................................................................................... 246
6.4.4 FLMD0 Pin........................................................................................................................ 247
6.4.5 Port Pins........................................................................................................................... 247
6.5 Option-Setting Bytes................................................................................................................... 248
6.5.1 OPBT0 - Option Byte Verification Register....................................................................... 249
6.6 Product Identification.................................................................................................................. 250
6.7 Setting the FLMD Pin.................................................................................................................. 253
6.7.1 Registers .......................................................................................................................... 253
6.7.2 Setting the FLMDCNT Register........................................................................................ 255
Section 7 Clock Generation.........................................................................................256
7.1 Overview of Clock Generation.................................................................................................... 257
7.2 Configuration .............................................................................................................................. 258
7.3 Selecting the Input Clock Signal................................................................................................. 259
7.4 Clock Generating Circuit............................................................................................................. 260
7.5 Clock Output Function (CLKOUT) .............................................................................................. 261
7.5.1 Baud-Rate Generator for CLKOUT Function (BRGA)...................................................... 261
7.5.2 BRGA Registers for CLKOUT Function............................................................................ 263
7.6 Single-Pin Debugging Clock (LPDCLK)...................................................................................... 267
7.7 WDTA0 Count Clock (WDTCLKI)............................................................................................... 267
7.8 Clock Monitor A (CLMAn) Function............................................................................................ 268
7.8.1 Features of the Clock Monitors (CLMAn; n = 0, 1, 2)....................................................... 268
7.8.2 CLMA Enable and Start-Up Options................................................................................. 270
7.8.3 Functional Overview......................................................................................................... 270
7.8.4 Functional Description...................................................................................................... 271
7.8.5 Clock Monitor A Registers................................................................................................ 277
Section 8 Reset Controller...........................................................................................282
8.1 Functional Overview................................................................................................................... 282
8.2 Functional Description................................................................................................................ 285
8.2.1 Reset Flags ...................................................................................................................... 285
8.2.2 Low-Voltage Indicator (LVI).............................................................................................. 286
8.2.3 External RESET ............................................................................................................... 287
8.2.4 Watchdog Timer Reset..................................................................................................... 288
8.2.5 Software Reset................................................................................................................. 288
8.2.6 Clock Monitor Reset......................................................................................................... 289
8.2.7 Self-Diagnostic BIST Reset.............................................................................................. 290
8.2.8 Safety Guardian Reset..................................................................................................... 290
8.2.9 Reset Flag Evaluation ...................................................................................................... 291
8.2.10 Protection for Registers of the Reset Controller............................................................... 292
8.3 Registers..................................................................................................................................... 293

8.3.1 Overview of Reset Controller Registers ........................................................................... 293
8.3.2 Details of Reset Controller Registers ............................................................................... 294
8.3.3 Details of Software Reset Control Registers.................................................................... 298
8.3.4 Details of Protection Command Registers........................................................................ 299
8.4 Power-on Flag/Low Voltage Indicator (POF/LVI)........................................................................ 300
8.4.1 Overview of the POF/LVI Function................................................................................... 300
8.4.2 Operation.......................................................................................................................... 301
8.4.3 Overview of POF/LVI Registers........................................................................................ 304
8.4.4 Details of POF / LVI Control Registers............................................................................. 305
Section 9 Safety Functions..........................................................................................308
9.1 Peripheral Bus Access Error Detection ...................................................................................... 308
9.2 Memory Access Protection......................................................................................................... 308
9.2.1 Memory Access Protection............................................................................................... 308
9.3 Registers Related to the Peripheral I/O Bus............................................................................... 309
9.3.1 Overview of Registers Related to the Peripheral I/O Bus................................................. 309
9.3.2 Details of Registers Related to the Peripheral I/O Bus..................................................... 310
9.4 Overview of Self-Diagnostic BIST............................................................................................... 315
9.4.1 Self-Diagnostic BIST Skip Function.................................................................................. 315
9.4.2 Output of a Toggled Signal during Execution of Self-Diagnostic BIST............................. 316
9.5 Self-Diagnostic BIST Related Registers..................................................................................... 318
9.5.1 Overview of Registers Related to Self-Diagnostic BIST................................................... 318
9.5.2 Details of Registers Related to Self-Diagnostic BIST....................................................... 319
9.5.3 Procedure for Setting the BSEQ0STCHBT Register........................................................ 329
9.6 ECC Related Registers............................................................................................................... 330
9.6.1 Overview of ECC Related Registers ................................................................................ 330
9.6.2 Details of ECC Related Registers .................................................................................... 331
9.7 Self-Diagnosis Method for a Compare Unit................................................................................ 341
9.8 Resources Required for Initialization.......................................................................................... 342
9.8.1 On-chip RAM.................................................................................................................... 342
9.8.2 Registers .......................................................................................................................... 342
Section 10 Safety Guardian (SGA)................................................................................346
10.1 SGA Features............................................................................................................................. 346
10.2 SGA Functional Overview........................................................................................................... 349
10.3 Functional Description................................................................................................................ 352
10.3.1 SGA Operating States...................................................................................................... 352
10.3.2 SGA Configuration Overview............................................................................................ 353
10.3.3 Operations for Error Output.............................................................................................. 354
10.3.4 Loop-Back Function.......................................................................................................... 355
10.3.5 Pseudo Error Generation.................................................................................................. 356
10.3.6 Error Status ...................................................................................................................... 357
10.3.7 Writing to Protected Registers.......................................................................................... 358
10.4 Registers..................................................................................................................................... 359

10.4.1 Overview of SGA Registers.............................................................................................. 359
10.4.2 SGA Registers Details...................................................................................................... 360
Section 11 Data CRC Function A (DCRA).....................................................................378
11.1 DCRA Features .......................................................................................................................... 378
11.2 Functional Overview................................................................................................................... 379
11.3 Functional Description................................................................................................................ 381
11.4 Registers..................................................................................................................................... 382
11.4.1 DCRA Registers Overview ............................................................................................... 382
11.4.2 DCRA Registers Details................................................................................................... 383
Section 12 Window Watchdog Timer A (WDTA) ...........................................................386
12.1 WDTA Features.......................................................................................................................... 386
12.2 Functional Overview................................................................................................................... 387
12.3 Functional Description................................................................................................................ 388
12.3.1 WDTA after Reset Release.............................................................................................. 388
12.3.2 WDTA Trigger................................................................................................................... 389
12.3.3 Error Detection ................................................................................................................. 390
12.3.4 75% Interrupt Output........................................................................................................ 392
12.3.5 Window Function.............................................................................................................. 393
12.4 Registers..................................................................................................................................... 394
12.4.1 WDTA Registers Overview............................................................................................... 394
12.4.2 WDTA Registers Details................................................................................................... 395
Section 13 Timer Array Unit B (TAUB) ..........................................................................397
13.1 TAUB Features........................................................................................................................... 397
13.2 Functional Overview................................................................................................................... 400
13.2.1 Terms ............................................................................................................................... 401
13.3 Functional Description................................................................................................................ 402
13.3.1 Functional List of Timer Operations.................................................................................. 404
13.4 General Operating Procedures................................................................................................... 405
13.5 Operation Modes........................................................................................................................ 406
13.6 Concepts of Synchronous Channel Operation ........................................................................... 407
13.6.1 Rules ................................................................................................................................ 407
13.6.2 Simultaneous Start and Stop of Synchronous Channel Counters.................................... 409
13.7 Simultaneous Rewrite................................................................................................................. 410
13.7.1 Overview........................................................................................................................... 410
13.7.2 How to Control Simultaneous Rewrite.............................................................................. 412
13.7.3 Other General Rules of Simultaneous Rewrite................................................................. 414
13.7.4 Type of Simultaneous Rewrite.......................................................................................... 415
13.8 Channel Output Modes............................................................................................................... 421
13.8.1 General Procedures for Specifying a Channel Output Mode ........................................... 423
13.8.2 Channel Output Modes Controlled Independently by TAUBn Signals ............................. 424

13.8.3 Channel Output Modes Controlled Synchronously by TAUBn Signals ............................ 425
13.9 Start Timing in Each Operating Modes....................................................................................... 427
13.9.1 Interval Timer Mode, Judge Mode, Capture Mode, and Up/Down Count Mode............... 427
13.9.2 Event Mode ...................................................................................................................... 428
13.9.3 Other Operating Modes.................................................................................................... 428
13.10 TAUBnTTOUTm Output and INTTAUBnIm Generation when Counter Starts or
Restarts (TAUBnMD0 bit)........................................................................................................... 429
13.11 TAUBnTTINm Edge Detection.................................................................................................... 431
13.12 Independent Channel Operation Functions................................................................................ 432
13.13 Independent Channel Interrupt Functions .................................................................................. 432
13.13.1 Interval Timer Function..................................................................................................... 433
13.13.2 TAUBnTTINm Input Interval Timer Function .................................................................... 440
13.13.3 One-Pulse Output Function.............................................................................................. 446
13.14 Independent Channel Signal Measurement Functions............................................................... 451
13.14.1 TAUBnTTINm Input Pulse Interval Measurement Function ............................................. 452
13.14.2 TAUBnTTINm Input Signal Width Measurement Function............................................... 460
13.14.3 TAUBnTTINm Input Period Count Detection Function..................................................... 468
13.14.4 TAUBnTTINm Input Pulse Interval Judgment Function.................................................... 473
13.14.5 TAUBnTTINm Input Signal Width Judgment Function..................................................... 478
13.15 Independent Channel Simultaneous Rewrite Functions............................................................. 483
13.15.1 Simultaneous Rewrite Trigger Generation Function Type 1............................................. 484
13.16 Other Independent Channel Functions....................................................................................... 490
13.16.1 External Event Count Function......................................................................................... 491
13.16.2 Clock Divide Function....................................................................................................... 498
13.16.3 TAUBnTTINm Input Position Detection Function ............................................................. 505
13.17 Synchronous Channel Operation Functions............................................................................... 511
13.18 Synchronous PWM Signal Functions Triggered at Regular Intervals......................................... 512
13.18.1 PWM Output Function...................................................................................................... 513
13.18.2 Delay Pulse Output Function............................................................................................ 524
13.18.3 AD Conversion Trigger Output Function Type 1 .............................................................. 540
13.19 Synchronous PWM Signal Functions Triggered by an External Signal...................................... 542
13.19.1 One-Shot Pulse Output Function...................................................................................... 543
13.20 Synchronous Triangle PWM Functions ...................................................................................... 556
13.20.1 Triangle PWM Output Function ........................................................................................ 557
13.20.2 Triangle PWM Output Function with Dead Time.............................................................. 568
13.20.3 AD Conversion Trigger Output Function Type 2 .............................................................. 592
13.21 Registers..................................................................................................................................... 594
13.21.1 Overview of TAUBn Registers.......................................................................................... 594
13.21.2 Details of TAUBn Prescaler Registers.............................................................................. 595
13.21.3 Details of TAUBn Control Registers................................................................................. 599
13.21.4 Details of TAUBn Output Registers.................................................................................. 610
13.21.5 Details of TAUBn Channel Output Level Registers.......................................................... 614
13.21.6 Details of TAUBn Simultaneous Rewrite Registers.......................................................... 615

Section 14 Timer Array Unit J (TAUJ)............................................................................619
14.1 Features of TAUJ........................................................................................................................ 619
14.2 Functional Overview................................................................................................................... 621
14.2.1 Terms ............................................................................................................................... 623
14.3 Functional Description................................................................................................................ 624
14.3.1 Timer Operation Functions............................................................................................... 625
14.4 General Operating Procedure..................................................................................................... 626
14.5 Operating Modes........................................................................................................................ 627
14.6 Concepts of Synchronous Channel Operation ........................................................................... 628
14.6.1 Rules ................................................................................................................................ 628
14.6.2 Simultaneous Start and Stop of Synchronous Channel Counters.................................... 630
14.7 Simultaneous Rewrite................................................................................................................. 631
14.7.1 Overview........................................................................................................................... 631
14.7.2 How to Control Simultaneous Rewrite.............................................................................. 632
14.7.3 Other General Rules for Simultaneous Rewrite ............................................................... 633
14.7.4 Simultaneous Rewrite Procedure..................................................................................... 634
14.8 Channel Output Modes............................................................................................................... 636
14.8.1 General Procedure for Specifying a Channel Output Mode............................................. 638
14.8.2 Channel Output Modes Controlled Independently by TAUJn Signals.............................. 639
14.8.3 Channel Output Modes Controlled Synchronously by TAUJn Signals............................. 640
14.9 Start Timing of Operating Modes................................................................................................ 641
14.9.1 Interval Timer Mode and Capture Mode........................................................................... 641
14.9.2 Other Operating Modes.................................................................................................... 642
14.10 TAUJnTTOUTm Output and INTTAUJnIm Generation When Counter Starts or Restarts......... 643
14.11 TAUJnTTINm Edge Detection.................................................................................................... 644
14.12 Independent Channel Operation Functions................................................................................ 645
14.12.1 Interval Timer Function..................................................................................................... 645
14.12.2 TAUJnTTINm Input Interval Timer Function..................................................................... 652
14.12.3 TAUJnTTINm Input Pulse Interval Measurement Function.............................................. 658
14.12.4 TAUJnTTINm Input Signal Width Measurement Function................................................ 667
14.12.5 TAUJnTTINm Input Period Count Detection Function...................................................... 675
14.12.6 TAUJnTTINm Input Position Detection Function.............................................................. 680
14.13 Synchronous Channel Functions................................................................................................ 685
14.13.1 PWM Output Functions ....................................................................................................686
14.14 Registers..................................................................................................................................... 697
14.14.1 Overview of TAUJn Registers .......................................................................................... 697
14.14.2 Details of TAUJn Prescaler Registers.............................................................................. 698
14.14.3 Details of TAUJn Control Registers.................................................................................. 702
14.14.4 Details of TAUJn Output Registers................................................................................... 713
14.14.5 Details of TAUJn Channel Output Level Registers........................................................... 715
14.14.6 Details of TAUJn Reload Data Registers ......................................................................... 716
Section 15 TSG2 (TSG20).............................................................................................718

15.1 Functions of TSG2n.................................................................................................................... 718
15.2 Functional Overview................................................................................................................... 720
15.3 Configuration .............................................................................................................................. 721
15.4 Registers..................................................................................................................................... 722
15.4.1 TSG2n Registers Overview.............................................................................................. 722
15.4.2 TSG2n Register Details.................................................................................................... 724
15.5 Basic Operation.......................................................................................................................... 773
15.5.1 Basic Operation of 16-Bit Counter.................................................................................... 773
15.5.2 Functions of Compare Registers...................................................................................... 775
15.5.3 Compare Register Rewrite Operation .............................................................................. 778
15.5.4 List of Outputs in Each Mode ........................................................................................... 785
15.6 Match Interrupt............................................................................................................................ 791
15.7 Flags........................................................................................................................................... 794
15.7.1 Up Count Flag (TSnCUF and TSnSUF)........................................................................... 795
15.7.2 Positive Phase and Inverse Phase Simultaneous Active State Detection Flag
(TSnTBF0 to TSnTBF2) ................................................................................................... 797
15.7.3 Reload Request Flag (TSnRSF)....................................................................................... 798
15.7.4 Noise Detection Flag (TSnNDF)....................................................................................... 799
15.7.5 Pattern Order Detection Flag (TSnTSF)........................................................................... 800
15.7.6 Pattern Error Detection Flag (TSnPEF)............................................................................ 802
15.7.7 Pattern Reversal Detection Flag (TSnPRF) ..................................................................... 803
15.7.8 TSG2nPTSI2 to TSG2nPTSI0 Pin Abnormal Toggle Detection Flag (TSnPTF).............. 804
15.7.9 TSnOPCI0 and TSnOPCI1 Signal Simultaneous Trigger Detection Flag (TSnTDF) ....... 805
15.7.10 Pattern Phase Difference Detection Flag (TSnPPF)........................................................ 806
15.7.11 Timer Output Pattern Flag (TSnOPF2 to TSnOPF0)........................................................ 807
15.7.12 Pattern Switch Detection Signal (TSnPTE)...................................................................... 808
15.8 Interrupt Skipping Function......................................................................................................... 810
15.8.1 Operation of Interrupt Skipping Function.......................................................................... 811
15.8.2 Example of Operation when Peak Interrupt is Generated (in PWM Mode)...................... 815
15.9 A/D Conversion Trigger Function ............................................................................................... 816
15.9.1 Operation of A/D Conversion Trigger............................................................................... 817
15.10 Error/Warning Interrupt............................................................................................................... 823
15.10.1 Error Interrupt Function .................................................................................................... 823
15.10.2 Warning Interrupt Function............................................................................................... 826
15.11 Operating Modes........................................................................................................................ 827
15.11.1 PWM Mode....................................................................................................................... 828
15.11.2 HT-PWM Mode (High accuracy Triangular - Pulse Width Modulation Mode) .................. 839
15.11.3 SP-PWM Mode (Shifted-pulse - Pulse Width Modulation Mode) ..................................... 861
15.11.4 120-DC Mode................................................................................................................... 873
15.11.5 Software Output Control Function.................................................................................... 907
Section 16 TPBA............................................................................................................909
16.1 Functions of TPBAn.................................................................................................................... 909
16.2 Functional Overview................................................................................................................... 910

16.3 Configuration .............................................................................................................................. 911
16.4 Registers..................................................................................................................................... 912
16.4.1 TPBAn Registers Overview.............................................................................................. 912
16.4.2 TPBAn Registers Details.................................................................................................. 913
16.5 Basic Operation.......................................................................................................................... 926
16.5.1 Basic Operation of Counter .............................................................................................. 926
16.5.2 Compare Register Rewrite Operation .............................................................................. 927
16.5.3 Duty Rewrite Operation.................................................................................................... 930
16.5.4 Basic Operation Example................................................................................................. 933
Section 17 OS Timer (OSTM)........................................................................................938
17.1 OSTM Features.......................................................................................................................... 938
17.2 Functional Overview................................................................................................................... 940
17.3 Functional Description................................................................................................................ 941
17.3.1 Clock Signal to Drive Counting......................................................................................... 941
17.3.2 Output Modes................................................................................................................... 943
17.3.3 Interrupt Request Generation........................................................................................... 944
17.3.4 Starting and Stopping the Timer....................................................................................... 945
17.3.5 Interval Timer Mode.......................................................................................................... 946
17.3.6 Free-Running Comparison Mode..................................................................................... 950
17.4 Registers..................................................................................................................................... 953
17.4.1 OS Timer Registers Overview.......................................................................................... 953
17.4.2 OS Timer Registers in Detail............................................................................................ 954
Section 18 Encoder Timer (ENCA)................................................................................964
18.1 ENCA Features........................................................................................................................... 964
18.2 Functional Overview................................................................................................................... 966
18.2.1 Block Diagram.................................................................................................................. 967
18.3 ENCA Control Registers............................................................................................................. 968
18.4 Functional Description................................................................................................................ 983
18.4.1 Timer Counter Operation.................................................................................................. 983
18.4.2 Up/Down Control of Timer Counter.................................................................................. 987
18.4.3 Control of Timer Counter Clearing.................................................................................... 991
18.4.4 Detailed Description of the ENCAnCCR0 Register.......................................................... 997
18.4.5 Detailed Description of the ENCAnCCR1 Register.......................................................... 999
18.4.6 Timer Counter Operation Start/Stop............................................................................... 1003
18.5 Setting Sequences.................................................................................................................... 1004
18.5.1 Encoder Timer Setting Procedure.................................................................................. 1004
18.6 Timing Charts for Encoder Operations ..................................................................................... 1007
Section 19 Timer Option Module (TAPA).....................................................................1013
19.1 Features of the Timer Option Module....................................................................................... 1013
19.2 Functional Overview................................................................................................................. 1021

19.2.1 Block Diagram................................................................................................................ 1021
19.2.2 Peak and Valley of Timer Counter, and Peak and Valley Interrupts .............................. 1022
19.3 Registers................................................................................................................................... 1023
19.3.1 Registers Overview ........................................................................................................ 1023
19.3.2 Registers Details ............................................................................................................ 1024
19.4 Basic Functions ........................................................................................................................ 1030
19.4.1 Hi-Z Control Functions.................................................................................................... 1030
19.4.2 Asynchronous Hi-Z Control for Pin Inputs...................................................................... 1031
19.4.3 Selection of INT Signal Output....................................................................................... 1037
19.4.4 Selecting a Trigger to Start Conversion by the A/D Converter....................................... 1041
Section 20 CAN Controller (FCN)................................................................................1046
20.1 FCN Features........................................................................................................................... 1046
20.2 Features ................................................................................................................................... 1048
20.2.1 Overview of Functions.................................................................................................... 1049
20.2.2 Configuration.................................................................................................................. 1050
20.3 Internal Registers of FCN......................................................................................................... 1051
20.3.1 CAN Controller Configuration......................................................................................... 1051
20.3.2 Overview of CAN Controller Registers........................................................................... 1052
20.3.3 Register Bit Configuration...............................................................................................1054
20.4 Bit Set/Clear Functions............................................................................................................. 1059
20.5 Control Registers...................................................................................................................... 1061
20.5.1 FCN Global Registers..................................................................................................... 1061
20.5.2 FCN Module Registers................................................................................................... 1069
20.5.3 FCN Message Buffer Registers...................................................................................... 1089
20.6 CAN Controller Initialization...................................................................................................... 1099
20.6.1 Initialization of FCN Module............................................................................................ 1099
20.6.2 Redefinition of Message Buffer ...................................................................................... 1099
20.6.3 Transition from Initialization Mode to Operating Mode................................................... 1101
20.7 Reception of Message.............................................................................................................. 1102
20.7.1 Message Reception........................................................................................................ 1102
20.7.2 Receive Data Read ........................................................................................................ 1103
20.7.3 Receive History List Function......................................................................................... 1104
20.7.4 Mask Function................................................................................................................ 1106
20.7.5 Multi Buffer Receive Block Function............................................................................... 1107
20.7.6 Remote Frame Reception .............................................................................................. 1108
20.8 Transmission of Message......................................................................................................... 1110
20.8.1 Message Transmission................................................................................................... 1110
20.8.2 Transmit History List Function........................................................................................ 1112
20.8.3 Automatic Block Transmission (ABT)............................................................................. 1114
20.8.4 Transmission Abort Process........................................................................................... 1116
20.8.5 Remote Frame Transmission......................................................................................... 1117
20.9 Power Save Modes................................................................................................................... 1118
20.9.1 FCN Sleep Mode............................................................................................................ 1118

20.9.2 FCN Stop Mode.............................................................................................................. 1121
20.9.3 Example of Using Power Save Modes ........................................................................... 1122
20.10 Interrupt Function...................................................................................................................... 1123
20.11 Diagnosis Functions and Special Operating Modes................................................................. 1124
20.11.1 Receive-only Mode......................................................................................................... 1124
20.11.2 Single-shot Mode............................................................................................................ 1125
20.11.3 Self-test Mode ................................................................................................................ 1126
20.11.4 Receive/Transmit Operations in Each Operating Mode................................................. 1127
20.12 Time Stamp Function................................................................................................................ 1128
20.12.1 Time Stamp Function ..................................................................................................... 1128
20.13 Baud Rate Settings................................................................................................................... 1130
20.13.1 Baud Rate Setting Conditions ........................................................................................ 1130
20.13.2 Typical Examples of Baud Rate Settings ....................................................................... 1133
20.14 Operation of the CAN Controller............................................................................................... 1137
20.14.1 Initialization..................................................................................................................... 1137
20.14.2 Message Transmission................................................................................................... 1143
20.14.3 Message Reception........................................................................................................ 1158
20.14.4 Power Save Modes ........................................................................................................ 1163
Section 21 Clocked Serial Interface G (CSIG).............................................................1170
21.1 CSIG Features.......................................................................................................................... 1170
21.2 Functional Overview................................................................................................................. 1172
21.3 Functional Description.............................................................................................................. 1174
21.3.1 Master/Slave Mode......................................................................................................... 1174
21.3.2 Master/Slave Connections.............................................................................................. 1175
21.3.3 Selection of Serial Communications Clock..................................................................... 1176
21.3.4 Data Transfer Modes...................................................................................................... 1177
21.3.5 Data length Selection ..................................................................................................... 1178
21.3.6 Serial Data Direction Selection....................................................................................... 1180
21.3.7 Communication in Slave Mode....................................................................................... 1181
21.3.8 CSIG Interrupts............................................................................................................... 1182
21.3.9 Handshake Function....................................................................................................... 1185
21.3.10 Loop-Back Mode ............................................................................................................ 1187
21.3.11 Error Detection ............................................................................................................... 1188
21.4 CSIG Control Registers ............................................................................................................ 1192
21.5 Operating Procedure Example ................................................................................................. 1207
Section 22 Synchronous/Asynchronous Serial Interface H (UARTH)..........................1209
22.1 UARTHn Features.................................................................................................................... 1209
22.2 Features.................................................................................................................................... 1211
22.3 Configuration ............................................................................................................................ 1212
22.4 UARTHn Registers ................................................................................................................... 1213
22.5 Interrupt Request Signals......................................................................................................... 1242
22.5.1 Transmission Interrupt Request URTHnTIT................................................................... 1242

22.5.2 Reception Interrupt Request URTHnTIR........................................................................ 1243
22.5.3 Status Interrupt Request URTHnTIS.............................................................................. 1243
22.6 Operation.................................................................................................................................. 1244
22.6.1 Data Formats.................................................................................................................. 1244
22.6.2 Clock Synchronous Mode............................................................................................... 1247
22.6.3 Handshake Mode ........................................................................................................... 1248
22.6.4 Consecutive Two-Frame Transfer Mode........................................................................ 1250
22.6.5 Extension bit Detection/ID Compare-Match Detection................................................... 1252
22.6.6 BF Transmission/Reception Format............................................................................... 1254
22.6.7 BF Transmission............................................................................................................. 1256
22.6.8 BF Reception.................................................................................................................. 1257
22.6.9 Transmission Data Consistency Check.......................................................................... 1259
22.6.10 UARTHn Transmission................................................................................................... 1260
22.6.11 Continuous Transmission Procedure ............................................................................. 1261
22.6.12 UARTHn reception ......................................................................................................... 1263
22.6.13 Reception Errors............................................................................................................. 1265
22.6.14 Parity Types and Operations.......................................................................................... 1266
22.6.15 Digital Receive Data Noise Filter.................................................................................... 1267
22.7 Baud-Rate Generator ............................................................................................................... 1268
22.8 Detecting the Baud Rate in LIN Communications as a Slave................................................... 1269
Section 23 A/D Converter............................................................................................1270
23.1 ADCA Features......................................................................................................................... 1270
23.2 Functional Overview................................................................................................................. 1273
23.3 Functional Description.............................................................................................................. 1275
23.3.1 Basic Operation.............................................................................................................. 1277
23.3.2 Clock Usage................................................................................................................... 1278
23.3.3 Channel and Channel Group.......................................................................................... 1279
23.3.4 A/D Conversion Modes................................................................................................... 1281
23.3.5 Starting A/D Conversion (Start Triggers)........................................................................ 1285
23.3.6 Stopping A/D Conversion (Stop Trigger)........................................................................ 1287
23.3.7 Resolution, Sampling Time and Conversion Time ......................................................... 1288
23.3.8 Interrupt Generation ....................................................................................................... 1290
23.3.9 Storage of A/D Conversion Results................................................................................ 1291
23.3.10 Result Check Functions.................................................................................................. 1294
23.3.11 Self-Diagnosis Functions................................................................................................ 1296
23.3.12 Channel Sample and Hold Function............................................................................... 1305
23.3.13 Discharge Function......................................................................................................... 1310
23.3.14 Buffer Amplifier Function................................................................................................ 1311
23.3.15 Stabilization Control........................................................................................................ 1311
23.4 Registers................................................................................................................................... 1312
23.4.1 ADCAn Registers Overview ........................................................................................... 1312
23.4.2 Control Registers............................................................................................................ 1314
23.4.3 Conversion Status Registers.......................................................................................... 1324
23.4.4 Software Trigger Registers............................................................................................. 1328

23.4.5 A/D Conversion Result Registers................................................................................... 1329
23.4.6 A/D Conversion Result Upper/Lower Limit Comparison Registers ................................ 1337
23.4.7 Diagnosis Function Control Registers ............................................................................ 1341
23.4.8 Channel Sample and Hold Function Setting Register.................................................... 1344
23.5 Usage Notes............................................................................................................................. 1345
23.5.1 Range of Channel Input Voltage .................................................................................... 1345
23.5.2 Stopping Conversion Operation ..................................................................................... 1345
23.5.3 Restrictions on Using Channel Sample and Hold Function............................................ 1345
23.5.4 Application Design Notes ............................................................................................... 1345
23.6 How to Read A/D Converter Characteristics Table .................................................................. 1350
Section 24 Peripheral Interconnection (PIC)................................................................1357
24.1 Features of Peripheral Interconnection..................................................................................... 1357
24.2 Functional Overview................................................................................................................. 1358
24.3 Peripheral Interconnection Registers........................................................................................ 1359
24.3.1 Start of PIC Function...................................................................................................... 1361
24.4 Connection Functions............................................................................................................... 1362
24.4.1 Simultaneous Start Trigger Function.............................................................................. 1362
24.4.2 ADC Trigger Selection Function..................................................................................... 1369
24.4.3 High Accuracy Triangle Wave PWM Output Function with Dead Time.......................... 1377
24.4.4 Trigger and Pulse Width Measurement Function ........................................................... 1408
24.4.5 Encoder Capture Trigger Selection Function ................................................................. 1422
24.4.6 Two-Phase Encoder Control Function (Control Method 1)............................................. 1432
24.4.7 Two-Phase Encoder Control Function (Control Method 2)............................................. 1444
24.4.8 Three-Phase Encoder Control Function......................................................................... 1455
24.4.9 CAN Time Stamp Function............................................................................................. 1464
24.4.10 TSG20 and TAUB0 Dead-Time Reduction Function...................................................... 1466
24.4.11 TAUB Input Selection..................................................................................................... 1478
Section 25 On-chip Debugging Unit (OCD).................................................................1483
25.1 Functional Overview................................................................................................................. 1483
25.2 Connection with the On-Chip Debugging Emulator.................................................................. 1486
25.3 Notes on On-Chip Debugging................................................................................................... 1489
Section 26 Power Supply Configuration ......................................................................1493
Section 27 Electrical Characteristics............................................................................1494
27.1 Absolute Maximum Ratings...................................................................................................... 1494
27.2 Capacity.................................................................................................................................... 1495
27.3 Operating Conditions................................................................................................................ 1495
27.4 Characteristics of Oscillation Circuit......................................................................................... 1496
27.4.1 Characteristics of Oscillation Circuit............................................................................... 1496
27.4.2 Characteristics of Internal Oscillation Circuit.................................................................. 1497
27.5 DC Characteristics.................................................................................................................... 1498

27.6 AC Characteristics.................................................................................................................... 1502
27.6.1 Measurement Conditions................................................................................................ 1502
27.6.2 Clock Timing (CLKOUT)................................................................................................. 1503
27.6.3 Timing in Turning the Power Supply On and Off............................................................ 1504
27.6.4 Regulator Characteristics............................................................................................... 1506
27.6.5 Reset Timing .................................................................................................................. 1507
27.6.6 Interrupt Timing .............................................................................................................. 1508
27.6.7 ESOn Timing.................................................................................................................. 1509
27.6.8 ADCA0TRGn Timing ...................................................................................................... 1510
27.6.9 Timer Timing................................................................................................................... 1511
27.6.10 CSIGn Timing................................................................................................................. 1512
27.6.11 UARTHn Timing ............................................................................................................. 1518
27.6.12 CAN Timing.................................................................................................................... 1525
27.6.13 Nexus Interface Timing................................................................................................... 1526
27.6.14 LPD Interface.................................................................................................................. 1527
27.6.15 A/D Converter Characteristics........................................................................................ 1528
27.6.16 POF/LVI Characteristics................................................................................................. 1533
27.6.17 Flash Memory Programming Characteristics ................................................................. 1535
27.6.18 FLMD0 Pulse Timing Characteristics............................................................................. 1536
27.6.19 Self-Diagnosis BIST Execution Time.............................................................................. 1538