Renesas V850ES/IE2 User manual

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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

V850ES/IE2
32-bit Single-Chip Microcontrollers
Hardware
Printed in Japan
User’s Manual
μ
PD70F3713
μ PD70F3714
Document No. U17716EJ2V0UD00 (2nd edition)
Date Published February 2008 N
2005

User’s Manual U17716EJ2V0UD
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[MEMO]

User’s Manual U17716EJ2V0UD 3
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4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL (MAX) and V IH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6

User’s Manual U17716EJ2V0UD
4
The information in this document is current as of January, 2008. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics
(as defined above).
•
•
•
•
•
•
M8E 02. 11-1

User’s Manual U17716EJ2V0UD 5
PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/IE2 to design application systems using the V850ES/IE2.
Purpose This manual is intended to give users an understanding of the hardware functions.
Organization The V850ES/IE2 User’s Manual is divided into two parts: Hardware (this manual) and
Architecture (V850ES Architecture User’s Manual). The organization of each manual
is as follows:
Hardware Architecture
•Pin functions •Data type
•CPU function •Register set
•On-chip peripheral functions •Instruction format and instruction set
•Flash memory programming •Interrupts and exceptions
•Electrical specifications •Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
•To understand the overall functions of the V850ES/IE2
→Read this manual according to the CONTENTS.
•To find the details of a register where the name is known
→See APPENDIX B REGISTER INDEX.
•How to interpret the register format
→For a bit whose bit number is enclosed in angle brackets < >, its bit name is
defined as a reserved word in the device file.
•To understand the details of an instruction function
→Refer to the V850ES Architecture User’s Manual.
•To know the electrical specifications of the V850ES/IE2
→See CHAPTER 19 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched
by copying an “<R>” in the PDF file and specifying it in the "Find what:" field.

User’s Manual U17716EJ2V0UD
6
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on
the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity): K (kilo): 210 = 1,024
M (mega): 220 = 1,0242
G (giga): 230 = 1,0243
Data type: Word ... 32 bits
Halfword ... 16 bits
Byte ... 8 bits

User’s Manual U17716EJ2V0UD 7
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/IE2
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/IE2 Hardware User’s Manual This manual
Documents related to development tools (user’s manuals)
Document Name Document No.
QB-V850ESIX2 (in-circuit emulator) U17909E
QB-MINI2 (On-Chip Debug Emulator with Programming Function) U18371E
Operation U17293E
C Language U17291E
Assembly Language U17292E
CA850 (Ver. 3.00) (C compiler package)
Link Directive U17294E
PM+ (Ver. 6.30) (Project manager) U18416E
ID850QB (Ver. 3.40) (Integrated debugger) Operation U18604E
TW850 (Ver. 2.00) (Performance analysis tuning tool) U17241E
Basics U13430E
Installation U17419E
Technical U13431E
RX850 (Ver. 3.20) (Real-time OS)
Task Debugger U17420E
Basics U18165E
Installation U17421E
Technical U13772E
RX850 Pro (Ver. 3.21) (Real-time OS)
Task Debugger U17422E
AZ850 (Ver. 3.30) (System performance analyzer) U17423E
PG-FP4 Flash Memory Programmer U15260E
PG-FP5 Flash Memory Programmer U18865E

User’s Manual U17716EJ2V0UD
8
CONTENTS
CHAPTER 1 INTRODUCTION................................................................................................................. 14
1.1 General .......................................................................................................................................14
1.2 Features .....................................................................................................................................15
1.3 Applications...............................................................................................................................16
1.4 Ordering Information ................................................................................................................16
1.5 Pin Configuration ......................................................................................................................17
1.6 Function Blocks ........................................................................................................................19
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 22
2.1 List of Pin Functions.................................................................................................................22
2.2 Pin I/O Circuits and Recommended Connection of Unused Pins........................................26
2.3 Pin I/O Circuits...........................................................................................................................28
CHAPTER 3 CPU FUNCTION................................................................................................................ 29
3.1 Features .....................................................................................................................................29
3.2 CPU Register Set.......................................................................................................................30
3.2.1 Program register set .....................................................................................................................31
3.2.2 System register set .......................................................................................................................32
3.3 Operating Modes.......................................................................................................................38
3.4 Address Space ..........................................................................................................................39
3.4.1 CPU address space......................................................................................................................39
3.4.2 Wraparound of CPU address space .............................................................................................40
3.4.3 Memory map.................................................................................................................................41
3.4.4 Areas ............................................................................................................................................43
3.4.5 Recommended use of address space...........................................................................................47
3.4.6 On-chip peripheral I/O registers....................................................................................................50
3.4.7 Special registers ...........................................................................................................................56
3.4.8 System wait control register (VSWC)............................................................................................61
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 62
4.1 Features .....................................................................................................................................62
4.2 Basic Port Configuration..........................................................................................................62
4.3 Port Configuration.....................................................................................................................63
4.3.1 Port 0 ............................................................................................................................................67
4.3.2 Port 1 ............................................................................................................................................73
4.3.3 Port 2 ............................................................................................................................................85
4.3.4 Port 3 ............................................................................................................................................91
4.3.5 Port 4 ............................................................................................................................................98
4.3.6 Port DL........................................................................................................................................105
4.4 Output Data and Read Value of Port for Each Setting ....................................................... 108
4.5 Port Register Settings When Alternate Function Is Used.................................................. 113
4.6 Noise Eliminator ..................................................................................................................... 117
4.7 Cautions .................................................................................................................................. 119
4.7.1 Cautions on setting port pins ......................................................................................................119

User’s Manual U17716EJ2V0UD 9
4.7.2 Cautions on bit manipulation instruction for port n register (Pn) .................................................120
CHAPTER 5 CLOCK GENERATOR .....................................................................................................121
5.1 Overview ..................................................................................................................................121
5.2 Configuration ..........................................................................................................................122
5.3 Control Registers....................................................................................................................124
5.4 PLL Function ...........................................................................................................................130
5.4.1 Overview.....................................................................................................................................130
5.4.2 PLL mode ...................................................................................................................................130
5.4.3 Clock-through mode ...................................................................................................................130
5.5 Operation .................................................................................................................................131
5.5.1 Operation of each clock.............................................................................................................. 131
5.5.2 Operation timing .........................................................................................................................132
5.6 Clock Monitor ..........................................................................................................................135
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................137
6.1 Overview ..................................................................................................................................137
6.2 Functions .................................................................................................................................137
6.3 Configuration ..........................................................................................................................138
6.4 Registers..................................................................................................................................143
6.5 Timer Output Operations .......................................................................................................156
6.6 Operation .................................................................................................................................157
6.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)................................................................165
6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001) ....................................................177
6.6.3 External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010)......................................186
6.6.4 One-shot pulse output mode (TPmMD2 to TPmMD0 bits = 011) ...............................................199
6.6.5 PWM output mode (TPmMD2 to TPmMD0 bits = 100)...............................................................206
6.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .......................................................215
6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110)............................................232
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................238
7.1 Overview ..................................................................................................................................238
7.2 Functions .................................................................................................................................239
7.3 Configuration ..........................................................................................................................239
7.4 Registers..................................................................................................................................244
7.5 Timer Output Operations .......................................................................................................260
7.6 Operation .................................................................................................................................261
7.6.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) ............................................................... 269
7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ...................................................281
7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .......................................291
7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011).................................................305
7.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100)................................................................ 314
7.6.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ......................................................325
7.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................... 345
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM).............................................................................351
8.1 Overview ..................................................................................................................................351

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8.2 Configuration.......................................................................................................................... 352
8.3 Control Register ..................................................................................................................... 353
8.4 Operation ................................................................................................................................ 354
8.4.1 Interval timer mode .....................................................................................................................354
8.5 Cautions .................................................................................................................................. 358
CHAPTER 9 MOTOR CONTROL FUNCTION .................................................................................... 359
9.1 Functional Overview .............................................................................................................. 359
9.2 Configuration.......................................................................................................................... 360
9.3 Control Registers ................................................................................................................... 364
9.4 Operation ................................................................................................................................ 377
9.4.1 System outline ............................................................................................................................377
9.4.2 Dead-time control (generation of negative-phase wave signal) ..................................................382
9.4.3 Interrupt culling function..............................................................................................................389
9.4.4 Operation to rewrite register with transfer function......................................................................396
9.4.5 TMP1 tuning operation for A/D conversion start trigger signal output .........................................414
9.4.6 A/D conversion start trigger output function ................................................................................417
CHAPTER 10 WATCHDOG TIMER FUNCTIONS .............................................................................. 422
10.1 Functions ................................................................................................................................ 422
10.2 Configuration.......................................................................................................................... 423
10.3 Control Registers ................................................................................................................... 424
10.4 Operation ................................................................................................................................ 425
10.5 Caution .................................................................................................................................... 425
CHAPTER 11 A/D CONVERTERS 0 AND 1 ..................................................................................... 426
11.1 Features .................................................................................................................................. 426
11.2 Configuration.......................................................................................................................... 427
11.3 Control Registers ................................................................................................................... 431
11.4 Operation ................................................................................................................................ 438
11.4.1 Basic operation ...........................................................................................................................438
11.4.2 Operation mode and trigger mode ..............................................................................................439
11.5 Operation in Software Trigger Mode.................................................................................... 450
11.5.1 Continuous select mode operations............................................................................................450
11.5.2 Continuous scan mode operations..............................................................................................453
11.5.3 One-shot select mode operations ...............................................................................................454
11.5.4 One-shot scan mode operations.................................................................................................456
11.6 Operation in Timer Trigger Mode ......................................................................................... 457
11.6.1 Continuous select mode/one-shot select mode operations.........................................................458
11.6.2 Continuous scan mode/one-shot scan mode operations ............................................................460
11.7 Operation in External Trigger Mode..................................................................................... 461
11.7.1 Continuous select mode/one-shot select mode operations.........................................................462
11.7.2 Continuous scan mode/one-shot scan mode operations ............................................................464
11.8 Internal Equivalent Circuit..................................................................................................... 465
11.9 Notes on Operation................................................................................................................ 467
11.9.1 Stopping conversion operation....................................................................................................467
11.9.2 Timer/external trigger interval .....................................................................................................467
11.9.3 Operation in standby mode.........................................................................................................467

User’s Manual U17716EJ2V0UD 11
11.9.4 Timer interrupt request signal in timer trigger mode ...................................................................468
11.9.5 Re-conversion start trigger input during stabilization time ..........................................................468
11.9.6 Variation of A/D conversion results............................................................................................. 468
11.9.7 A/D conversion result hysteresis characteristics.........................................................................468
11.9.8 Restrictions on setting one-shot mode and software trigger mode .............................................469
11.10 How to Read A/D Converter Characteristics Table .............................................................470
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)..............................................474
12.1 Features ...................................................................................................................................474
12.2 Configuration ..........................................................................................................................475
12.3 Control Registers....................................................................................................................477
12.4 Interrupt Request Signals ......................................................................................................482
12.5 Operation .................................................................................................................................483
12.5.1 Data format................................................................................................................................. 483
12.5.2 UART transmission.....................................................................................................................485
12.5.3 Continuous transmission procedure ...........................................................................................486
12.5.4 UART reception ..........................................................................................................................488
12.5.5 Reception errors .........................................................................................................................489
12.5.6 Parity types and operations ........................................................................................................ 490
12.5.7 Receive data noise filter .............................................................................................................491
12.6 Dedicated Baud Rate Generator............................................................................................492
12.7 Cautions...................................................................................................................................499
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................500
13.1 Features ...................................................................................................................................500
13.2 Configuration ..........................................................................................................................501
13.3 Control Registers....................................................................................................................503
13.4 Operation .................................................................................................................................510
13.4.1 Single transfer mode (master mode, transmission mode) ..........................................................510
13.4.2 Single transfer mode (master mode, reception mode)................................................................512
13.4.3 Single transfer mode (master mode, transmission/reception mode)...........................................514
13.4.4 Single transfer mode (slave mode, transmission mode) ............................................................. 516
13.4.5 Single transfer mode (slave mode, reception mode) ..................................................................518
13.4.6 Single transfer mode (slave mode, transmission/reception mode) .............................................520
13.4.7 Continuous transfer mode (master mode, transmission mode) ..................................................522
13.4.8 Continuous transfer mode (master mode, reception mode)........................................................524
13.4.9 Continuous transfer mode (master mode, transmission/reception mode)...................................527
13.4.10 Continuous transfer mode (slave mode, transmission mode)..................................................... 531
13.4.11 Continuous transfer mode (slave mode, reception mode) ..........................................................533
13.4.12 Continuous transfer mode (slave mode, transmission/reception mode) .....................................536
13.4.13 Reception error........................................................................................................................... 540
13.4.14 Clock timing ................................................................................................................................541
13.5 Output Pins..............................................................................................................................543
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................544
14.1 Features ...................................................................................................................................544
14.2 Non-Maskable Interrupts........................................................................................................548
14.2.1 Operation....................................................................................................................................549

User’s Manual U17716EJ2V0UD
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14.2.2 Restore .......................................................................................................................................550
14.2.3 Non-maskable interrupt status flag (NP) .....................................................................................551
14.3 Maskable Interrupts ............................................................................................................... 552
14.3.1 Operation ....................................................................................................................................552
14.3.2 Restore .......................................................................................................................................554
14.3.3 Priorities of maskable interrupts..................................................................................................555
14.3.4 Interrupt control registers (xxICn) ...............................................................................................559
14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)...........................................................................562
14.3.6 In-service priority register (ISPR)................................................................................................564
14.3.7 Maskable interrupt status flag (ID) ..............................................................................................565
14.4 External Interrupt Request Input Pins (INTP0 to INTP6) .................................................... 566
14.4.1 Noise elimination.........................................................................................................................566
14.4.2 Edge detection............................................................................................................................567
14.5 Software Exception................................................................................................................ 568
14.5.1 Operation ....................................................................................................................................568
14.5.2 Restore .......................................................................................................................................569
14.5.3 Exception status flag (EP)...........................................................................................................570
14.6 Exception Trap ....................................................................................................................... 571
14.6.1 Illegal opcode definition ..............................................................................................................571
14.6.2 Debug trap ..................................................................................................................................573
14.7 Multiple Interrupt Servicing Control..................................................................................... 575
14.8 Interrupt Response Time of CPU.......................................................................................... 577
14.9 Periods in Which CPU Does Not Acknowledge Interrupts ................................................ 578
14.10 Caution .................................................................................................................................... 578
CHAPTER 15 STANDBY FUNCTION .................................................................................................. 579
15.1 Overview ................................................................................................................................. 579
15.2 Control Registers ................................................................................................................... 581
15.3 HALT Mode ............................................................................................................................. 583
15.3.1 Setting and operation status .......................................................................................................583
15.3.2 Releasing HALT mode................................................................................................................583
15.4 IDLE Mode............................................................................................................................... 585
15.4.1 Setting and operation status .......................................................................................................585
15.4.2 Releasing IDLE mode .................................................................................................................585
15.5 STOP Mode ............................................................................................................................. 587
15.5.1 Setting and operation status .......................................................................................................587
15.5.2 Releasing STOP mode ...............................................................................................................587
15.6 Securing Oscillation Stabilization Time............................................................................... 589
CHAPTER 16 RESET FUNCTIONS ..................................................................................................... 590
16.1 Overview ................................................................................................................................. 590
16.2 Registers to Check Reset Source ........................................................................................ 590
16.3 Operation ................................................................................................................................ 592
16.3.1 Reset operation via RESET pin ..................................................................................................592
16.3.2 Reset operation by watchdog timer (WDT) overflow (WDTRES)................................................594
16.3.3 Low-voltage detector (LVI)..........................................................................................................595
16.3.4 Power-on-clear circuit (POC) ......................................................................................................603

User’s Manual U17716EJ2V0UD 13
CHAPTER 17 REGULATOR ..................................................................................................................605
17.1 Overview ..................................................................................................................................605
17.2 Operation .................................................................................................................................606
CHAPTER 18 FLASH MEMORY...........................................................................................................607
18.1 Features ...................................................................................................................................607
18.2 Memory Configuration............................................................................................................608
18.3 Functional Overview...............................................................................................................609
18.4 Rewriting by Dedicated Flash Memory Programmer ..........................................................613
18.4.1 Programming environment .........................................................................................................613
18.4.2 Communication mode................................................................................................................. 614
18.4.3 Flash memory control .................................................................................................................619
18.4.4 Selection of communication mode..............................................................................................620
18.4.5 Communication commands ........................................................................................................621
18.4.6 Pin connection ............................................................................................................................622
18.5 Rewriting by Self Programming (
μ PD70F3714 only) ...........................................................627
18.5.1 Overview.....................................................................................................................................627
18.5.2 Features .....................................................................................................................................628
18.5.3 Standard self programming flow .................................................................................................629
18.5.4 Flash functions ...........................................................................................................................630
18.5.5 Pin processing ............................................................................................................................630
18.5.6 Internal resources used ..............................................................................................................631
CHAPTER 19 ELECTRICAL SPECIFICATIONS..................................................................................632
CHAPTER 20 PACKAGE DRAWING ...................................................................................................651
CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS ...........................................................652
APPENDIX A CAUTIONS.......................................................................................................................653
A.1 Restriction on Conflict Between sld Instruction and Interrupt Request...........................653
A.1.1 Description..................................................................................................................................653
A.1.2 Countermeasure.........................................................................................................................653
APPENDIX B REGISTER INDEX..........................................................................................................654
APPENDIX C INSTRUCTION SET LIST..............................................................................................659
C.1 Conventions ............................................................................................................................659
C.2 Instruction Set (in Alphabetical Order).................................................................................662
APPENDIX D REVISION HISTORY ......................................................................................................669
D.1 Major Revisions in This Edition.............................................................................................669
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User’s Manual U17716EJ2V0UD
14
CHAPTER 1 INTRODUCTION
The V850ES/IE2 is one of the low-power operation products in the NEC Electronics V850 Series of single-chip
microcontrollers designed for real-time control applications.
1.1 General
The V850ES/IE2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions
such as ROM/RAM, a timer/counter, serial interfaces, a watchdog timer, and an A/D converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/IE2 features
instructions such as multiply instructions, saturated operation instructions, and bit manipulation instructions realized by
a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control
system, the V850ES/IE2 enables an extremely high cost-performance for applications such as motor inverter control.

CHAPTER 1 INTRODUCTION
User’s Manual U17716EJ2V0UD 15
1.2 Features
{Minimum instruction execution time:
50 ns (at internal 20 MHz operation)
{General-purpose registers: 32 bits ×32
{CPU features: Signed multiplication (16 ×16 →32): 1 to 2 clocks
Signed multiplication (32 ×32 →64): 1 to 5 clocks
Saturated operation instructions (with overflow/underflow detection function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
Part Number Internal ROM Internal RAM
μ PD70F3713 64 KB (flash memory) 6 KB
{Internal memory:
μ PD70F3714 128 KB (flash memory) 6 KB
{Interrupts/exceptions: Non-maskable interrupts: 1 source (external: none, internal: 1)
Maskable interrupts: 42 sources (external: 7, internal: 35)
Software exceptions: 32 sources
Exception traps: 2 sources
{I/O lines: I/O ports: 39
{Timer/counter function: 16-bit interval timer M (TMM): 1 channel
16-bit timer/event counter Q (TMQ): 2 channels
16-bit timer/event counter P (TMP): 4 channels
Motor control function (uses timer TMQ: 1 channel (TMQ1), TMP: 1 channel (TMP1))
16-bit accuracy 6-phase PWM function with dead time: 1 channel
High-impedance output control function
Timer tuning operation function
Arbitrary cycle setting function
Arbitrary dead-time setting function
Watchdog timer: 1 channel
{Serial interfaces: Asynchronous serial interface A (UARTA)
3-wire variable length serial I/O (CSIB)
CSIB: 1 channel
UARTA: 2 channels
{A/D converter: 10-bit resolution A/D converters (A/D converters 0 and 1): 4 channels ×2 units

CHAPTER 1 INTRODUCTION
User’s Manual U17716EJ2V0UD
16
{Clock generator: 2.5 MHz resonator connectable (external clock input prohibited)
Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, fXX =
20 MHz)
CPU clock division function (fXX, fXX/2, fXX/4, fXX/8)
{Power-save function: HALT/IDLE/ STOP mode
{Power-on-clear function
{Low-voltage detection function
{Self programming Supported only in the
μ PD70F3714 (not supported in the μ PD70F3713)
{Package: 64-pin plastic LQFP (14 ×14)
O Operation supply voltage: VDD = EVDD = 3.5 to 5.5 V
AVDD0, AVDD1 = 4.5 to 5.5 V
O Operation ambient temperature:
T
A= −40 to +85°C
1.3 Applications
•Consumer appliances (such as inverter air conditioners, refrigerators, washing machines, etc.)
•Industrial equipment (such as motor control and general-purpose inverters, etc.)
1.4 Ordering Information
Part Number Package Internal ROM
μ PD70F3713GC-8BS-A 64-pin plastic LQFP (14 ×14) Flash memory (64 KB)
μ PD70F3714GC-8BS-A 64-pin plastic LQFP (14 ×14) Flash memory (128 KB)
Remark Products with -A at the end of the part number are lead-free products.

CHAPTER 1 INTRODUCTION
User’s Manual U17716EJ2V0UD 17
1.5 Pin Configuration
•64-pin plastic LQFP (14 ×14)
μ PD70F3713GC-8BS-A
μ PD70F3714GC-8BS-A
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P25/TOQ1B3
P24/TOQ1T3
P23/TOQ1B2
P22/TOQ1T2
P21/TOQ1B1
P20/TOQ1T1
ANI13
ANI12
ANI11
ANI10
AV
REF1
AV DD1
AV SS1
AV SS0
AV DD0
AV REF0
PDL3
PDL4
PDL5/FLMD1
PDL6
PDL7
EV
SS
EV DD
FLMD0
P10/TOQH01/TIQ01/TOQ01
P11/TIQ02/TOQ02
P12/TOQH02/TIQ03/TOQ03
P13/TIQ00
P14/TOQH03/EVTQ0
P16(CLMER)
Note
/TOQ00(CLMER)
Note
/TIP20
P17/TOP21/TIP21
P00/INTP0/TOQH0OFF
ANI00 ANI01 ANI02 ANI03
RESET
X1 X2
V
SS
V
DD
REGC
P06/INTP6
P05/INTP5/ADTRG1 P04/INTP4/ADTRG0
P03/INTP3/TOP3OFF P02/INTP2/TOP2OFF
P01/INTP1/TOQ1OFF
EV
SS
EV
DD
P26/TOQ10 P27/TOP31 P30/RXDA0 P31/TXDA0 P32/RXDA1 P33/TXDA1 P40/SIB0 P41/SOB0 P42/SCKB0 P43/TOP00/TIP00 P44/TOP01/TIP01 PDL0 PDL1 PDL2
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of
TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output.
Low-level output is released by reset signal. For details, see Table 4-5 Alternate-Function Pins of
Port 1.