Renesas RAA226110 User manual

RTKA226110DE0010BU
Evaluation Board
X0115710 Rev.1.00 Page 1 of 25
Dec.7.20
User Manual
This user manual discusses the RTKA226110DE0010BU with GS66508B GaN E-HEMT daughter board and
GS665MB-EVB evaluation platform. The RTKA226110DE0010BU is a gate drive evaluation board following the
GS665XXX-EVBDB daughter board style and uses the RAA226110 device. This evaluation board consists of two
GaN Systems 650V GaN Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half-bridge
gate drivers, isolated power supplies, and an optional heatsink to form a functional half-bridge power stage. It
allows you to evaluate the GaN E-HEMT performance in any half-bridge-based topology, either with the universal
mother board (GS665MB-EVB) or your own system design. The RTKA226110DE0010BU evaluation board
provides a 0V turn-off voltage solution. A 0V turn-off solution is normally used in low power applications. A 0V
turn-off solution is easy to implement as there is no need for a negative power supply rail and the reverse
conduction voltage drop of GaN is lower. For the E-mode GaN device, the VGS threshold voltage is low (typical
1.7V). A 0V turn-off has the risk of false turn-on when the GaN device is in an off state. Also, the switching-off loss
is higher than the negative turn-off voltage. The 0V turn-off solution is normally used in low power applications.
Read the entire user manual and, specifically, the warnings and restrictions notices before handling the product.
Persons handling the product(s) must have electronics training and observe good engineering practice standards.
Features
• Serves as a reference design and evaluation tool in addition to a deployment-ready solution for easy in-system
evaluation.
• Vertical mount style with the height of 35mm that fits in the majority of 1U designs and allows evaluation of a
GaN E-HEMT in traditional through-hole type power supply board.
• Current shunt position for switching characterization testing
• Universal form factor and footprint for all products
• 0V turn off voltage
Related Literature
For a full list of related documents, visit our website:
•RAA226110 device page
Ordering Information
Part Number Description
RTKA226110DE0010BU RAA226110 evaluation board
DANGER!
This evaluation board is designed for engineering evaluation in a controlled lab environment and should be handled by
qualified personnel ONLY. High voltage is exposed on the board during the test and even brief contact during operation
may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized, always wait until all capacitors are discharged
before touching the board.
CAUTION:
This product contains parts that are susceptible to damage by Electrostatic Discharge (ESD). Always follow ESD
prevention procedures when handling the product.

RTKA226110DE0010BU
X0115710 Rev.1.00 Page 2 of 25
Dec.7.20
Figure 1. RTKA226110DE0010BU Evaluation Board Block Diagram
VCC
ENABLE
PWMH
PWML Isolat or
IL611-1E
Isolator
IL611-1E
Iso. DC/DC
Iso. DC/DC
RAA226110
Gate Driver
RAA226110
Gate Driver
Q1
Q2
VDC+
VSW
VDC-
C4-10
Shunt

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 3 of 25
Dec.7.20
1. Functional Description
1.1 Control and Power I/Os:
The daughter board RTKA226110DE0010BU circuit diagram is shown in Figure 1. The control logic inputs on the
2x3 pin header J1 are listed in Table 1.
The three power pins are:
• VDC+: Input DC Bus voltage
• VSW: Switching node output
• VDC-: Input DC bus voltage ground return. Note: Control ground 0V is isolated from VDC-
1.2 Using RTKA226110DE0010BU with Universal Mother Board GS665MB-EVB
GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold separately)
that can be used as the basic evaluation platform for all applicable daughter boards.
Table 1. Control Pins
Pin Description
ENABLE Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate drive outputs.
+5V +5V auxiliary power supply input for logic circuit and gate driver. On the daughter board there are two isolated 5V to 9V
DC/DC power supplies for top and bottom switches.
VDRV Not used. VDRV can be connected to VCC though R43. R43 is DNP by default.
PWMH_IN High-side PWM logic input for top switch Q1. It is compatible with 3.3V and 5V.
PWML_IN Low-side PWM logic input for bottom switch Q2. It is compatible with 3.3V and 5V.
0V Logic inputs and gate drive power supply ground return.
Figure 2. 650V Universal Mother Board GS665MB-EVB
12V INPUT
(+)
5V Power Supply
CIN
VSW
PWM control & dead
time circuit
Daughter Board
Probing point for VSW
For Ext.
12VDC Fan
Airflow direction
Optional Cout
VDC- VOUT
VDC-
VDC+

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 4 of 25
Dec.7.20
The universal 650V mother board evaluation kit includes the following items:
• Mother board GS665MB-EVB
•12V
DC Fan
1.2.1 12V Input
The mother board can be powered by 9V to 12V on J1. The on-board voltage regulator creates 5V for the
daughter board and control logic circuits. J3 is used for the external 12VDC fan.
1.2.2 PWM Control Circuit
The top and bottom switches (PWM inputs) can be individually controlled by two jumpers, J4 and J6. You can
choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted, controlled
by J7 input) with dead time or an external high-side/low-side drive signals from J5 (your own control board).
An on-board dead time generation circuit is included on the mother board. Dead time is controlled by two RC
delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally, two potentiometer
locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time, if needed.
Figure 3. PWM Control Input and Dead Time Circuit
Figure 4. On-Board Dead Time Generation Circuit
WARNING!
ALWAYS double check the jumper setting and PWM gate drive signals before applying power. Incorrect PWM inputs or
jumper settings may cause device failures
0V
D1 PMEG2005EB
SOD523
R6
1K00
TR12K C11
100pF
0V
R5
1K00
C10
1uF
C9
0.1uF
+5V
J7
112538 1
2 3 4 5
R4
100R
R1206
R2
100R
R1206
U2A
74VHC132
3
1
2
147
0V
R1
49R9
0V
D2 PMEG2005EB
SOD523
TR22K
C12
100pF
0V
U2B
74VHC132
4
5
6
U2C
74VHC132
9
10
8
U2D
74VHC132
12
13
11
TP7
TP8
DNP
DNP
PWM
OUTPUT
INVERTED
PWM OUTPUT
R3
49R9
DNP
DNP
R7
49R9

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 5 of 25
Dec.7.20
1.2.3 Test Points
Test points are designed in groups/pairs to facilitate probing.
1.2.4 Power Connections
The CON1-CON7 mounting pads are compatible with following mounting terminals:
• #10-32 Screw mount
• Banana Jack PCB mount (Keystone P/N: 575-4)
• PC Mount Screw Terminal (Keystone P/N: 8191)
1.2.5 Output Passives (L and C14)
An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5) or
VDC+ (CON2/3) for double pulse test. You can choose your inductor size to meet the test requirement. Renesas
recommends using a power inductor with low inter-winding capacitance to obtain best switching performance. For
the double pulse testing, use 2x 60µH/40A inductor (CWS, HF467-600M-40AV) in series. C14 accommodates a
film capacitor as an output filter.
1.2.6 Double Pulse Test Mode
The double pulse test allows evaluation of the device switching performance at high voltage/current without the
need of actually running at high power. It is also used for the switching loss (Eon/Eoff) measurement and other
switching characterization parameter tests.
Table 2. Test Points
Test points Name Description
TP1/TP2 +5V/0V 5V bias power
TP7/TP8 PWMIN/0V PWM input signal from J7
TP4/TP3/TP13 PWMH/PWML/0V High-side/low-side gate signals to daughter board
TP9/TP10 VDC+/VDC- DC bus voltage
TP11/TP12 VOUT/VDC- Output voltage
TP6/TP5 VSW/VDC- Switching node output voltage (for HV oscilloscope probe)
Figure 5. Double Pulse Test Setup
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
OUT
400V DC
+
VDC+
CON7CON6
VSW
CON5
+5V
0V
PWM
Input
(J7)
V
DS
I
L
I
SW
V
GL
+6V
0V
V
DS
V
GL
I
L
t0 t1 t2 t3
T
ON1

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 6 of 25
Dec.7.20
The circuit configuration and operating principle is shown in Figure 5.
• The output inductor is connected to the VDC+.
• At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first pulse TON1
defines the switching current ISW = (VDS * TON1) / L.
• t1-t2 is the free wheeling period when the inductor current ILforces Q1 to conduct in reverse.
• t1 (turn-off) and t2 (turn-on) are of interest for this test because they are the hard switching transients for the
half-bridge circuit when Q2 is under high switching stress.
• Keep the second pulse t2-t3 short to limit the peak inductor current at t3.
The double pulse signal can be generated using a programmable signal generator or microcontroller/DSP board.
Because this test involves high switching stress and high current, Renesas recommends setting the double pulse
test gate signal as a single trigger mode or use a long repetition period (for example >50ms-100ms) to avoid
excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or
INT_INV) and Q2 is set to INT (or EXT position if the PWM signal is from J5).
1.2.7 Buck/Standard Half-Bridge Mode
1.2.8 Boost Mode
WARNING!
Limit the maximum switching test current to 30A and ensure maximum drain voltage including ringing is below 650V for
pulse testing. Exceeding this limit may cause damage to the devices.
This is a standard half-bridge configuration that can be used in the following
circuits:
• Synchronous Buck DC/DC
• Single phase half-bridge inverter
• ZVS half-bridge LLC
• Phase leg for full bridge DC/DC or
• Phase leg for a 3-phase motor drive
Jumper setting:
• J4 (Q1): INT
• J6 (Q2): INT_INV
When the output becomes the input and the load is attached between VDC+ and
VDC-, the board is converted into a boost mode circuit and can be used for the
following:
• Synchronous Boost DC/DC
• Totem pole bridgeless PFC
Jumper setting:
• J4 (Q1): INT_INV
• J6 (Q2): INT
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
OUT
400V DC
+
VDC+
CON7
CON6
VSW
CON5
C
OUT
R
Load
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
IN
VDC+
CON7
CON6
VSW
CON5
INPUT
VIN

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 7 of 25
Dec.7.20
1.3 Using RTKA226110DE0010BU in System
The daughter board allows you to evaluate the GaN performance in your own systems. See the footprint drawing
of RTKA226110DE0010BU shown in Figure 6.
1.4 Quick Start Procedure – Pulses Test
The following equipment and components are required:
• Four-channel oscilloscope with 500MHz bandwidth or higher
• High bandwidth (500MHz or higher) passive probe
• High bandwidth (500MHz) high voltage probe (>600V)
• AC/DC current probe for inductor current measurement
• 12V DC power supply
• Signal generator capable of creating testing pulses
• High voltage power supply (0-400VDC) with current limit.
• External power inductor (recommend toroid inductor 50-200µH)
The following are the instructions to quickly get started with your evaluation of the GaN E-HEMT.
1. Check position E (Figure 10) on the RTKA226110DE0010BU daughter board.
2. Install RTKA226110DE0010BU on the mother board. Press all the way down until you feel a click. Connect the
probe between TP8 (low-side GaN gate) and TP3 (low-side GaN source) for gate voltage measurement in the
daughter board.
3. Set up the mother board
a. Connect 12VDC bias supply to J1.
b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator, ensure the output
mode is high-Z mode.
c. Set J4 to OFF position and J7 to INT.
d. Set the High Voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect the HV supply
to CON2 and CON6.
e. Use the HV probe between TP6 and TP5 for VDS measurement.
Figure 6. Recommended Footprint Drawing of Daughter Board
135
246
7
89
1. All units are in mm.
2. Pin 1-6: Dia. 1mm
3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312 -0-15-15-34-27-10-0.

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 8 of 25
Dec.7.20
f. Connect an external inductor between CON1 and CON3. Use the current probe to measure the inductor
current (IL).
4. Set up and check the PWM gate signal
a. Turn on the 12VDC power.
b. Check the two LEDs on the daughter board. They should be turned on indicating the isolated 9V is present.
c. Set up the signal generator as shown in Figure 5 to create the waveforms. Use equation
ISW =(V
DS *T ON1) / L to calculate the pulse width of the first pulse and ensure the ISW_MAX is ≤40A at
400VDC.
d. Set the operation mode to either Single Trigger or Burst mode with repetition periods of 100ms.
e. Turn on the PWM output and check on the oscilloscope to make sure the GaN gate drive voltage waveform
is present and matches the PWM input.
5. Power on
a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up until it reaches
400VDC. During the ramping period, closely observe the voltage and current waveforms on the oscilloscope.
6. Power off
a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the output. Then turn
off the 12V bias supply and signal generator output.
Figure 7. Pulses Test Setup Example
Inductor
PWM_in
12VDC VDC+/VDC-

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 9 of 25
Dec.7.20
1.5 Test Results
Pulses test (VDS = 400V, IMAX = 33A, Lp = 120µH, RG(ON) = 0Ω, IGSEL is connected to VDRV, Gate driver
current is 0.3A, RG(OFF) =1Ω, 8 pulses, period = 4µs, duty = 50%).
Figure 8 shows the hard switching on waveforms at 400V/33A. A VDS dip can be seen because of the rising drain
current (di/dt in the power loop ΔV = Lp * di/dt, where Lp is the total power loop inductance). After the drain current
reaches the inductor current, the VDS starts to fall. The VGS undershoot spike is caused by the Miller feedback
through Cgd under negative dv/dt.
Because of the low gate charge and small RG(OFF), the GaN E-HEMT gate has limited control on the turn-off
dv/dt. Instead, the VDS rise time is determined by how fast the turn-off current charges the switching node
capacitance (COSS).
The low COSS of the GaN E-HEMT and low parasitic inductance of the GaNPX™ package together with optimized
PCB layout, enables a fast and clean turn-off VDS waveform with 50V the turn-off VDS overshoot at dv/dt
>100V/ns. The measured rise time is 4ns at 400V and 33A hard turn-off.
The OCP setting point is 40A. Because of the ringing on the current sensing signal, the actual OCP trigger point is
33A. After the OCP occurs, the driver is locked with the Gate pulled low regardless the PWM input.
Figure 8. 400V/33A Pulses Test Waveform
PWM_low-side
I_inductor
Vds_low-side

RTKA226110DE0010BU 1. Functional Description
X0115710 Rev.1.00 Page 10 of 25
Dec.7.20
Synchronous Buck Test (L = 120µH, VIN = 400V, VOUT = 80V, D = 20%, fSW = 100kHz, POUT = 300W).
Figure 9. Buck Test Waveform (POUT = 300W)
PWM_low-side
I_inductor
Vds_low-side
V_out

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 11 of 25
Dec.7.20
2. PCB Layout Guidelines
2.1 RTKA226110DE0010BU Evaluation Board (Daughter Board)
• A. 2x GaN Systems 650V E-HEMT GS66508B, 30A/50mΩ
• B. Decoupling capacitors C14-C17 and C47-C54
• C. Signal isolator IL611-1E
• D. GaN driver RAA226110
• E. OCP shunt
• F. TP8 (gate) and TP3 (source) test points for bottom Q2 VGS
• G. 5V-9V isolated DC/DC gate drive power supply
Figure 10. RTKA226110DE0010BU Top Side
Figure 11. RTKA226110DE0010BU Bottom Side
B
A
E
F
CD
Heat Sink Location
G

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 12 of 25
Dec.7.20
2.1.1 GaN E-HEMTs
This daughter board includes two GaN Systems E-HEMT GS66508B (650V/30A, 50mΩ) in a GaNPx™ B type
package. The large S pad serves as source connection and thermal pad. Pin 4 is the Kelvin source connection for
gate drive return.
2.1.2 Gate Driver Circuit
The Renesas RAA226110 low-side gate driver is chosen for this design. This driver provides 5.8V gate drive with
3.8V UVLO. It supports the 5.8V turn-on and -3V/0V turn-off. It has separated source and sink drive outputs that
eliminates the need for an additional diode. OCP is also integrated in the driver.
RAA226110 provides configurable source current (0.3A/0.75A/2A) to adjust the slew rate of GS66508B without
gate resistor to minimize the gate loop. The turn off speed can be directly controlled by the gate resistor RG(OFF)
(R19/R20).
2.1.3 Gate Drive Power Supply
5V to 9V isolated DC/DC converters are used for gate drive. The RAA226110 accepts 4.5V to 18V VDD input
voltage. DC/DC converter 9V output is directly connected to RAA226110.
Figure 12. Package Outline of GS66508B
Figure 13. Gate Driver Circuit
Figure 14. Gate Drive Power Supply
Package Outline
Circuit Symbol
'
6
*66
GNDH
PART #: 3-141410UBLAN
USE: SIL-PAD WITH HS1
BERGQUIST ST-1500
GNDL
A
A
A
A
A
A
HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
+VO
0V
VIN
GND
NC
U5
PES1-S5-S9-M
1
2
4
5
8
C21
4.7UF
R43
DNP
R28
3.3K
C22
4.7UF
HEAT SINK
HS1
3-141411UBLAN
R29
3.3K
TP5
C20
4.7UF
D4
Default
TP4
D3
Default
R50
3.3K
TP7
C19
4.7UF
R31
3.3K
3
5
12
4
6
J1
TP6
R30
3.3K
4
2
3
5
6
1
J2
CONN-1X6
+VO
0V
VIN
GND
NC
U6
PES1-S5-S9-M
1
2
4
5
8
EN
PWMH_IN
PWML_IN
UNNAMED_4_SMLED_I134_B
UNNAMED_4_SMLED_I185_B
VCC
VDDHIN
VDDLIN
VSW

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 13 of 25
Dec.7.20
2.1.4 Current Shunt
• The board provides an optional current shunt position E (Figure 10) between the source of Q2 and power
ground return, allowing the drain current measurement for switching characterization test such as Eon/Eoff
measurement.
• The current shunt also provides the OCP signal for the RAA226110 to trigger OCP. The OCP threshold voltage
40mV/80mV/120mV can be configured through the IDSET pin of RAA226110.
• If current shunt is not used, position E must be shorted.
2.1.5 Measurement with Current Shunt
• When measuring VSW with current shunt, ensure all channel probe grounds and the current shunt BNC output
case are all referenced to the source end of Q2 before the current shunt. The recommended setup of probes is
shown in Figure 16.
• The output of coaxial current shunt can be connected to oscilloscope through a 50Ωtermination impedance to
reduce the ringing.
• The measured current is inverted and can be scaled by using: ID= VID / RSHUNT.
Figure 15. Current Shunt Position E
CAUTION:
Check the shunt position E before the first time use. To complete the circuit position E needs to be either shorted or a current shunt must be
inserted before powering up.
Figure 16. Recommended Probe Connection with Current Shunt
Q2 Source VDC-
Shunt
VGL
VSL
VSW
BNC case
To oscilloscope
probe input (use
50Ωtermination)
BNC tip
V
DS
V
GS
I
D

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 14 of 25
Dec.7.20
2.1.6 Thermal Design
• GS66508B has a thermal pad on the bottom side for heat dissipation. The heat is transferred to the bottom side
of the Printed Circuit Board (PCB) using thermal vias and copper plane.
• A heatsink (35x35mm size) can be attached to the bottom side of the board for optimum cooling. Thermal
Interface Material (TIM) is needed to provide electrical insulation and conformance to the PCB surface. The
daughter board is shipped with a sample 35x35mm fin heatsink (not installed), although other heatsinks can
also be used to fit your system design.
• A thermal tape type TIM (Berguist® Bond-Ply 100) is chosen for its easy assembly. The supplied heatsink has
the thermal tape pre-applied so simply peel off the protective film and attach the heatsink to the back of board
as marked in Figure 11.
• Two optional mounting holes as shown in Figure 17 are provided for mounting customized heatsink using
screws.
• Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is ~9°C/W with
500LFM airflow.
• Forced air cooling is recommended for power testing.
Figure 17. Daughter Board with Heatsink Attached
CAUTION:
There is no on-board over-temperature protection. Device temperature must be closely monitored during the test. Never operate the board
with device temperature exceeding TJ_MAX (150°C)

RTKA226110DE0010BU 2. PCB Layout Guidelines X0115710 Rev.1.00 Page 15 of 25 Dec.7.20
2.2 RTKA226110DE0010BU Circuit Schematic
Figure 18. Schematic
TITLE:
ENGINEER: DATE:
RELEASED BY:
DRAWN
BY:
DATE:
DATE:
RAA226110
RICHARD KOVACS TENY XU04/15/2020
VDC-
LOW SIDE SECTION
HIGH SIDE SECTION
LOW VOLTAGE SECTION
HIGH VOLTAGE SECTION
A
A
HV
HV
HV
HV
HV HV
HV
HV
HV
HV
HV
P
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
C8
0.1UF
.001
RSH1
RS1
.1
R10 DNP
C51
0.1UF
C52
0.1UF
R9
DNP
C53
0.1UF
R12
1M
C54
0.1UF
CON3
1M R11
CON2
CON1
EP
U4
RAA226110
1
FLT
2
EN
3
INB
4
IN
5
IGSEL
6
IDSET
7
ISNSN
8
ISNSP
9
VEEL
10
OUTL
11
OUTH
12
VDRV
13
VEEH
14
VSSP
15
VSS
16
VDD
17
C10
0.1UF
EP
RAA226110
U3
1
FLT
2
EN
3
INB
4
IN
5
IGSEL
6
IDSET
7
ISNSN
8
ISNSP
9
VEEL
10
OUTL
11
OUTH
12
VDRV
13
VEEH
14
VSSP
15
VSS
16
VDD
17
C9
0.1UF
R2
820
C12
4.7UF
C2
16PF
1
R20
R1
820
C1
16PF
C11
4.7UF
C4
16PF
R19
1
R4
820
TP1
C3
16PF
TP2
R3
820
TP3
GND
IN1+
IN1-
IN2+
IN2-
OUT2
OUT1
VDD
IL611-1E
U2
1
2
3
4 5
6
7
8
R21
3.3K
GND
IN1+
IN1-
IN2+
IN2-
OUT2
OUT1
VDD
U1
IL611-1E
1
2
3
4 5
6
7
8
D2
RB751V40
D1
RB751V40
3.3K
R22
TP8
1200PF
C16
D
S
G
SS
Q1
GS66508B
1
2
3
4
0.1UF
C6
D
S
G
SS
GS66508B
Q2
1
2
3
4
C5
0.1UF
C13
1200PF
5.7
R24
TP9
TP10
TP11
R5
10K
C47
0.1UF
R8 10K
0
R7
1UF
C14
DNP
R6
0
C48
0.1UF
R13
5.7
C7
0.1UF
C49
0.1UF
C15
DNP
1UF
C50
0.1UF
C17
1UF
DNP
EN
EN
PWMH_IN
PWML_IN
UNNAMED_5_GS66508B_I420_3
UNNAMED_5_GS66508B_I421_2
UNNAMED_5_GS66508B_I421_3
UNNAMED_5_IL611_I227_PIN2
UNNAMED_5_IL611_I227_PIN4
UNNAM ED_5_IL611_I227_PIN 6
UNNAM ED_5_IL611_I227_PIN 7
UNNAM ED_5_IL611_I227_PIN 8
UNNAMED_5_IL611_I228_PIN2
UNNAMED_5_IL611_I228_PIN4
UNNAM ED_5_IL611_I228_PIN 6
UNNAM ED_5_IL611_I228_PIN 7
UNNAM ED_5_IL611_I228_PIN 8
UNNAMED_5_RAA226110_I441_1
UNNAMED_5_RAA226110_I441_10
UNNAMED_5_RAA226110_I441_5
UNNAMED_5_RAA226110_I442_1
UNNAMED_5_RAA226110_I442_10
UNNAM ED_5_RAA226110_I442_5
UNNAMED_5_RAA226110_I442_7
UNNAMED_5_RAA226110_I442_8
VCC
VCC
VDC+
VDDHIN
VDDLIN
VDRVH
VDRVH
VDRVH
VDRVH
VDRVL
VDRVL
VDRVL
VDRVL
VSW

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 16 of 25
Dec.7.20
2.3 RTKA226110DE0010BU Bill of Materials
Qty Reference Designator Description Manufacturer Manufacturer Part
1 PWB-PCB,RTKA226110DE0010BU,
REVC, ROHS
Imagineering Inc RTKA226110DE0010BURVCPCB
6 C11, C12, C19-C22 CAP-AEC-Q200, SMD, 0805, 4.7µF, 25V,
10%, X7R, ROHS
TDK CGA4J1X7R1E475K125AC
2 C7, C8 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R,
ROHS
Yageo CC0603KRX7R8BB104
4 C5, C6, C9, C10 CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R,
ROHS
AVX 06035C104KAT2A
2 C13, C16 CAP, SMD, 0603, 1200pF, 50V, 10%, X7R,
ROHS
Panasonic ECJ-1VB1H122K
4 C1, C2, C3, C4 CAP, SMD, 0603, 16pF, 50V, 5%,
C0G/NP0, ROHS
Yageo CC0603JRNPO9BN160
3 CON1, CON2, CON3 CONN-PC PIN, TH, 1.02mmDIA.,
9.04mmLENGTH, GOLD, ROHS
Mill-max 3620-2-32-15-00-00-08-0
1 J2 CONN-HEADER,1x6, BRKAWY 1x36,
2.54mm, ROHS
BERG/FCI 68000-236HLF
1 J1 CONN-HEADER, 2x3, BRKAWY, 2.54mm,
TIN, R/A, ROHS
Samtec TSW-103-08-T-D-RA
2 D1, D2 DIODE-SCHOTTKY, SMD, SOD-323, 40V,
120mA, ROHS
Nexperia USA,
INC
RB751V40,115
2 D3, D4 LED, SMD, 0603, GREEN CLEAR, 2V,
20mA, 574nm, 35mcd, ROHS
LITEON/VISHAY LTST-C191KGKT
2 U1, U2 IC-DIGITAL ISOLATOR, SMD, 8P, MSOP,
2-CHANNEL, 2500Vrms, ROHS
NVE
Corporation
IL611-1E
2 U3, U4 IC Low-Side Gan Driver, 16P, QFN, 4x4,
ROHS
Renesas
Electronics
RAA2261104GNP#MA0
2 Q1, Q2 TRANSISTOR-MOS, N-CHANNEL, SMD,
8.8x7mm, 650V, 30A, 50mΩ, ROHS
GaN Systems GS66508B-E01-MR
0 R9, R10, R43 RESISTOR, SMD, 0603, 0.1%, MF,
DNP-PLACE HOLDER
2 R19, R20 RES, SMD, 0603, 1Ω, 1/10W, 1%, TF,
ROHS
Panasonic ERJ-3RQF1R0V
2 R6, R7 RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS Venkel CR0603-10W-000T
2 R5, R8 RES, SMD, 0603, 10k, 1/10W, 1%, TF,
ROHS
Venkel CR0603-10W-1002FT
2 R11, R12 RES, SMD, 0603, 1M, 1/10W, 1%, TF,
ROHS
Panasonic ERJ-3EKF1004V
2 R13, R24 RES, SMD, 0603, 5.76Ω, 1/10W, 1%, TF,
ROHS
Yageo RC0603FR-075R76L
4 R1, R2, R3, R4 RES, SMD, 0603, 820Ω, 1/10W, 1%, TF,
ROHS
Venkel CR0603-10W-8200FT
7 R21, R22, R28, R29, R30, R31,
R50
RES-AEC-Q200, SMD, 0603, 3.3k, 1/10W,
1%, TF, ROHS
Rohm KTR03EZPF3301
1 RSH1A RES-AEC-Q200, SMD, 2512-WIDE,
0.001Ω, 2W, 5%, ROHS
Rohm PML100HZPJV1L0
1 HS1 (See Assy Instructions) HEATSINK-BGA, 35x35x24.50mm, Straight
Fin w/Thermal Tape
Advanced
Thermal
Solutions Inc
ATS-54350W-C1-R0

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 17 of 25
Dec.7.20
2.4 RTKA226110DE0010BU Board Layout
1 HS1-Cut thermal sheet into 1.378
inch squares and place between
heat sink and PCB.
Instructions for assembly. Renesas
Electronics
America
Assembly Instructions
1 HS1 (SEE ASSY
INSTRUCTIONS)
INSULATION-BOND-PLY, 11mil, 10x10in,
2-SIDE ADHESIVE, ROHS
Bergquist BP100-0.011-00-1010-NA
8 C47, C48, C49, C50, C51, C52,
C53, C54
CAP, SMD, 1812, 0.1µF, 1kV, 10%, X7R,
ROHS
Kemet C1812C104KDRAC7800
0 C14, C15 ,C17
(2220Y6300105KXTWS2)
DO NOT POPULATE OR PURCHASE
0 RS1 DO NOT POPULATE OR PURCHASE
0 TP1-TP11 DO NOT POPULATE OR PURCHASE
2 U5, U6 PWR-SUPPLY, DC/DC CONVERT, SMD,
12.7x8.3, 1W, 5V, 111mA, ROHS
CUI, INC PES1-S5-S9-M-TR
Figure 19. Silkscreen Top
Figure 20. Assembly Top
Qty Reference Designator Description Manufacturer Manufacturer Part

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 18 of 25
Dec.7.20
Figure 21. Solder Top
Figure 22. Top Layer
Figure 23. Layer 2

RTKA226110DE0010BU 2. PCB Layout Guidelines
X0115710 Rev.1.00 Page 19 of 25
Dec.7.20
Figure 24. Layer 3
Figure 25. Bottom Layer
Figure 26. Solder Bottom

RTKA226110DE0010BU 3. Appendix A - GS665MB-EVB X0115710 Rev.1.00 Page 20 of 25 Dec.7.20
3. Appendix A - GS665MB-EVB
To ensure that you have the latest GS665MB-EVB information, visit the GaN systems Inc website.
3.1 GS665MB-EVB Circuit Schematics
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