Renesas HIP2105-6MBEVAL1Z User manual

Rev.1.00 Jul 2018
User’s Manual
HIP2105-6MBEVAL1Z
User’s Manual: Evaluation Board
Industrial Analog and Power

UG167 Rev.1.00 Page 2 of 30
Jul 31, 2018
UG167
Rev.1.00
Jul 31, 2018
HIP2105-6MBEVAL1Z
Evaluation Board
USER’S MANUAL
1. Overview
The HIP2105-6MBEVAL1Z is an evaluation tool for the HIP2105 and HIP2106A half bridge MOSFET drivers. This
tool consists of a mother board and HIP2105DBEVAL1Z or HIP2106ADBEVAL1Z evaluation daughter cards. The
mother board platform provides an on-board microcontroller that is used to generate appropriate control inputs to the
HIP2105 or HIP2106A. The frequency, the PWM duty cycle, and the dead time provided by the microcontroller are
user adjustable.
For customers who want to provide their own external signals, the on-board controller can be configured to allow the
daughter cards to be controlled by externally provided inputs.
The daughter cards can also be used as stand-alone units mounted on a customer designed main board that incorporates
customer selected bridge FETs and any other external circuits desired. The daughter cards have optional circuits so that
the HIP2105 or HIP2106A can be configured as required by the customer’s application.
1.1 Key Features
• Adaptive shoot-through protection, HIP2106A only
• HI/PWM and LI inputs, HIP2105 only
• 0.4Ω ON-resistance and 4A sink current capability
• Low tri-state hold-off time (20ns), HIP2106A only after 20ns
• Supports 3.3V and 5V HI/LI or PWM input
• Power-On Reset (POR)
1.2 Specifications
• Bridge Bias Voltage (VBAT): 5V minimum, 25V maximum operating including transients
• External bias for microcontroller: 3.3V - 5.0V, ~30mA
• Maximum bridge current: 12A
• PWM switching frequency: 25kHz to 625kHz
• PWM duty cycle: Adjustable from 0% to ~ 98%
• Dead time: 0.0µs to 0.7µs in 100ns increments
• Large terminal blocks: 15A each connection
• Small terminal blocks: 6A each connection
1.3 Ordering Information
1.4 Related Literature
For a full list of related documents, visit our website
•HIP2105, HIP2106A product pages
Part Number Description
HIP2105-6MBEVAL1Z HIP2105 and HIP2106A mother board
HIP2105DBEVAL1Z HIP2105 evaluation board
HIP2106ADBEVAL1Z HIP2106A evaluation board

UG167 Rev.1.00 Page 3 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 1. Overview
Figure 1. HIP2105-6MBEVAL1Z Block Diagram
Microcontroller External Inputs
Buffer
LI, HI/PWM
Multiplexer
Option
Switches
HIP2105
or
HIP2106A
Daughter Card
Half Bridge FETs
External
Bias
Optional
DC Motor or
other Loads
Optional External
LI, HI/PWM Inputs
Jumper
Option
Push
Buttons LEDs

UG167 Rev.1.00 Page 4 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
2. Functional Description
The HIP2105-6MBEVAL1Z is a fully self-contained test platform for evaluation of the HIP2105 or the HIP2106A,
which are provided on daughter cards.
The HIP2105-6MBEVAL1Z mother board and associated daughter cards are the same test boards used by the Renesas
application engineers and IC designers to evaluate the performance of the HIP2105 and HIP2106A MOSFET drivers.
2.1 Scope
This user manual describes the use of the HIP2105-6MBEVAL1Z mother board and the HIP2105DBEVAL1Z and
HIP2106ADBEVAL1Z daughter cards. A detailed description is provided for setting up and using the
microcontroller. Assembly options on the motherboard are discussed, and sample waveforms are provided.
The microcontroller firmware is provided on request, but the only support offered by Renesas is for bug issues.
Refer to Microchip for details on the use of the PIC18F2431.
2.2 Bias Supplies
The HIP2105-6MBEVAL1Z mother board requires a current limited lab supply (0V to 25V) for the VBAT and
GND inputs on TB1. The current capacity is dependent on the users desired load if any.
An external 5V bias supply (~25mA) is required for the microcontroller and associated circuits. This 5V bias
supply for the microcontroller is supplied by an external source connected to TB8. The 5V bias for the HIP2105
and HIP2106A daughter cards must be supplied by an external source connected to VCC and GND of TB6.
2.3 Microcontroller and Associated Circuits
The PWM frequency and the dead time options of the microcontroller are configured by the SW5 DIP switch.
Refer to the chart on the mother board schematic (Figure 12 on page 16) for the DIP switch settings, or to Table 1
on page 10. The DIP switch settings are read only once after the Start/Stop button is pressed to start the PWM. Any
changes to the frequency or dead time settings are not recognized until the PWM is stopped then restarted.
Turning the potentiometer, R1, fully Counter Clockwise (CCW) reduces the duty cycle of the output of the bridge
to a minimum. Turning fully clockwise results with a maximum duty cycle. The duty cycle is proportional to the
tap voltage of the potentiometer independent of the PWM frequency. The dead time subtracts from the duty cycle
period on the leading edge of the HI/PWM and LI inputs to the daughter cards altering the actual duty cycle.
To emulate controllers that may be used by customers that do not have the ability to generate dead time, the dead
time of the microcontroller can be set to zero. On the daughter cards, an optional RCD circuit is provided for the LI
and HI/PWM inputs of the HIP2105 and HIP2106A to generate dead time.
Be cautious if the zero dead time option is selected when the HIP2105 and HIP2106A daughter cards are not
configured for delays with the RCD circuit, as this results in shoot-through currents in the bridge.
Four LEDs are used to indicate the operating status of the microcontroller. Refer to “Setup and Operating
Instructions” on page 9 for complete details.

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HIP2105-6MBEVAL1Z 2. Functional Description
2.4 Half Bridge
The bridge is composed of two (NVTFS5C466NLWF) 51A, 40V MOSFETs. Each FET has an optional gate-to-
source and drain-to-gate capacitors to allow the emulation of FETs with larger capacitances if desired. An optional
series gate resistor is also provided for each bridge FET that can also be used the emulate the internal gate
resistance. The current rating of these NVTFS5C466NLWF MOSFETs was chosen primarily to eliminate the need
of a heat sink when operating with heavy current loads. The maximum output load current is constrained by the
current rating of the VBAT (TB1) and the VOUT (TB7) terminal blocks. If a load current higher than 15A is
desired, it is recommended that the battery and load wires are soldered directly to the solder pads of the TB1 and TB2
terminal blocks on the bottom of the PCB.
The bridge bias source is connected to the VBAT terminal block (TB1). The voltage source can be either a current
limited power supply (recommended for initial setup) or a battery (a fuse is highly recommended).
An external load can be connected to the VOUT (TB7) terminal block. The load can be of any configuration (for
example a DC motor or an LCR load) as desired by the user within the constraints of the bridge FETs and the
terminal blocks.
Even though the FETs have a voltage rating of 40V, the maximum operating voltage is limited to 25V by the rating
of the Phase and VBAT pins on the HIP2105, HIP2106A drivers.
2.5 Daughter Cards
Two different daughter cards are provided for evaluation. These cards are mounted on the back side of the mother
board to facilitate temperature testing using a temperature forcing system.
The HIP2105DBEVAL1Z and HIP2106ADBEVAL1Z daughter cards are identical except for the differences
between the HIP2105 and the HIP2106A.
When using the HIP2105 daughter card, VCC must come from external sources. As mentioned previously, the J2
strap option is used to select the bias source for the microcontroller. If the 5V strap option is selected, the bias to the
microcontroller is always be present. This is desirable during the initial setup of the evaluation board or when
testing the HIP2105 for varying the VCC to the driver.
2.6 Switches and Push Buttons
Three push buttons provide control signals to the microcontroller. The reset button restarts the firmware. The
Start/Stop button starts and stops the PWM signals to the LI and HI inputs of the HIP2105, and PWM input to the
HIP2106A.

UG167 Rev.1.00 Page 6 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
2.7 User Assembly Options
The following optional assembly features are provided on the evaluation mother board:
• Series connected diode (D1) on the VBAT input to the HIP2106A daughter card for holding up VBAT when there is
severe ripple voltage from a Li-ion battery. A 0Ω resistor (R23) shorts out this diode when not required (installed).
• Gate-to-source resistors on the bridge FETs. (R19 and R21 are omitted)
• Series connected gate resistors on each bridge FET (R34 and R35 are installed with 0Ω)
• Gate-to-source, and gate-to-drain capacitors on the bridge FETs (C11, C12, C9, and C10 omitted). The capacitors
can be added to emulate larger FETs.
Figure 2. Diode to Suppress Li-Ion Battery Ripple
Figure 3. Optional Resistors and Capacitors for Bridge FETs
DAU
VDEN SWICH
VCEN SWITCH
4
SW4
1
2
3
VCC
D3
1 3
VCEN
U3D
32
1
4
U3A
1112
13
D2
1 3
VDEN
U3E
714
SK2-7
3
D1
S1B
12
R30
100
SW3
1
2
3
SK2-8
2
0
R23
R33
100
GND1
SK2-9
1
C16
270UF
12 LI-IN 12 HI/PWM-IN
0.01UF
50V
C7
VDD
2.2UF
C8
UNNAMED_4_HC125_I173_Y
UNNAMED_4_HC125_I175_Y
UNNAMED_4_HEADERS_I 45_IN1
UNNAMED_4_HEADERS_I 46_IN1
UNNAMED_4_SMRES_I155_B
UNNAMED_4_SMRES_I156_B
OUT
10UF
C13
OPEN
C9
OPEN
C12
C14
10UF
100K
R21
OPEN
C11
1
R19
100K
VBAT
TB7-2
2
0
R35
0.1UF
C15
NVTFS5C466NL
Q1
1
2
3
4 5
6
7
8
0
R34
NVTFS5C466NL
Q2
1
2
3
4 5
6
7
8
OPEN
C10
GND
UNNAMED_4_N CHANNEL_I 178_G1X
UNNAMED_4_N CHANNEL_I 179_G1X
VOUT

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Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
The following user optional assembly features are provided on the HIP2105, HIP2106A daughter cards.
• The HO = HGATE and LO = LGATE outputs have options for a bypass diode across a series connected gate
resistor for slower turn-on and faster turn-off of the driven bridge FET. The default configuration includes the
bypass diode in parallel with a 0Ω resistor.
• The LI and HI/PWM inputs have optional RCD circuits for the purpose of generating dead time if a controller is used
that does not have built-in dead time capability. As previously mentioned, the on-board microcontroller can be
configured for no dead time delays. The default configuration includes Schottky diodes in parallel with a 0Ω resistor.
Figure 4. Bypass Diodes (D3, D4) for Slow Turn-On and Fast Turn-Off
Figure 5. Bypass Diodes (D1, D2) Used for Dead Time Generation
A
J1-3
7
R5
24.9
J1-4
6
24.9
R6
J1-5
5
D4
1 2
J1-6
4
J1-7
3
F
TP9
J1-8
2
R7
0
J1-9
1
OPEN
C7
J1-1
9
J1-2
8
D3
1 2
AGND
BOOT
LGATE-OUT
PHASE-OUT
UGATE-OUT
A
A
J2-9
1
16V
C3
4.7UF
J2-1
9
TP4
OPEN
C2
J2-2
8
R1
0
TP1
J2-3
7
D1
1 2
TP3
J2-4
6
TP2
J2-5
5
OPEN
C1
J2-6
4
0
R2
HI
EP
UGATE
GND
BOOT
NC
HIP
1
2
3
4
5
11
J2-7
3
D2
1 2
J2-8
2
AGND
HI
HI-IN
LI-IN

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Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
• The PHASE pin has an RC filter (R7/C7 on the HIP2105 daughter card and R7/C9 on the HIP2106A daughter
card) This filter is used if needed. The default value for R7 is 0Ω and the capacitor between Phase and VSS is
omitted.
2.8 Switching Transients
The recommended maximum operating voltage on the PHASE and VBAT pins is 25V. This includes the switching
transients resulting from parasitic inductance in the bridge circuit.
A similar transient situation may occur with the Phase pin. In this situation, a ringing spike can be more severe
because of high speed switching from the bridge FETs, the large amplitude of switching currents, and because of
parasitic inductance associated with the bridge high current PCB traces. Because the amplitude of the ringing spike
also increases with the switching load current amplitude, evaluation should be across the full operating load range
including fault currents. Good bridge circuit PCB design minimizes but cannot totally eliminate ringing on the
Phase node.
These switching transients are relatively fast. When evaluating the spikes on these pins, it is necessary to use a time
base on the scope of about 100ns/division. Slower sweep speeds may mask the switching spike depending on the
sample rate of the digital scope.
Other methods can also be used to reduce ringing on the Phase node. Sufficiently large value gate resistors on the
bridge FETs reduce the switching speed and consequently the amplitude of the ringing. The above mentioned RC
filter on the Phase pin can also be used to attenuate the spike directly on the Phase pin. By default, the gate resistors
on the HIP2105/6A daughter cards, R5 and R6, is 0Ω. With this evaluation PCB layout, 0Ω is sufficient to prevent
excessive switching transient, but a user’s PCB layout may require more or less gate resistance or another method
to attenuate the switching transients.
Another source of switching transients that must be dealt with is from the bridge voltage source, especially with
Li-ion batteries. When the Li-ion battery load current is interrupted when the bridge turns off, the voltage from the
battery can rise dramatically because of the internal inductance of the battery. The usual solution is to have
sufficiently large capacitance across the bridge. This bridge bypass capacitor is effectively an LC filter working
Figure 6. RC Filter on PHASE Pin (not required)
A
J1-3
7
C4
OPEN
R5
24.9
J1-4
6
TP6
24.9
R6
J1-5
5
OPEN
C6
D4
1 2
J1-6
4
OPEN
R3
J1-7
3
0.1UF
C5
TP9
J1-8
2
TP7
R7
0
J1-9
1
OPEN
C7
J1-1
9
NC
LI
LGATE
VCC
PHASE
5IRZ
6
7
8
9
10
TP8
J1-2
8
TP5
D3
1 2
LGATE
LI

UG167 Rev.1.00 Page 9 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
with the internal inductance of the Li-ion battery (typically a few hundred nH). If the capacitor value is large
enough, the battery voltage is close to the nominal unloaded value with minimal ripple. Another approach to reduce
the amplitude of the voltage transient from the battery without increasing the size or value of the bridge capacitor,
is to increase the PWM switching frequency.
If it is not desirable to use relatively large value capacitors across the bridge, a clamping method must be used to
limit the peak voltage ripple from the battery. In any case, a relatively small capacitor across the bridge should be
used to limit the rate of change of the ripple voltage and to minimize the effects of the PCB parasitic trace
inductance on the Phase pin.
Another consequence of allowing a relatively large ripple voltage on the battery, is that under heavy load
conditions, the voltage ripple valley drops to very low levels. Because most motor loads respond to the average
voltage applied, this ripple voltage is of minimal concern. If the valley voltage drops too low, the UVLO of the
HIP2105/4 is 3.0V typical. If the bridge FETs are selected appropriately, this low-gate drive voltage has no
significant effect except for the usual consequence of higher rDS(ON) of the bridge FETs.
2.9 Setup and Operating Instructions
The following procedures ensure a correct setup of the evaluation board and illustrate various operating methods.
2.9.1 Required Lab Equipment
• Power supply (or battery), 13V minimum to 25V maximum operating for the bridge bias. The current rating of
the power supply must have sufficient capacity for the external load used for testing (if any). If no load is
applied, 200mA is sufficient. If a battery is the power source, it is highly recommended that an appropriate
fuse be used. With a Li-ion battery, it is necessary to add sufficient capacitance (100µF or greater) across the
VBAT terminal block to prevent excessive ringing.
• Bias supply, 5V at ~50mA, required for testing the HIP2105 or HIP2106A
• Bench fan (only necessary when testing with large loads at elevated ambient temperatures)
• Four channel oscilloscope, ~500MHz recommended
• Current probe (optional) when testing with external loads
• Multimeter
2.9.2 Initial Configuration for the Microcontroller
The following procedure illustrates how to configure the microcontroller without applying power to the bridge.
(1) Connect a 5.0V bias supply to the +5V_GND terminal block (TB8). This voltage powers the
microcontroller.
(2) Ensure that the jumper strap on J2 is on the 5V option. This connects the microcontroller to the external lab
supply.
(3) Set up the DIP switch on the mother board with the desired PWM frequency and dead time. For the initial
setup, start with 200kHz and 100ns dead time (in bold type).

UG167 Rev.1.00 Page 10 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
(4) Connect scope probes on the HI/PWM and LI test points on the mother board. Set the time base to
50ns/Div, the vertical gain to 2V/Div, the trigger on the LI input at the 2.5V level with a negative edge
trigger, and the trigger position at the 100ns division (on the left side of the screen) and use the auto trigger
mode.
(5) Turn the duty cycle potentiometer, R1, fully counter clockwise until it clicks.
(6) Turn on the lab supply. Observe that the four LEDs turn on and off, one after another. This flashing
sequence indicates that power has been applied. After the initial flash, all LEDs are off.
(7) Observe that the LI and HI/PWM inputs are low.
(8) Press the Start/Stop push button once. The Run LED (LED0) blinks indicating that PWM signals from the
controller have been enabled.
The DIP switch options are read only when the Start/Stop button is pressed to start the PWM signals. Changing
the settings while the Run LED is flashing has no effect. To update the DIP switch setting, change the setting,
stop the PWM signals, then start again.
Table 1. DIP Switch Options
Switch Position 6 5 4 3 2 1
PWM Frequency x x x 0 0 0 25kHz
xxx001 50kHz
x x x 0 1 0 100kHz
xxx011 200kHz
x x x 1 0 0 300kHz
x x x 1 0 1 400kHz
x x x 1 1 0 500kHz
x x x 1 1 1 625kHz
External inputs 1 1 1 1 1 1
Dead Time 0 0 0 x x x 0.0µs
001xxx 0.1µs
0 1 0 x x x 0.2µs
0 1 1 x x x 0.3µs
1 0 0 x x x 0.4µs
1 0 1 x x x 0.5µs
1 1 0 x x x 0.6µs
1 1 1 x x x 0.7µs
LED0LED2LED3 LED1
At initial turn on, LEDs will turn on and
off one at a time starting with LED0
LED0LED2LED3 LED1
With PWM signals present on LI and HI,
the Run LED is blinking
RunExternal Sleep

UG167 Rev.1.00 Page 11 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
(9) Slowly rotate the potentiometer, R1, to the right (CW) until the waveforms shown in Figure 7 appear.
(10) Confirm that a the preset dead time is present.
(11) Rotate the potentiometer CCW to zero the PWM period.
(12) Press the Start/Stop push button to disable the PWM outputs. The blinking LED0 turns off.
(13) Press the Sleep button. LED1 turns on to indicate that Sleep mode is active.
(14) Press the Start/Stop button. LED0 flashes indicating that the PWM outputs are active. Simultaneously,
LED1 turns off indicating that Sleep mode is no longer active.
(15) Press the Sleep button. LED0 turns off and LED1 turns on indicating that Sleep mode is active.
2.9.3 Initial Setup to Evaluate the HIP2105 Daughter Card
The following procedure illustrates how to setup the HIP2105 daughter card and apply power to the bridge.
(1) Install a HIP2105 daughter card on the mother board. Be careful with the polarity.
Incorrect installation may damage the daughter card and the mother board.
(2) Connect an additional scope probe to the Phase test point on the mother board. Set the vertical gain to
10V/Div and the time base to 10µs/Div.
(3) Connect 5V supply to VCC and set the output to OFF
(4) Connect the bridge power supply to the VBAT_GND terminal block (TB1).
(5) Starting with an initial output of 20V and a current limit of 200mA, turn on the bridge supply.
Caution: If a Li-ion battery is used instead of a regulated supply, it is recommended to add a 100µF or
larger capacitor across the VBAT input terminal. This is necessary because the relatively large inductance
of an Li-ion battery can resonate with the bridge bypass capacitor resulting with excessive voltage.
(6) Turn on VCC = 5V.
(7) Measure 12V ±5% on the VDD pin of TB6 relative to the GND pin.
(8) Press the Reset button. The four LEDs flash one after another, and then turn off.
(9) Press the Start/Stop button. LED0 is flashing and HI/PWM and LI signals are active.
Figure 7. HI/PWM and LI Signals
HI/PWM
LI

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Jul 31, 2018
HIP2105-6MBEVAL1Z 2. Functional Description
(10) Turn the potentiometer CW until the waveform shown in Figure 8 appears.
(11) Confirm that the PWM frequency is 200kHz on the HI/PWM and LI pins.
(12) Turn on the bridge supply (still at 20V).
(13) Press the Start/Stop button. The LI and HI/PWM inputs start switching. The Phase output is also switching.
(14) Turn off VCC. Phase stops switching.
2.10 Initial Setup to Evaluate the HIP2106A Daughter Card
The method to evaluate the HIP2106A is similar to the HIP2105 except only the PWM signal is provided as an
input to the HIP2106A. TB6 input terminal for VCC bias for the HIP2105 and HIP2106A. VCC on TB6 can also be
used as a bias input for the microcontroller (or alternatively TB8).
2.11 DIP Switch Configuration for Testing with External Signals
It may be desirable to provide control signals from an off-board controller or logic generator.
(1) Configure the DIP switch for external signals (all switches on), see Table 1 on page 10.
(2) Press the START/STOP button. Observe that LED3 (External) is on.
(3) The U3 buffer on the mother board is now in the tri-state mode. All inputs, VCEN, VDEN, HI/PWM, LI must
now come from an external controller. Terminal blocks GND_VDEN_VCEN (TB5), and HI_LI (TB4) are
used for these inputs.
Figure 8. HI/PWM, LI, and Phase Signals
HI/PWM
LI
PHASE
LED0LED3 LED2 LED1
LED3 is on when configured for external inputs
RunExternal Sleep

UG167 Rev.1.00 Page 13 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
3. PCB Layout Guidelines
The HIP2105-6MBEVAL1Z board is 84mmx94mm. The tallest component is the RJ25 connector. The total height is
38mm. Multiple inputs have miniature terminal blocks and the high current battery inputs and load outputs have larger
terminal blocks rated for 15A each connection. Three push-buttons are used for Reset, Start/Stop, and Sleep functions.
An on-board potentiometer adjusts the duty cycle.
The six position DIP switch sets up the PWM switching frequency (Positions 1, 2, and 3) and the dead time (Positions
4, 5, and 6). One specific combination of DIP switch settings (all positions set to on) disables the signals from the
microcontroller and enables all of the external inputs.
For users who want to modify the firmware of the PIC18F2431 microcontroller, an RJ25 connector is provided for
easy connection with Microchip firmware development tools (not provided or supported by Renesas).
3.1 HIP2105-6MBEVAL1Z Evaluation Board
Figure 9. HIP2105-6MBEVAL1Z Top View
Freq
Dead Time
Duty Cycle
Not UsedBias µC
VDD, VCC
External Inputs
Load
Bridge Bias
µC Bias
I/O
Option
HIP2105-6MBEVAL1Z

UG167 Rev.1.00 Page 14 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
Figure 10. HIP2105-6MBEVAL1Z Bottom View
Observe the
Installation
Polarity

UG167 Rev.1.00 Page 15 of 30 Jul 31, 2018 HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
3.2 Schematics
Figure 11. HIP2105-6MBEVAL1Z Bridge and Daughter Card Socket Schematic
ENGINEER: DATE:DRAW N BY: DATE:
TIM KLEMANN THEJU BERNARD
04/25/2018
SOCKET
DAUGHTER CARD
VDEN SWICH
VCEN SWITCH
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
3
SK2-4
6
U3C
65
4
12
G-LO
SW4
1
2
3
10UF
C13
TB1-2
2
VCC
SK1-3
7
R22
1K
OPEN
C9
1
SK2-5
5
1K
R18
12
PHASE
D3
1 3
1
VCEN
SK1-4
6
U3D
32
1
OPEN
C12
TB4-2
2
SK2-6
4
U3A
1112
13
12
G-HO
D2
1 3
C14
10UF
VDEN
U3E
714
SK1-5
5
R24
1K
100K
R21
SK2-7
3
D1
S1B
12
12
HB
R30
100
TB6-3
1
SK1-6
4
SW3
1
2
3
OPEN
C11
SK2-8
2
0
R23
R33
100
1
2
GND1
SK1-7
3
R29
10K
R19
100K
SK2-9
1
VBAT
TB7-2
2
3
SK2-1
9
C16
270UF
SK1-8
2
R28
10K
1K
R20
0
R35
12 LI-IN
0.1UF
C15
TB5-3
1
SK2-2
8
U3B
89
10
SK1-9
1
R27
10K
NVTFS5C466NL
Q1
1
2
3
4 5
6
7
8
SK1-1
9
0
R34
12 HI/PWM-IN
2
SK2-3
7
0.01UF
50V
C7
GND2
R25
10K
NVTFS5C466NL
Q2
1
2
3
4 5
6
7
8
VDD
SK1-2
8
2.2UF
C8
OPEN
C10
EN_LI_HI
EN_VD_VC
GND
GND
GND
GND
HI/PWM-C
HI/PWM-IN
HI/PWM-X
LI-C
LI-X
UNNAMED_4_HC125_I 173_Y
UNNAMED_4_HC125_I 174_Y
UNNAMED_4_HC125_I 175_Y
UNNAMED_4_HEADERS_I18_IN1
UNNAMED_4_HEADERS_I19_IN1
UNNAMED_4_HEADERS_I20_IN1
UNNAMED_4_HEADERS_I38_IN1
UNNAMED_4_HEADERS_I45_IN1
UNNAMED_4_HEADERS_I46_IN1
UNNAMED_4_NCHANNEL_I178_G1X
UNNAMED_4_NCHANNEL_I179_G1X
UNNAMED_4_SMRES_I155_B
UNNAMED_4_SMRES_I156_B
VBAT
VCC
VCEN-C
VCEN-X
VDD
VDEN-C
VDEN_X
VOUT
V_5V

UG167 Rev.1.00 Page 16 of 30 Jul 31, 2018 HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
Figure 12. HIP2105-6MBEVAL1Z Controller
RELEASED BY:
DRAW N BY:
UPDATED BY:
TESTER
DATE:
DATE:
DATE:
4/25/201
TIM KLEMANN
CONTROLLER
PROGRAMING
PORT
(CORRECTED)
(3.3V OR 5V)
VCC OUTPUT FROM HIP210X
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
CSTCE10M5G55
U1
10MHZ
4
LED2
1 2
C2
50V
0.01UF
S4
1 2
3
TB8-2
2
START/STOP
1 23
4
5
10K
R17
R1
10K
1
2
3
C3
4.7UF
R2
10K
S1
1 2
3
J1-1
555165-1
6
LED3
1 2
R6
1K
U2
PIC18F2431S0
1MCLR
2RA0
3RA1
4RA2
5RA3
6RA4
7AVDD
8AVSS
9OSC1
10 OSC2
11 RC0
12 RC1
13 RC2
14 RC3 15
RC4
16
RC5
17
RC6
18
RC7
19
VSS
20
VDD
21
RB0
22
RB1
23
RB2
24
RB3
25
RB4
26
RB5
27
RB6
28
RB7
C5
4.7UF
TB9-2
2
1K
R10
R7
470
10K
R11
J2
1
2
3
R3
10K
R8 10K
1
1K
R12
LED0
1 2
OPEN
R4
S2
1 2
3
2
1K
R14
C4
4.7UF
1
10K
R13
R9
2K
TB10-3
1
1K
R16
SLEEP
1 23
4
2
LED1
1 2
0.047UF
C1
S3
1 2
3
RESET
1 23
4
3
10K
R15
10K
R5
8 7
10 11
3 4 5 6
9
112 2
SW5
1 2 3 4 5 6 7
8 9 10 11 12
1
C6
4.7UF
+5V
A
B
C
EN_LI_HI
EN_VD_VC
GND
GND
GND
HI/PWM-C
LI-C
MCLR
MCLR
RB6
RB6
RB7
RB7
UNNAMED_2_B3S_I 32_1
UNNAMED_2_B3S_I32_3
UNNAMED_2_B3S_I 46_1
UNNAMED_2_B3S_I94_1
UNNAMED_2_B3S_I 94_3
UNNAMED_2_BAW56_I73_A UNNAMED_2_BAW56_I74_A
UNNAMED_2_BAW56_I74_C1UNNAMED_2_BAW56_I74_C2UNNAMED_2_BAW56_I75_C1UNNAMED_2_BAW56_I75_C 2 UNNAMED_2_BAW56_I76_C1UNNAMED_2_BAW56_I76_C2
UNNAMED_2_CST CE10M_I34_P1
UNNAMED_2_CST CE10M_I34_P3 UNNAMED_2_PIC18F2431_I 95_14 UNNAMED_2_PI C18F2431_I95_15
UNNAMED_2_PI C18F2431_I95_16
UNNAMED_2_PI C18F2431_I95_17
UNNAMED_2_PI C18F2431_I95_18
UNNAMED_2_PIC18F2431_I95_2
UNNAMED_2_PIC18F2431_I95_3
UNNAMED_2_PIC18F2431_I95_4
UNNAMED_2_PIC18F2431_I95_5
UNNAMED_2_PIC18F2431_I95_6
UNNAMED_2_PIC18F2431_I95_7
UNNAMED_2_SD06H0SK_I35_PIN1UNNAMED_2_SD06H0SK_I35_PIN2
VCC
VCEN-C
VDEN-C
VOUT
V_5V
V_5V
Switch Position654321
PWM Frequency xxx000 25kHz
xxx001 50kHz
xxx010100kHz
xxx011200kHz
xxx100300kHz
xxx101400kHz
xxx110500kHz
xxx111625kHz
External Inputs 111111
Dead Time 0 0 0 x x x 0.0µs
001xxx 0.1µs
0 1 0 x x x 0.2µs
0 1 1 x x x 0.3µs
1 0 0 x x x 0.4µs
1 0 1 x x x 0.5µs
1 1 0 x x x 0.6µs
1 1 1 x x x 0.7µs

UG167 Rev.1.00 Page 17 of 30 Jul 31, 2018 HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
Figure 13. HIP2105DBEVAL1Z Daughter Card Schematic
A
A
A
A
J2-9
1
C4
OPEN
J1-3
7
J2-1
9
16V
C3
4.7UF
R5
24.9
TP4
TP6
J1-4
6
J2-2
8
OPEN
C2
24.9
R6
R1
0
OPEN
C6
J1-5
5
J2-3
7
TP1
D4
1 2
D1
1 2
OPEN
R3
J1-6
4
J2-4
6
TP3
0.1UF
C5
J1-7
3
J2-5
5
TP2
TP9
OPEN
C1
TP7
J1-8
2
J2-6
4
R7
0
0
R2
OPEN
C7
J1-9
1
J2-7
3
NC
LI
HI
EP
UGATE
GND LGATE
VCC
PHASE
BOOT
NC
HIP2105FRZ
U1
1
2
3
4
5 6
7
8
9
10
11
J1-1
9
D2
1 2
TP8
J2-8
2
TP5
J1-2
8
D3
1 2
AGND
AGND
BOOT
HI
HI-IN
LGATE LGATE-OUT
LI
LI-IN
PHASE
PHASE-OUT
UGATE
UGATE-OUT
VCC

UG167 Rev.1.00 Page 18 of 30 Jul 31, 2018 HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
Figure 14. HIP2106ADBEVAL1Z Daughter Card Schematic
A
A
A
A
A
J1-5
5
OPEN
C6
J2-9
1
D4
1 2
OPEN
C2
J2-1
9
J1-6
4
OPEN
R3
TP4
TP2
J2-2
8
J1-7
3
0.1UF
C5
TP9
PHASE
VCC
LGATEGND
UGATE
EP
NC
PWM
NC
VCTRLBOOT
HIP2106AIRZ
U1
1
2
3
4
5 6
7
8
9
10
11
J2-3
7
J1-8
2
TP7
R7
0
J2-4
6
J1-9
1
C7
OPEN
4.7UF
C3
16V
J1-1
9
TP5
J2-5
5
TP8
TP1
J1-2
8
0
R1
J2-6
4
D3
1 2
D2
J1-3
7
OPEN
C4
J2-7
3
24.9
R5
0
R2
J1-4
6
TP6
J2-8
2
24.9
R6
AGND
AGND
BOOT
HI-IN
LGATE
LGATE-OUT
PHASE
PHASE-OUT
PWM UGATE
UGATE-OUT
UNNAMED _1_HIP2106A_I224_9
VCC

UG167 Rev.1.00 Page 19 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
3.3 Board Layouts
3.3.1 HIP2105DBEVAL1Z
Figure 15. HIP2105DBEVAL1Z Top Silkscreen

UG167 Rev.1.00 Page 20 of 30
Jul 31, 2018
HIP2105-6MBEVAL1Z 3. PCB Layout Guidelines
Figure 16. HIP2105DBEVAL1Z Top Layer
Figure 17. HIP2105DBEVAL1Z Bottom Layer