Renesas ISL81802EVAL2Z User manual

ISL81802EVAL2Z
Evaluation Board
R16UH0003EU0100 Rev.1.00 Page 1 of 25
Aug.24.20
User Manual
The ISL81802EVAL2Z dual-output evaluation board (shown in Figure 4) features the ISL81802, an 80V high
voltage dual synchronous buck controller that offers external soft-start, independent enable functions, and
integrates UV/OV/OC/OT protection. A programmable switching frequency ranging from 100kHz to 1MHz helps to
optimize inductor size while the strong gate driver delivers up to 10A for each output.
Key Features
• Wide input range: 18V to 80V for 12V output, 6V to 80V for 5V output
• High light-load efficiency in pulse skipping DEM operation
• Programmable soft-start
• Optional DEM/PWM operation
• Optional CC/HICCUP OCP protection
• Supports pre-bias output with soft-start
• PGOOD indicator
• OVP, OTP, and UVP protection
• Back biased from output to improve efficiency
Specifications
The ISL81802EVAL2Z dual-output evaluation board is designed for high current applications. The current rating
of the ISL81802EVAL2Z is limited by the FETs and inductor selected. The ISL81802EVAL2Z electrical ratings are
shown in Ta ble 1.
Ordering Information
Related Literature
For a full list of related documents, visit our website:
•ISL81802 device page
Table 1. ISL81802EVAL2Z Electrical Ratings
Parameter Rating
Input Voltage 18V to 80V (6V to 80V for 5V output)
Switching Frequency 200kHz
Output Voltage 1 12V
Output Current 1 10A
Output Voltage 2 5V
Output Current 2 10A
OCP Set Point Minimum 12.6A each output at ambient room temperature
Part Number Description
ISL81802EVAL2Z High Voltage Dual Buck Controller Evaluation Board

ISL81802EVAL2Z
R16UH0003EU0100 Rev.1.00 Page 2 of 25
Aug.24.20
Figure 1. ISL81802EVAL2Z Block Diagram
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ISL81802EVAL2Z 1. Functional Description
R16UH0003EU0100 Rev.1.00 Page 3 of 25
Aug.24.20
1. Functional Description
The ISL81802EVAL2Z is the same test board used by Renesas application engineers and IC designers to
evaluate the performance of the ISL81802 TQFN IC. The board provides an easy and complete evaluation of all
the IC and board functions.
As shown in Figure 3, the 6V to 80V VIN is supplied to J1 (+) and J2 (-). The regulated 12V output is on J4 (+) and
J5 (-), while the regulated 5V output is on J17 (+) and J16 (-). They both can supply up to 10A to the load. Due to
the high power efficiency, the evaluation board can run at 20A in total continuously without airflow at ambient
room temperature conditions.
Test points TP1 through TP25 provide easy access to the IC pin and external signal injection terminals.
As shown in Tabl e 2 , connector J6 provides a selection of either Forced PWM mode (shorting Pin 1 and Pin 2) or
DEM mode (shorting Pin 2 and Pin 3). Connector J7 provides a selection of either constant current limit (shorting
Pin 1 and Pin 2) or HICCUP OCP (shorting Pin 2 and Pin 3). Connector J3 provides an option to disable the
converter by shorting its Pin 1 and Pin 2.
1.1 Recommended Testing Equipment
The following materials are recommended for testing:
• 0V to 80V power supply with at least 30A source current capability
• Electronic loads capable of sinking current up to 30A
• Digital Multimeters (DMMs)
• 100MHz quad-trace oscilloscope
1.2 Operating Range
The input voltage range is from 18V to 80V for the 12V output, while the input voltage range is from 6V to 80V for
the 5V output. If the output voltage is set to a lower value, the minimum VIN can be reset to a lower value by
changing the ratio of R1and R5. The minimum EN threshold that VIN can be set to is 4.5V.
The rated load current for each output is 10A with the OCP point set at a minimum 12A at ambient room
temperature conditions. The operating temperature range of this board is -40°C to +85°C.
Note: Airflow is needed for higher ambient temperature conditions.

ISL81802EVAL2Z 1. Functional Description
R16UH0003EU0100 Rev.1.00 Page 4 of 25
Aug.24.20
1.3 Quick Test Guide
1. Jumper J6 provides the option to select PWM or DEM. Jumper J7 provides the option to select a constant
current limit or HICCUP. See Table 2 for the operating options. Ensure that the circuit is correctly connected to
the supply and electronic loads before applying any power. See Figure 3 for the proper setup.
2. Turn on the power supply.
3. Adjust the input voltage (VIN) within the specified range and observe the output voltage. The output voltage
variation should be within 3%.
4. Adjust the load current within the specified range and observe the output voltage. The output voltage variation
should be within 3%.
5. Use an oscilloscope to observe output voltage ripple and phase node ringing. For accurate measurement, see
Figure 2 for the proper test setup.
Table 2. Operating Options
Jumper Position Function
3 EN-GND Disable output
EN Floating Enable output
6Pin1-2 PWM
Pin 2-3 DEM
7 Pin 1-2 Constant current limit
Pin 2-3 HICCUP
Figure 2. Proper Probe Setup to Measure Output Ripple and Phase Node Ringing
Figure 3. Proper Test Setup
Output Capacitor
or MOSFET
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ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 5 of 25
Aug.24.20
2. PCB Layout Guidelines
Careful attention to Printed Circuit Board (PCB) layout requirements is necessary for the successful
implementation of an ISL81802 based DC/DC converter. The ISL81802 switches at a high frequency; therefore,
the switching times are short. At these switching frequencies, even the shortest trace has significant impedance
and the peak gate drive current rises significantly in an extremely short time. The transition speed of the current
from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and
ringing. Careful component selection and proper PCB layout minimize the magnitude of these voltage spikes.
Three sets of components are critical when using the ISL81802 DC/DC converter:
• Controller
• Switching power components
• Small-signal components
The switching power components are the most critical to the layout because they switch a large amount of energy,
which tends to generate a large amount of noise. The critical small-signal components are those connected to
sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.
Complete the following steps to optimize the PCB layout:
1. Place the input capacitors, FETs, inductor, and output capacitor first. Isolate these power components on
dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output
high-frequency decoupling ceramic capacitors very close to the MOSFETs.
2. If signal components and the IC are placed separately from the power train, Renesas recommends using full
ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise,
use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND
together close to the IC. Note: DO NOT connect them together anywhere else.
3. Keep the loop formed by the input capacitor, the top FET, and the bottom FET as small as possible.
4. Ensure the current paths from the input capacitor to the FETs, the power inductor, and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the lower FETs. The low-side FETs gate drive connections should be
short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.
6. Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND
pin. Connect the PGND pin to the ground plane by a via.
Note: DO NOT connect the PGND pin directly to the SGND EPAD.
7. Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.
8. Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output
capacitors to load to avoid inductance and resistances.
9. Use copper filled polygons or wide, short traces to connect the junction of the upper FET, lower FET, and output
inductor. Keep the PHASE nodes connection to the IC short. Note: DO NOT unnecessarily oversize the copper
islands for the PHASE nodes. Because the phase nodes are subjected to very high dv/dt voltages, the stray
capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.
10. Route all high-speed switching nodes away from the control circuitry.
11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. Connect all
small signal grounding paths including feedback resistors, current monitoring resistors and capacitors,
soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors to this SGND
plane.
12. Use a pair of traces with minimum loop for the input or output current sensing connection.
13. Ensure the feedback connection to the output capacitor is short and direct.

ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 6 of 25
Aug.24.20
2.1 ISL81802EVAL2Z Evaluation Board
Figure 4. ISL81802EVAL2Z Evaluation Board, Top View
Figure 5. ISL81802EVAL2Z Evaluation Board, Bottom View

ISL81802EVAL2Z 2. PCB Layout Guidelines R16UH0003EU0100 Rev.1.00 Page 7 of 25 Aug.24.20
2.2 ISL81802EVAL2Z Circuit Schematic
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ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 8 of 25
Aug.24.20
2.3 Bill of Materials
Qty Reference Designator Description Manufacturer Manufacturer Part
1 PWB-PCB, ISL81802EVAL1Z, REVB, ROHS Multilayer
PCB Technology
ISL81802EVAL1ZREVBPCB
2 C1, C2 CAP, RADIAL, 12.5x26.5, 220μF, 100V,
20%, ALUM.ELEC., 5mm, ROHS
United Chemi-Con EKZN101ELL221MK25S
8 C3, C4, C5, C6, C42, C43,
C44, C45
CAP-AEC-Q200, SMD, 1210, 4.7μF, 100V,
10%, X7S, ROHS
TDK CGA6M3X7S2A475K200AB
3 C7, C12, C51 CAP, SMD, 0603, 1000pF, 50V, 10%, X7R,
ROHS
TDK C1608X7R1H102K080AE
3 C8, C41, C53 CAP, SMD, 0603, 0.1µF, 100V, 10%, X7R,
ROHS
Vishay GRJ188R72A104KE11D
4 C9, C22, C47, C50 CAP, SMD, 0603, 0.047µF, 25V, 10%, X7R,
ROHS
TDK CGJ3E2X7R1E473K080AA
1 C11 CAP, SMD, 0603, 10µF, 16V, X5R, 10%,
ROHS
Murata GRM188R61C106KAALJ
2 C15, C49 CAP, SMD, 0603, 220pF, 50V, 10%, X7R,
ROHS
Murata GRM188R71H221KA01D
2 C16, C39 CAP, SMD, 0603, 0.47µF, 25V, 10%, X7R,
ROHS
Murata GRM188R71E474KA12D
2 C17, C48 CAP, SMD, 0603, 0.022µF, 25V, X7R, ROHS TDK CGJ3E2X7R1E223K080AA
8 C18, C19, C20, C23, C34,
C35, C36, C37
CAP, SMD, 1210, 22µF, 25V, X7R, ROHS Murata GRM32ER71E226KE15L
2 C21, C38 CAP-OSCON, SMD, 10mm, 1000μF, 16V,
20%, 12mΩ, ROHS
Panasonic 16SVPF1000M
2 C24, C26 CAP, SMD, 0805, 10µF, 16V, 10%, X7S,
ROHS
Murata GRM21BC71C106KE11L
5 C27, C29, C30, C31, C32 CAP, SMD, 0603, 0.01µF, 100V, 5%, X7R,
ROHS
Kemet C0603C103J1RACTU
1 C28 CAP, SMD, 0603, 820pF, 50V, 10%, X7R,
ROHS
Kemet C0603C821K5RACTU
0 C13, C14, C25, C33, C46,
C52, C54, C55
CAP, SMD, 0603, DNP-PLACE
HOLDER, ROHS
3 D1, D3, D4 DIODE-RECTIFIER, SMD, 2P, S0D-123FL,
100V, 1A, ROHS
ON Semiconductor MBR1H100SFT3G
6 J1, J2, J4, J5, J6, J17 HDWARE, TERMINAL, M4 METRIC
SCREW, TH, 4P, SNAP-FIT, ROHS
Keystone 7795
1 J3 CONN-HEADER, 1x2, BRKAWY 1x36,
2.54mm, ROHS
BERG/FCI 68000-236HLF
2 J6, J7 CONN-HEADER, 1x3, BREAKAWY 1x36,
2.54mm, ROHS
BERG/FCI 68000-236HLF
0 J12, J13, J14, J15, J18, J19 2.54mm Headers, DNP-PLACE HOLDER,
ROHS
1 L1 COIL-PWR INDUCTOR, SMD, 6.8μH, 20%,
15A, 4.1mΩ, ROHS
Wurth 74439370068
1 L2 COIL-PWR INDUCTOR, SMD, 4.7μH, 20%,
17A, 3.5mΩ, ROHS
Wurth 74439370047
1 U1 80V DUAL-BUCK PWM CONTROLLER,
32P, TQFN, 5x5, ROHS
Renesas Electronics
America
ISL81802FRTZ
4 Q2, Q3, Q5, Q7 TRANSISTOR-MOS, N-CHANNEL, SMD,
8P, PPK SO-8, 100V, 80A, ROHS
Infineon BSC070N10NS5ATMA1
0 Q1, Q4, Q6, Q8 DO NOT POPULATE OR PURCHASE

ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 9 of 25
Aug.24.20
1 R1 RES SMD 430kΩ1% 1/4W 1206 Panasonic ERJ-8ENF4303V
3 R2, R5, R43 RES SMD 48.7kΩ1% 1/10W 0603 Yageo RC0603FR-0748K7L
2 R3, R45 RES SMD 20Ω1% 1/10W 0603 Yageo RC0603FR-0720RL
4 R6, R10, R25, R48 RES SMD 1Ω1% 1/10W 0603 Panasonic ERJ-3RQF1R0V
1 R7 RES SMD 5.1Ω1% 1/10W 0603 Yageo RC0603FR-075R1L
2 R8, R26 RES SMD 40.2kΩ1% 1/10W 0603 Yageo RC0603FR-0740K2L
2 R11, R27 RES SMD 5.1kΩ1% 1/10W 0603 Yageo RC0603FR-075K1L
1 R12 RES SMD 3.48kΩ1% 1/10W 0603 Yageo RC0603FR-073K48L
2 R14, R22 RES SMD 0.004Ω3W 2512 WIDE Susumu KRL6432E-M-R004-F-T1
1 R46 RES SMD 0Ω1% 1/10W 0603 Yageo RC0603JR-070RL
2 R16, R21 RES SMD 3.3Ω1% 1/10W 0603 Yageo RC0603FR-073R3L
4 R18, R30, R32, R38 RES SMD 22kΩ1% 1/10W 0603 Yageo RC0603FR-0722KL
1 R19 RES SMD 169kΩ1% 1/10W 0603 Venkel CR0603-10W-1693FT
1 R20 RES SMD 2.7kΩ1% 1/10W 0603 Yageo RC0603FR-072K7L
1 R23 RES SMD 100kΩ1% 1/10W 0603 Yageo RC0603FR-07100KL
2 R31, R33 RES SMD 39kΩ1% 1/10W 0603 Yageo RC0603FR-0739KL
1 R39 RES SMD 9.31kΩ1% 1/10W 0603 Yageo RC0603FR-079K31L
0 RT2, RT5, R15, R17, R34,
R35, R41, R44, R47, R49,
R50, R51, R52, R53, R54,
R55, R56, R57
RES, SMD, 0603, DNP-PLACE HOLDER,
ROHS
15 TP1, TP2, TP3, TP5, TP7,
TP9, TP10, TP13, TP14,
TP15, TP18, TP22, TP23,
TP24, TP25
CONN-COMPACT TEST PT, VERTICAL,
WHT, ROHS
Keystone 5007
3 J3, J6, J7 CONN-JUMPER, SHORTING, 2PIN,
BLACK, GOLD, ROHS
Sullins SPC02SYAN
4 Four corners SCREW, 4-40x1/4in, PHILLIPS, PANHEAD,
STAINLESS, ROHS
Keystone 2204
4 Four corners STANDOFF, 4-40x3/4in, F/F, HEX,
ALUMINUM, 0.25 OD, ROHS
Keystone 7795
Qty Reference Designator Description Manufacturer Manufacturer Part

ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 10 of 25
Aug.24.20
2.4 Board Layout
Figure 7. Silkscreen Top
Figure 8. Top Layer

ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 11 of 25
Aug.24.20
Figure 9. Second Layer (Solid Ground)
Figure 10. Third Layer

ISL81802EVAL2Z 2. PCB Layout Guidelines
R16UH0003EU0100 Rev.1.00 Page 12 of 25
Aug.24.20
Figure 11. Bottom Layer
Figure 12. Silkscreen Bottom

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 13 of 25
Aug.24.20
3. Design Example
3.1 Design Requirements
3.2 Frequency Setting
The default switching frequency of the PWM controller is determined by the resistor RT(R19). It adjusts the default
switching frequency from 100kHz to 1MHz. The RT value for fSW = 200kHz is calculated using Equation 1.
where fSW is the switching frequency in MHz. Select a standard value resistor RT = 169kΩ.
3.3 Output Voltage Setting
The output voltage can be set from 0.8V up to a level determined by the feedback voltage divider. A resistive
divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT
pin.
With VOUT1 =12V,R
FBO1 (R2) = 487k, the RFBO2 (R12) value is calculated using Equation 2.
Select a standard value resistor RFBO2 = 34.8kΩ.
With VOUT2 = 5V, RFBO1 (R43) = 487k, the RFBO2 (R39) value is calculated using Equation 3.
Select a standard value resistor RFBO2 = 93kΩ.
RFBO1 is the top resistor of the feedback divider network and RFBO2 is the bottom resistor connected from
FB_OUT to ground. To avoid an unstable state during hiccup, the value of RFBO1 and RFBO2 in parallel should be
no less than 30k.
Parameter Rating
Input Voltage 18V to 80V for 12V output
6V to 80V for 5V output
Switching Frequency 200kHz
Output Voltage 1 12V
Output Current 1 10A
Output Voltage 2 5V
Output Current 2 10A
OCP Set Point 12.6A for each output
Output Mode Dual output
PWM Mode Forced PWM
OCP Mode Constant current
RT
34.7
fSW
----------- 4.78–


34.7
0.2
----------- 4.78–168.72k===
(EQ. 1)
RFBO2 12V
0.8V RFBO1 
VOUT1 0.8V–
-------------------------------------- 0.8V 487k
12V 0.8V–
------------------------------------- 34.78k===
(EQ. 2)
RFBO2 5V
0.8V RFBO1 
VOUT2 0.8V–
-------------------------------------- 0.8V 487k
5V 0.8V–
------------------------------------- 92.8k===
(EQ. 3)

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 14 of 25
Aug.24.20
3.4 UVLO Setting
The ISL81802 has input UVLO protection. When the voltage on the EN/UVLO pin reaches 1.8V, the PWM
modulator is enabled. Accurate UVLO feature can be implemented by feeding the VIN into the EN/UVLO pin using
a voltage divider, RUV1 (R1) and RUV2 (R5). The VIN UVP rising threshold is calculated using Equation 4.
The VIN UVP falling threshold is calculated using Equation 5.
where VUVLO_THR is the 1.8V UVLO rising threshold and IUVLO_HYST is the 3.4µA UVLO hysteresis current.
3.5 Soft-Start Capacitor
The soft-start time for dual output is set by the value of the soft-start capacitor CSS1 (C22) connected from
SS/TRK1 to GND and CSS2 (C47) connected from SS/TRK2 to GND separately. The soft-start time with
CSS1 =C
SS2 = 47nF is calculated using Equation 6.
When the soft-start time set by external CSS or tracking is less than 1.7ms, an internal soft-start circuit of 1.7ms
takes over the soft-start.
3.6 MOSFET Considerations
The MOSFETs are selected based on rDS(ON), gate supply requirements, and thermal management
considerations. The maximum operation voltage of the MOSFETs in Buck mode is decided by the maximum VIN
voltage.
The power loss of the upper and lower MOSFETs for the 12V output are calculated using Equation 7 and
Equation 8. The equations assume linear voltage current transitions and do not model power loss due to the
reverse recovery for the body diode of the lower MOSFET.
Ensure that all MOSFETs are within their maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal resistance specifications.
(EQ. 4) VUVRISE
VUVLO_THR RUV1 RUV2 +ILEAK –RUV1RUV2
RUV2
----------------------------------------------------------------------------------------------------------------------------------1.8V 430k48.7k+1.4A–430k48.7k
48.7k
-------------------------------------------------------------------------------------------------------------------------------------17.09V== =
VUVFALL
VUVLO_THR RUV1 RUV2 +IUVLO_HYST–RUV1RUV2
RUV2
--------------------------------------------------------------------------------------------------------------------------------------------------------
1.8V 430k48.7k+3.4A–430k48.7k
48.7k
-------------------------------------------------------------------------------------------------------------------------------------16.23V
=
==
(EQ. 5)
tSS 0.8V
CSS
2A
-----------


0.8V 47nF
2A
--------------


18.8ms== =
(EQ. 6)
PUPPERMAX
IOUT
2
rDS ON VOUT 
VINMAX
-----------------------------------------------------------------------IOUT
VINMAX tSW fSW 
2
------------------------------------------------------------------------------+
10A2
6m12V
80V
------------------------------------------------------
10A80V 6nC
8V 4.9V–
3.3
--------------------------


--------------------------------6nC
4.9V
3.3
-------------


-------------------+





200kHz
2
---------------------------------------------------------------------------------------------------------------------------+0.09W 0.834W+0.843W
=
===
(EQ. 7)
PLOWERMAX
IOUT
2
rDS ON VINMAX VOUT –
VINMAX
---------------------------------------------------------------------------------------------------
10A
26m80V 12V–
80V
------------------------------------------------------------------------0.51W
=
==
(EQ. 8)

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 15 of 25
Aug.24.20
3.7 Inductor Selection
The inductor value determines the ripple current of the converter. The ripple voltage is a function of the ripple
current and the output capacitor(s) ESR. Assume the ripple current ratio is 80% of the inductor average current at
the maximum input voltage and the full output load condition. The inductor value for the 12V output is calculated
using Equation 9.
The recommended inductor value is 6.8µH. Then the ripple current and peak current are calculated using
Equation 10, Equation 11, and Equation 12.
The saturation current of the inductor should be larger than 16.35A. The heat rating current of the inductor should
be larger than 10.23A.
The maximum DC power dissipation in the inductor is calculated using Equation 13.
3.8 Output Capacitor Selection
The maximum capacitor value required to provide the full, rising step, transient load current during the response
time of the inductor for the 12V output is shown in Equation 14.
where COUTMIN is the minimum output capacitor(s) required, ITRAN is the transient load current step, and ΔVOUT
is the drop in output voltage allowed during the load transient. Choose a capacitor no less than 314.8µF for each
phase. 1000µF electrolytic capacitor and 88µF MLCC in total are used for each output on this board.
The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by
Equation 15.
LINMIN
VINMAX VOUT –VOUT 
fSW
0.8 IOUTMAX VINMAX 
------------------------------------------------------------------------------------------80V 12V–12V
200kHz0.8 10A80V
--------------------------------------------------------------------------6.375H===
(EQ. 9)
ILMAX
VINMAX VOUT –VOUT 
fSW
LVINMAX 
---------------------------------------------------------------------- 80V 12V–12V
200kHz6.8H80V
-----------------------------------------------------------------7.5A===
(EQ. 10)
ILRMS IOUTMAX 
2ILMAX

2
12
-----------------------------+10A
27.5A
2
12
--------------------+10.23A===
(EQ. 11)
ILPEAKMAX IOUTOCP
ILMAX
2
---------------------+12.6A 7.5A
2
------------+16.35A===
(EQ. 12)
PLMAX IOUT 
2DCR10A 24.1m0.41W== =
(EQ. 13)
COUTMIN
LI
TRAN

2
2V
INMIN VOUT
–VOUT 
-----------------------------------------------------------------------------6.8F 10A 0A–
2

218V 12V–12V 1.5
100
----------



---------------------------------------------------------------------- 314.8F===
(EQ. 14)
VRIPPLE ILMAX ESR7.5A 5m 37.5mV===
(EQ. 15)

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 16 of 25
Aug.24.20
3.9 Input Capacitor Selection
The important parameters for the input capacitors are the voltage rating and the RMS current rating. The
capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a
conservative guideline. The AC RMS input current varies with the load given in Equation 16.
The maximum RMS current supplied by the input capacitance occurs at VIN = 2VOUT, D = 50% as shown in
Equation 17.
Renesas recommends using a mix of input bypass capacitors to control the voltage ripple across the MOSFETs.
Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Two
220µF electrolytic capacitors with 2.2A rating current and eight 4.7µF ceramic capacitors are used to share the 5A
RMS input current on this board.
3.10 First Level Peak Current Limit and Sense Resistor Selection
The inductor peak current for 12V output is sensed by the shunt resistor RS (R14). When the voltage drop on RS
reaches the set point VOCSET-CS typical 85mV, it triggers the pulse-by-pulse peak current limit. With current limit
set point IOCPP1 = 2xIOUTMAX = 20A, the value of the sense resistor is calculated using Equation 18.
Select a standard value resistor RS = 4mΩ. Then the actual peak current limit is calculated using Equation 19.
The maximum power dissipation in RSis calculated using Equation 20.
Therefore, a sense resistor with 1W power rating is sufficient for this application.
3.11 Second Level Hiccup Peak Current Protection
In the output dead short condition especially at high VIN, the inductor current runs away with the minimum on
PWM duty. The ISL81802 integrates a second level hiccup type of peak current protection. The second level peak
current protection set point IOCPP2 is calculated using Equation 21.
IRMS DD
2
–IOUT =
(EQ. 16)
IRMSMAX
1
2
---IOUTMAX
1
2
---10A5A===
(EQ. 17)
RS
VOCSET CS–
IOCPP1
---------------------------------- 85mV
20A
---------------- 4.25m===
(EQ. 18)
IOCPP1
VOCSET CS–
RS
---------------------------------- 85mV
4m
---------------- 21.25A===
(EQ. 19)
PRSMAX IOUT 
2RS10A 24m0.4W== =
(EQ. 20)
IOCPP2
VOCSET-CS-HIC
RS
--------------------------------------------115mV
4m
------------------- 28.75A===
(EQ. 21)

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 17 of 25
Aug.24.20
3.12 Output Average Overcurrent Protection and RIM Selection
The ISL81802 provides either constant current or hiccup type of overcurrent protection for output average current.
The OCP mode is set by a resistor connected between the LG2/OC_MODE pin and ground. With the output
constant current/hiccup set point IOUTOCP = 12.6A for each output, the current monitoring resistor RIM (R8) is
calculated using Equation 22.
Select a standard value resistor RIM = 40.2kΩ.
3.13 PWM Mode Selection
You can set the ISL81802 to either forced PWM mode or DE mode. The mode is set by a resistor RPWMMODE (R30
or R31) connected between the LG1/PWM_MODE pin and GND. The critical resistor value for RPWMMODE is
calculated using Equation 23.
A resistor less than 30kΩsets the converter to forced PWM mode, while a resistor higher than 30kΩsets the
converter to DE mode. Considering the tolerance in all temperature ranges, Renesas recommends using 15kΩto
set to Forced PWM node and 51kΩto set to DE mode.
3.14 Overcurrent Protection Mode Selection
The ISL81802 is set to either a constant current or hiccup type of overcurrent protection for output average
current by selecting a different value of the resistor ROCMODE (R32 or R33) connected between LG2/OC_MODE
and GND. The critical resistor value for ROCMODE is calculated using Equation 24.
A resistor less than 30kΩsets the converter to Constant Current mode, while a resistor higher than 30kΩsets the
converter to Hiccup mode. Considering the tolerance in all temperature ranges, Renesas recommends using
21kΩto set to constant current and 39kΩto set to hiccup mode.
3.15 Phase Lock Loop (PLL)
The PLL of the ISL81802 ensures the wide range of accurate clock frequency and phase setting. It also makes
the internal clock easily synchronized to an external clock with the frequency either lower or higher than the
internal setting. The external compensation network of RPLL (R20), CPLL1 (C27), and CPLL2 (C28) is needed to
connect to the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩfor RPLL,
10nF for CPLL1, and 820pF for CPLL2.
RIM
1.2
IOUTOCP RSGmCS
 ICSOFFSET +
--------------------------------------------------------------------------------------------------------1.2V
12.6Ax4mx195S20A+
----------------------------------------------------------------------------- 40.23k===
(EQ. 22)
(EQ. 23) RPWMMODE
0.3V
10A
---------------30k==
(EQ. 24) ROCMODE
0.3V
10A
---------------30k==

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 18 of 25
Aug.24.20
3.16 Feedback Loop Compensation
To adapt the different applications, the controller is designed with an externally compensation network. Figure 13
shows the peak current mode buck converter circuit.
In the current loop, the control to output simplified transfer function is shown in Equation 25.
where:
•R
Ois the load resistor
•C
Ois the output capacitor
• L is the inductor
•R
Sis the current sense resistor
•V
Ois the output voltage
•T
Sis the period of one switching cycle
• D is the duty cycle of upper MOSFET
•V
SL = 0.843V, is the slope compensation voltage
•V
IN is the input voltage of the buck
•V
Cis the output of the error amplifier
•G
I= 5.472, is the gain of the current sensor
Figure 13. Peak Current Mode Buck Converter Circuit
V
O
Vc
V
REF
(0.8V)
gm
C
2
R
3
C
3
R
2
R
1
C
1
Fm
Gi
Rs
Slope
R
ESR
C
O
R
O
L
V
IN
Clock
R
SQ
QN
I
L
D
(EQ. 25) VO
ˆ
VC
ˆ
--------
RO
RIKd 
-------------------
1s
zesr
-------------------+
1s
po
----------+


1s
pi
--------+


--------------------------------------------------
=
(EQ. 26) Kd1RO
KmRI 
---------------------+=
(EQ. 27) Km
1
0.5 D–RI
Ts
L
------
VSL
VIN
-----------+
------------------------------------------------------------=
(EQ. 28) RIGIRS
=

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 19 of 25
Aug.24.20
The low frequency pole frequency is shown in Equation 29.
The high frequency pole frequency is shown in Equation 30.
The output capacitor ESR (RESR) zero frequency is shown in Equation 31.
The output voltage is regulated by an error amplifier EA. The EA compensation network parameters can be
determined by compensating the current loop poles and zero so as to implement an ideal -20dB/decade
close-loop gain with around 0.1xfsw crossover frequency.
If the crossover frequency fc<< fpi, a type-2 compensation network is enough to achieve the goal.
Because a strong slope compensation is used, the fpi is usually not too high but close to fc. Therefore, a type-3
amplifier is still needed.
To simplify the model, assuming C3<< C2, the type-3 EA amplifier transfer function is simplified to Equation 32.
The transfer function has two poles and two zeros.
• The first pole at the original at the frequency of fp1 = 1/2πR1C2. This is the frequency where the impedance of
R1is equal to C2.
• The second pole is at the frequency of fp2 = 1/2πR3C3.
• The first zero is at the frequency of fz1 = 1/2πR3C2.
• The second zero is at the frequency of fz2 = 1/2πR1C1
To achieve ideal compensation, Renesas recommends making fz1= fp0, fz2 = fpi and fp2 = fz(esr) as shown in
Figure 14.
Figure 14. Feedback Loop Compensation
(EQ. 29) p0 2fp0
1
CO
-------- 1
RO
-------- 1
KmRI

---------------------+


==
(EQ. 30) pi 2fpi
KmRI 
L
---------------------==
zesr2fzesr 1
CoRESR

-----------------------------==
(EQ. 31)
Vc
ˆ
Vo
ˆ
-------1sR
3C2
+1sR
1C1
+
sR1C21sR
3C3
+
-------------------------------------------------------------------=
(EQ. 32)
Compensation
f
Z1
f
p2
f
p0
f
C
Modulator
f
z2
f
pi
f
z(esr)
Converter
f
Gain

ISL81802EVAL2Z 3. Design Example
R16UH0003EU0100 Rev.1.00 Page 20 of 25
Aug.24.20
The close-loop transfer function is then simplified to Equation 33.
The crossover frequency is shown in Equation 34.
The Loop design example for the 12V output under the typical 48V input voltage is shown in the following:
VIN = 48V, VOUT = 12V, IOUT = 10A, fsw = 200kHz, Ts= 5μs, D = VOUT / Vin = 0.25, L = 6.8μH, CO= 1088μF
(1000μFx1+22μFx4), RO= VOUT /IOUT = 1.2Ω, Rs= 4mΩ, Resr = 5mΩ.
To make 0.1xfscrossover frequency and make the gain -20dB/decade by Equation 44.
Gloop s RO
RIKd 
-------------------
1s
zesr
-------------------+
1s
p0
----------+


1s
pi
--------+


--------------------------------------------------
1sR
3C2
+1sR
1C1
+
sR1C21sR
3C3
+
-------------------------------------------------------------------
RO
RIKd 
-------------------1
sR1C2
------------------
==
(EQ. 33)
fc
RO
KdRI 
-------------------1
2R1C2
----------------------
=
(EQ. 34)
Km
1
0.5 D–RI
Ts
L
------
VSL
VIN
-----------+
------------------------------------------------------------ 1
0.5 0.25–4m5.472
5s
6.8H
-----------------
0.843V
48V
-------------------+
-------------------------------------------------------------------------------------------------------------------------46.33== =
(EQ. 35)
Kd1RO
KmRI 
--------------------+11.2
46.33 0.022
-----------------------------------------+ 2.177== =
(EQ. 36)
Gdc
RO
KdRI 
-------------------1.2
2.177 0.022
-----------------------------------------25.06== =
(EQ. 37)
p0
1
CO
-------- 1
RO
-------- 1
KmRI

--------------------+


1
1088F
---------------------1
1.2
-------------1
46.33 0.022
-----------------------------------------+


1.52kHz== =
(EQ. 38)
fp0
p0
2
---------- 0.24kHz==
(EQ. 39)
pi
KmRI 
L
-------------------- 46.33 0.022
6.8H
-----------------------------------------149.9kHz== =
(EQ. 40)
fpi
pi
2
-------- 23.87kHz==
(EQ. 41)
zesr 1
CORESR

-------------------------------1
1088F5m
----------------------------------------- 183.8kHz== =
(EQ. 42)
fzesr
zesr
2
------------------- 29.3kHz==
(EQ. 43)
fc0.1 fsw 20kHz==
(EQ. 44)