Renesas RTKA214023DE0000BU User manual

Evaluation Board Manual
R16UZ0020EU0100 Rev.1.00 Page 1
Sep 16, 2021 © 2021 Renesas Electronics
The RTKA214023DE0000BU evaluation board
provides a simple platform to evaluate the
RAA214023. It contains all the important circuitry
needed to characterize critical performance
parameters.
The RAA214023 is a low noise, high PSRR, low
dropout voltage regulator. It accepts a input voltage
range of 2.7V to 5.5V, and the output voltage can be
programmed from 0.8V to 3.95V by means of voltage
setting pins. To extend the output voltage range up to
5.5V-VDROPOUT, an external resistor divider feedback
network can be used. The device can source a load
current of up to 2A and has an output voltage
accuracy of ±1.75% over line, load, and temperature.
Features
▪Input Voltage Range: 2.7V to 5.5V
▪Voltage Set Pins easily programmed with JP1: 0.8V
to 3.95V
▪Switch between Voltage Set pins or Eternal
Resistor Divider using jumper JP_FB
▪Convenient shutdown mode function using Jumper
JP_EN
▪Power good (PG) indication test point
Specifications
This board has been optimized for the following
operating conditions:
▪VIN range from 2.7V to 5.5V
▪VOUT adjustable from 0.8V to 3.95V with Voltage
Set Pins
▪VOUT adjustable from 0.8V up to 5.5V - VDROPOUT
with External Resistor Divider
▪Low dropout: 420mV at 2A and VIN= 3.3V (typical)
▪High PSRR for VHEADROOM= 1.7V:
• 100kHz: 62dB at 2A and 85dB at 500mA
• 1MHz: 51dB at 2A and 60dB at 500mA
Figure 1. Block Diagram
IN
OUT
CSET
SNS
FB
EN
PG
1.6V
NC
50mV
RAA214 023
1µF
10kΩ
22µF
0.1µF 10µF0.1µF
V
OUT
3.3V,
I
OUT ( MAX )
2A
V
IN
2.7V – 5.5V
V
PG
R3
C5
C6 C2C3
C4
10kΩ
R1
RTKA214023DE0000BU

R16UZ0020EU0100 Rev.1.00 Page 2
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Setting the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Setting Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Enabling and Disabling the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Quick Start Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Schematic Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

R16UZ0020EU0100 Rev.1.00 Page 3
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
1. Functional Description
The RTKA214023DE0000BU evaluation board provides a simple platform to evaluate the features of the
RAA214023 low-noise, high PSRR LDO and help characterize important critical performance parameters. The
evaluation board is functionally optimized to allow efficient operation up to the maximum output current of 2A.
1.1 Setting the Output Voltage
The output voltage can be programmed by means of the PCB layout or with traditional feedback resistors. To
switch between the two configurations, the 3-pin JP_FB jumper is used.
1.1.1 Voltage Set Pins
The evaluation board can be configured to use the Voltage Set pins by shorting the device SNS pin to OUT using
the JP_FB jumper as shown in Figure 2.
The voltage set pins are labeled 0.05V, 0.1V, 0.2V, 0.4V, 0.8V, and 1.6V on the PCB Board. Grounding these pins
adds the voltages assigned to each grounded pin to the reference voltage (0.8V) as expressed in Equation 1.
These pins can easily be grounded on the evaluation board using the J1 jumper. In this configuration, the output
voltage can be programmed from 0.8V to 3.95V in steps of 50mV.
For example, to set VOUT(TARGET) to 3.3V ground the 0.1V, 0.8V, and 1.6V pins. The sum of these three pins
(2.5V) added to the 0.8V reference gives the expected 3.3V for the output. Table 1 is a full list of all the possible
VOUT(TARGET) and the corresponding Voltage Set pins to short to ground.
Figure 2. RTKA214023DE0010BU JP_FB Jumper for Voltage Set Pin Configuration
(EQ. 1)
Table 1. User Configurable Output Voltage Settings
VOUT
(V) 50mV 100mV 200mV 400mV 800mV 1.6V
VOUT
(V) 50mV 100mV 200mV 400mV 800mV 1.6V
0.80 Open Open Open Open Open Open 2.40 Open Open Open Open Open GND
0.85 GND Open Open Open Open Open 2.45 GND Open Open Open Open GND
0.90 Open GND Open Open Open Open 2.50 Open GND Open Open Open GND
0.95 GND GND Open Open Open Open 2.55 GND GND Open Open Open GND
VOUT 0.8V Grounded Voltage Set Pins+=

R16UZ0020EU0100 Rev.1.00 Page 4
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
1.00 Open Open GND Open Open Open 2.60 Open Open GND Open Open GND
1.05 GND Open GND Open Open Open 2.65 GND Open GND Open Open GND
1.10 Open GND GND Open Open Open 2.70 Open GND GND Open Open GND
1.15 GND GND GND Open Open Open 2.75 GND GND GND Open Open GND
1.20 Open Open Open GND Open Open 2.80 Open Open Open GND Open GND
1.25 GND Open Open GND Open Open 2.85 GND Open Open GND Open GND
1.30 Open GND Open GND Open Open 2.90 Open GND Open GND Open GND
1.35 GND GND Open GND Open Open 2.95 GND GND Open GND Open GND
1.40 Open Open GND GND Open Open 3.00 Open Open GND GND Open GND
1.45 GND Open GND GND Open Open 3.05 GND Open GND GND Open GND
1.50 Open GND GND GND Open Open 3.10 Open GND GND GND Open GND
1.55 GND GND GND GND Open Open 3.15 GND GND GND GND Open GND
1.60 Open Open Open Open GND Open 3.20 Open Open Open Open GND GND
1.65 GND Open Open Open GND Open 3.25 GND Open Open Open GND GND
1.70 Open GND Open Open GND Open 3.30 Open GND Open Open GND GND
1.75 GND GND Open Open GND Open 3.35 GND GND Open Open GND GND
1.80 Open Open GND Open GND Open 3.40 Open Open GND Open GND GND
1.85 GND Open GND Open GND Open 3.45 GND Open GND Open GND GND
1.90 Open GND GND Open GND Open 3.50 Open GND GND Open GND GND
1.95 GND GND GND Open GND Open 3.55 GND GND GND Open GND GND
2.00 Open Open Open GND GND Open 3.60 Open Open Open GND GND GND
2.05 GND Open Open GND GND Open 3.65 GND Open Open GND GND GND
2.10 Open GND Open GND GND Open 3.70 Open GND Open GND GND GND
2.15 GND GND Open GND GND Open 3.75 GND GND Open GND GND GND
2.20 Open Open GND GND GND Open 3.80 Open Open GND GND GND GND
2.25 GND Open GND GND GND Open 3.85 GND Open GND GND GND GND
2.30 Open GND GND GND GND Open 3.90 Open GND GND GND GND GND
2.35 GND GND GND GND GND Open 3.95 GND GND GND GND GND GND
Table 1. User Configurable Output Voltage Settings (Cont.)
VOUT
(V) 50mV 100mV 200mV 400mV 800mV 1.6V
VOUT
(V) 50mV 100mV 200mV 400mV 800mV 1.6V

R16UZ0020EU0100 Rev.1.00 Page 5
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
1.1.2 External Feedback Resistors
To evaluate the RAA214023 in applications where VOUT is greater than 3.95V, an external feedback resistor
divider, R4 and R5 in Figure 3, can be used.
To use this configuration, the JP_FB jumper should be connected to short the top of R4 with OUT as shown in
Figure 4. R4 and R5 need to be populated with resistors. In this configuration, VOUT can be set from 0.8V up to
5.5V-VDROPOUT.
For a required output voltage, R4 can be easily calculated by setting R5 to 10kΩand solving for Equation 2 where
VOUT(TARGET) is the required output voltage.
There might not always be a resistor that is exactly the calculated R4 value, but in most cases the closest resistor
value commercially available can be used and gives ±1% or better accuracy. Based on the actual resistor values
commercially available, the actual output voltage can be calculated with Equation 3. Then, the output voltage
percent error can be calculated using Equation 4 to decide if the accuracy meets the application design.
Note: VOUT(ACTUAL) is the VOUT value calculated in Equation 3.
Figure 3. RAA214023 External Feedback Resistors Schematic
Figure 4. RTKA214023DE0000BU JP_FB Jumper for External Feedback Configuration
(EQ. 2)
(EQ. 3)
VIN VOUT
RAA214023
VEN
FB
SNS
CSET
R
4
R
5
C
IN
C
OUT
C
SET
R
1
R4R5
VOUT TARGET
0.8V
-------------------------------------------- 1–


=
VOUT 0.8V 1 R4
R5
-------+



=

R16UZ0020EU0100 Rev.1.00 Page 6
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
For 0.1% or better accuracy, this method does not give the required accuracy for some VOUT(TARGET). To remedy
this, increase R5 to the next highest resistor value that is commercially available and calculate for R4 with
Equation 1. Next, verify that the calculated R4 resistor value is commercially available and meets the required
output accuracy. Repeat as needed. Tabl e 2 provides the feedback resistor values to obtain some common
voltage rails using this method. These values give a ±0.1% or better nominal voltage accuracy.
1.2 Setting Noise Performance
For low-noise applications, a 1µF CSET (C4) capacitor is optimal. Larger capacitor values can be used with little
benefit in lowering the internally generated output voltage noise and PSRR for frequencies above 10Hz. C7 is a
spot for a feed-forward capacitor and is not populated. Using a feed-forward capacitor does not improve the
already low noise and high PSRR of the RAA214023 but is useful to test pin-to-pin compatible competitor LDOs,
which do require feed-forward capacitance to achieve the similar noise and PSRR performance on the same EVB.
1.3 Enabling and Disabling the Device
R1 is a 10kΩpull-up resistor that ties the device EN pin to VIN. To ENABLE the device, remove the JPP_EN
jumper. To DISABLE the device connect JP_EN jumper.
(EQ. 4)
Table 2. Recommended R4and R5Resistor Values for Common Voltage Rails
VOUT(TARGET) (V) R4 (kΩ)R
5 (kΩ)V OUT Error (%)
1 2.55 10.2 0.0
1.2 5.9 11.8 0.0
1.5 10.5 12 0.0
1.8 15 12 0.0
1.9 15.8 11.5 -0.05
2.5 25.5 12 0.0
3 31.6 11.5 -0.06
3.3 75 24 0.0
4.2 51 12 0.0
4.5 74.1 16 0.1
5 105 20 0.0
Error(%)
VOUT ACTUAL
VOUT TARGET –
VOUT ACTUAL
-----------------------------------------------------------------------------------------------100=

R16UZ0020EU0100 Rev.1.00 Page 7
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
1.4 Quick Start Guide
1.4.1 Voltage Set Pins configuration
1. Verify Jumper JP_EN is not in the circuit. The 10kΩpull-up R1 resistor provides a logic HIGH that enables the
LDO.
2. Use the JP_FB jumper to short the SNS pin to OUT.
3. Use a jumper to short the required voltage set pins to ground to obtain the required VOUT.
4. Connect the input supply to VIN and GND_IN.
5. Connect the load to OUT and GND_OUT.
6. Observe the output voltage.
1.4.2 External Resistor Divider
1. Verify Jumper JP_EN is not in the circuit. The 10kΩpull-up R1 resistor provides a logic HIGH that enables the
LDO.
2. Use the JP_FB jumper to connect the top of R4 with OUT.
3. Populate the R4 and R5 feedback resistor divider for the required VOUT.
4. Connect the input supply to VIN and GND_IN.
5. Connect the load to OUT and GND_OUT.
6. Observe the output voltage.
2. Board Design
Figure 5. RTKA214023DE0000BU Evaluation Board

R16UZ0020EU0100 Rev.1.00 Page 8
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
2.1 Layout Guidelines
A good PCB layout is important to achieve expected performance. Consideration should be taken when placing
the components and routing the trace to minimize the ground impedance, and keep the parasitic inductance low.
The input and output capacitors should have a good ground connection and be placed as close to the IC as
possible. The trace for FB must be away from noisy planes and traces.
The large 2.05mm x 2.05mm thermal pad under the 5mm x 5mm RAA214023 is connected to a large ground
copper plane on the bottom layer for effective thermal dissipation.RTKA214023DE0000BU Evaluation Board
2.2 Schematic Drawing
Figure 6. RTKA214023DE0000BU Schematic

R16UZ0020EU0100 Rev.1.00 Page 9
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
2.3 Bill of Materials
2.4 Board Layout
Qty
Reference
Designator Description Mfr
Manufacturer
Part Number
2 C2 CAP-AEC-Q200, SMD, 0805, 10µF, 10V, 10%, X7R,
ROHS
Murata GCJ21BR71A106KE01L
2 C5 CAP, SMD, 1206, 22µF, 10V, 10%, X7R, ROHS Murata GRM31CR71A226KE15L
1 C7 CAP, SMD, 0603, DNP Generic Various
4 C3, C6 CAP, SMD, 0603, 0.1µF, 16V, 10%, X7R, ROHS Generic Various
2 C4 CAP, SMD, 1206, 1µF, 100V, 10%, X7R, ROHS Generic Various
1 OUT, VIN,
GND_IN,
GND_OU
CONN-JACK, STD BANANA, SDRLESS,
NICKEL/BRASS, 0.350inch, ROHS
Keystone 575-8
1 J1 CONN-HEADER, 2x6, BRKAWY-2x36, 2.54mm, ROHS BERG/FCI 67996-272HLF
2 JP_FB CONN-HEADER, 1x3, BREAKAWY 1x36, 2.54mm,
ROHS
BERG/FCI 68000-236HLF
1 JP_EN CONN-HEADER, 1X2, RETENTIVE, 2.54mm,
0.230x 0.120, ROHS
BERG/FCI 69190-202HLF
2 R1, R3 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Generic Various
1 R2 100k, 1%, 1/16W, 0603, Thick Film Chip Resistor Generic Various
1 U1 RAA214023, IC-2A LOW NOISE LDO, 20P, QFN, 5x5,
ROHS
Renesas RAA214023
Figure 7. Top Layer Silk Screen Figure 8. Top Layer

R16UZ0020EU0100 Rev.1.00 Page 10
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
3. Typical Performance Curves
Figure 9. Bottom Layer
Figure 10. Output Noise vs Frequency for Various CSET
(VIN= VOUT+500mV, IOUT = 2A, CSET = 1µF, COUT = 22µF)
Figure 11. Output Noise vs Frequency for various IOUT
(VIN = VOUT+1V, CSET = 1µF, COUT = 22µF)
Figure 12. PSRR vs Frequency (VIN = 4V, VOUT = 3.3V,
CSET= 1µF, COUT = 22μF)
Figure 13. PSRR vs Frequency for various VIN
(VOUT = 3.3V, IOUT = 2A, CSET= 1µF, COUT = 22µF)
0.1
1.0
10.0
100.0
1,000.0
10,000.0
1 10 100 1K 10K 100K 1M 10M
Output Noise (nV/√Hz)
Frequency (Hz)
CSET = 100nF, 6.8μVRMS
CSET = 1μF, 6.5μVRMS
CSET = 10μF, 6.4μVRMS
0.1
1.0
10.0
100.0
1,000.0
10,000.0
100,000.0
1 10 100 1K 10K 100K 1M 10M
Output Noise (nV/√Hz)
Frequency (Hz)
IOUT = 10mA, 6.4μVRMS
IOUT = 100mA, 6.3μVRMS
IOUT = 500mA, 6.2μVRMS
IOUT = 1A, 6.2μVRMS
IOUT = 2A, 6.3μVRMS
0
10
20
30
40
50
60
70
80
90
100
10 100 1K 10K 100K 1M 10M
PSRR (dB)
Frequency (Hz)
10mA
100mA
500mA
1A
1.5A
2A
0
20
40
60
80
100
120
10 100 1K 10K 100K 1M 10M
PSRR (dB)
Frequency (Hz)
4.1V 4.2V
4.3V 4.5V
5V

R16UZ0020EU0100 Rev.1.00 Page 11
Sep 16, 2021
RTKA214023DE0000BU Evaluation Board Manual
4. Ordering Information
5. Revision History
Part Number Description
RTKA214023DE0000BU RAA214023 evaluation board
Rev. Date Description
1.00 Sep 16, 2021 Initial release

Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
Contact Information
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)