Renesas IDT 89HPES24T6 User manual

®
April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.
IDT™89HPES24T6
PCI Express® Switch
User Manual

GENERAL DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
CODE DISCLAIMER
Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU-
LAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with
any applicable laws or regulations.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
PES24T6 User Manual 1 April 10, 2008
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES24T6, a member of IDT’s
PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan-
dard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES24T6 Device Overview,” provides a complete introduction to the performance capabil-
ities of the 89HPES24T6. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Theory of Operation,” provides basic information on the architecture and operation of the
89HPES24T6 chip.
Chapter 4, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.
Chapter 5, “General Purpose I/O,” describes how the 11 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES24T6.
Chapter 7, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES24T6.
Chapter 8, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES24T6.
Chapter 9, “Configuration Registers,” discusses the base addresses, PCI configuration space, and
registers associated with the PES24T6.
Chapter 10, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.

IDT
PES24T6 User Manual 2 April 10, 2008
Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x:y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD if x < y or to
ABCxD, ABC(x-1)D, ABC(x-2)D,... ABCyD if x > y.
Data Units
The following data unit terminology is used in this document.
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
Ter m Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1234
high-to-low
transition low-to-high
transition
single clock cycle

IDT
PES24T6 User Manual 3 April 10, 2008
Notes The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

IDT
PES24T6 User Manual 4 April 10, 2008
Notes
Use of Hypertext
In Chapter 9, Tables 9.2 and 9.3 contain register names and page numbers highlighted in blue under the
Register Definition column. In pdf files, users can jump from this source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Reference Documents
PCI Express Base Specification, Revision 2.0, PCI Special Interest Group.
PCI Power Management Interface Specification, Revision 1.1, PCI Special Interest Group.
PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.
SMBus Specification, Revision 2.0.
Revision History
February 8, 2007: Initial Publication.
March 23, 2007: In Chapter 2, changed port description in Figures 2.1 through 2.4.
May 30, 2007: In Table 1.2, added revision information for ZG silicon. Added Notes to Figure 2.5.
July 18, 2007: In Chapter 9, changed bits [10:9] in HPCFGCTL from RO to RW. In Chapter 2, changed
references to correctly state SRESET field is in BCTL register, not the SWCTL register.
April 10, 2008: In the About section, Table 2, changed SYSCNTL to SWCTL. In Chapter 9, changed
default value for VER field in PCIECAP register from 0x2 to 0x1 and changed 0x0 definition for bit EEPE in
SWPERCTL register from “time-out” to “end-to-end parity error”.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked
RWL Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only
Write Transient WT The zero is always read from a bit/field of this type. Writing of a
one is used to quality the writing of other bits/fields in the same
register.
Zero Zero A zero register or bit must be written with a value of zero and
returns a value of zero when read.
Type Abbreviation Description
Table 2 Register Terminology (Sheet 2 of 2)

Notes
PES24T6 User Manual i April 10, 2008
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................1
Numeric Representations .............................................................................................................. 2
Data Units ......................................................................................................................................2
Register Terminology ..................................................................................................................... 3
Use of Hypertext ............................................................................................................................4
Reference Documents ................................................................................................................... 4
Revision History .............................................................................................................................4
PES24T6 Device Overview
Introduction .....................................................................................................................................1-1
List of Features ...............................................................................................................................1-1
System Diagrams............................................................................................................................1-3
Logic Diagram.................................................................................................................................1-4
System Identification.......................................................................................................................1-5
Vendor ID................................................................................................................................1-5
Device ID ................................................................................................................................1-5
Revision ID .............................................................................................................................1-5
JTAG ID..................................................................................................................................1-5
SSID/SSVID............................................................................................................................1-5
Device Serial Number Enhanced Capability...........................................................................1-5
Pin Description................................................................................................................................1-6
Pin Characteristics........................................................................................................................1-11
Port Configuration.........................................................................................................................1-12
Clocking, Reset, and Initialization
Introduction .....................................................................................................................................2-1
Initialization .....................................................................................................................................2-3
Reset............................................................................................................................................... 2-4
Fundamental Reset ................................................................................................................2-4
Hot Reset................................................................................................................................2-6
Upstream Secondary Bus Reset ............................................................................................2-7
Downstream Secondary Bus Reset........................................................................................2-7
Downstream Port Reset Outputs ....................................................................................................2-8
Power Enable Controlled Reset Output..................................................................................2-8
Power Good Controlled Reset Output ....................................................................................2-9
Theory of Operation
Introduction .....................................................................................................................................3-1
Data Paths ...................................................................................................................................... 3-2
Store-and-Forward vs. Cut-Through Switching and Latency..........................................................3-3
Switch Core.....................................................................................................................................3-3
Transaction Routing................................................................................................................3-4
Transaction Reordering ..........................................................................................................3-5

IDT Table of Contents
PES24T6 User Manual ii April 10, 2008
Notes Scheduling and Port Arbitration..............................................................................................3-6
Peer-to-Peer Transactions.............................................................................................................. 3-8
Bus Locking .................................................................................................................................... 3-9
Port Interrupts ............................................................................................................................... 3-10
Legacy Interrupt Emulation........................................................................................................... 3-11
Standard PCIe Error Detection and Handling...............................................................................3-11
Physical Layer Errors ...........................................................................................................3-11
Data Link Layer Errors..........................................................................................................3-12
Transaction Layer Errors ...................................................................................................... 3-12
Routing Errors ...................................................................................................................... 3-15
Switch Specific Error Detection and Handling ..............................................................................3-16
Switch Time-Outs ................................................................................................................. 3-16
End-to-End Parity Checking .................................................................................................3-16
TLP Processing ............................................................................................................................ 3-17
Port 1 Performance Characteristics..............................................................................................3-18
Link Operation
Introduction ..................................................................................................................................... 4-1
Polarity Inversion ............................................................................................................................ 4-1
Link Width Negotiation.................................................................................................................... 4-1
Lane Reversal................................................................................................................................. 4-1
Link Retraining................................................................................................................................ 4-5
Link Down ....................................................................................................................................... 4-6
Slot Power Limit Support ................................................................................................................ 4-6
Upstream Port ........................................................................................................................ 4-6
Downstream Port.................................................................................................................... 4-6
Link States ...................................................................................................................................... 4-6
Active State Power Management ...................................................................................................4-7
Link Status ...................................................................................................................................... 4-8
General Purpose I/O
Introduction ..................................................................................................................................... 5-1
GPIO Configuration ........................................................................................................................ 5-1
GPIO Pin Configured as an Input ........................................................................................... 5-2
GPIO Pin Configured as an Output ........................................................................................5-2
GPIO Pin Configured as an Alternate Function......................................................................5-2
SMBus Interfaces
Introduction ..................................................................................................................................... 6-1
Master SMBus Interface ................................................................................................................. 6-2
Initialization............................................................................................................................. 6-2
Serial EEPROM...................................................................................................................... 6-2
I/O Expanders.........................................................................................................................6-6
Slave SMBus Interface .................................................................................................................6-12
Initialization........................................................................................................................... 6-12
SMBus Transactions ............................................................................................................ 6-13
Power Management
Introduction ..................................................................................................................................... 7-1
PME Messages............................................................................................................................... 7-2
Power Express Power Management Fence Protocol .....................................................................7-2
Power Budgeting Capability............................................................................................................ 7-3

IDT Table of Contents
PES24T6 User Manual iii April 10, 2008
Notes Hot-Plug and Hot-Swap
Introduction ..................................................................................................................................... 8-1
Hot-Plug I/O Expander ...........................................................................................................8-4
Hot-Plug Interrupts and Wake-up ...........................................................................................8-4
Legacy System Hot-Plug Support ..........................................................................................8-4
Hot-Swap ........................................................................................................................................ 8-6
Configuration Registers
Introduction ..................................................................................................................................... 9-1
Upstream Port (Port 0) ........................................................................................................... 9-3
Downstream Ports (Ports 1 through 5) ...................................................................................9-8
Register Definitions.......................................................................................................................9-12
Type 1 Configuration Header Registers ............................................................................... 9-12
PCI Express Capability Structure .........................................................................................9-21
Power Management Capability Structure ............................................................................. 9-33
Message Signaled Interrupt Capability Structure .................................................................9-35
Subsystem ID and Subsystem Vendor ID ............................................................................ 9-36
Extended Configuration Space Access Registers ................................................................9-37
Advanced Error Reporting (AER) Enhanced Capability .......................................................9-37
Device Serial Number Enhanced Capability.........................................................................9-43
PCI Express Virtual Channel Capability ............................................................................... 9-44
Power Budgeting Enhanced Capability ................................................................................9-49
Switch Control and Status Registers ....................................................................................9-50
Internal Switch Error Control and Status Registers .............................................................. 9-62
JTAG Boundary Scan
Introduction ................................................................................................................................... 10-1
Test Access Point ......................................................................................................................... 10-1
Signal Definitions .......................................................................................................................... 10-1
Boundary Scan Chain................................................................................................................... 10-3
Test Data Register (DR) ............................................................................................................... 10-4
Boundary Scan Registers.....................................................................................................10-4
Instruction Register (IR)................................................................................................................ 10-6
EXTEST................................................................................................................................ 10-7
SAMPLE/PRELOAD............................................................................................................. 10-7
BYPASS ............................................................................................................................... 10-7
CLAMP ................................................................................................................................. 10-8
IDCODE................................................................................................................................ 10-8
VALIDATE ............................................................................................................................ 10-8
RESERVED.......................................................................................................................... 10-8
Usage Considerations .......................................................................................................... 10-9

IDT Table of Contents
PES24T6 User Manual iv April 10, 2008
Notes