Renesas IDT 89HPES24T3G2 User manual

®
February 2012
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©2012 Integrated Device Technology,Inc.
IDT™89HPES24T3G2
PCI Express® Switch
User Manual

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Notes
PES24T3G2 User Manual 1 February 22, 2012
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES24T3G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included inthis manual such as mechanicals, packagepin-outs, and electrical character-
istics can be found in thedata sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES24T3G2 Device Overview,” provides a complete introduction to the performance
capabilities of the 89HPES24T3G2. Included in this chapter is a summary of features for the device as well
as a system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “General Purpose I/O,” describes how the 8 General Purpose I/O (GPIO) pins may be indi-
vidually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 5, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES24T3G2.
Chapter 6, “Power Management,” describes the power management capability structure locatedin the
configuration space of each PCI-PCI bridge in the PES24T3G2.
Chapter 7, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug andhot-swap features in
the PES24T3G2.
Chapter 8, “Configuration Registers,” discusses the base addresses, PCI configuration space, and
registers associated with the PES24T3G2.
Chapter 9, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is representedby a high or low voltage. The term negate ornegation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.

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PES24T3G2 User Manual 2 February 22, 2012
Notes
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to1) transition. Falling edge indicates ahigh-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Term Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1 2 3 4
high-to-low
transition low-to-high
transition
single clock cycle

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PES24T3G2 User Manual 3 February 22, 2012
Notes
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications madeby PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, softwaremust useappropriatemaskstoextract thedefined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

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PES24T3G2 User Manual 4 February 22, 2012
Notes
Use of Hypertext
In Chapter 8, Tables 8.2 and 8.3 containregister names and page numbershighlighted in blue under the
Register Definition column. In pdf files, users can jump from this source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Reference Documents
PCI Express Base Specification, Revision 2.0, PCI Special Interest Group.
PCI Power Management Interface Specification, Revision 1.2, PCI Special Interest Group.
PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.
SMBus Specification, Revision 2.0.
Revision History
September 26, 2007: Initial publication of preliminary user manual.
November 28, 2007: Updated Chapter 1 to reflect some pins are not available in the 19x19 pinout
package.
December 4, 2007: Added hardwired address locations for MSMBADDR and SSMBADDR to Chapters
1 and 5.
January 7, 2008: In Chapter 1, Table 1.9, MSMBADDR[4:1] pins changed to pull-down. In Chapter 5, I/
O Expanders section, added text explaining legacy compatibility with Gen1 PCIe switches. In Chapter 8,
modified the following fields: L0SEL in PCIELCAP has default value of 0x6, ARIS in PCIEDCAP2 is RO,
and ARIFEN in PCIEDCTL2 is RO.
July 15, 2008: In Chapter 8. added Autonomous Link Reliability Management section and 4 registers.
Removed General Purpose Register (0x40C).
August 25, 2008: In Chapter 2, deleted reference to FRSTS pins.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked RWL Software can read the register/bits with this attribute. Writing to register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only.
RWL bits are implicitly “Sitcky.”
Write Transient WT The zero is always read from a bit/field of this type. Writing of a
one is used to quality the writing of other bits/fields in the same
register.
Zero Zero A zero register or bit must be written with a value of zero and
returns a value of zero when read.
Type Abbreviation Description
Table 2 Register Terminology (Sheet 2 of 2)

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PES24T3G2 User Manual 5 February 22, 2012
Notes
November 3, 2008: In Chapter 1, updated Table 1.2 with additional silicon revisions. Updated the
description for the following fields in Chapter 8: LDIS and LRET in the PCIELCTL register, ULD in the
ALRSTS register, and TLW in the PHYLCFG0 register, and changed the last Reserved field in the
PCIEDCTL2 register from 31:6 to 15:6.
May 7, 2009: In Chapter 3, revised the Lane Reversal section.
July 21, 2009: In Chapter 3, revised section Dynamic Link Width Reconfiguration Support in the
PES24T3G2. Also, deleted entire section Software Management of Link Width Upconfiguration and Down-
configuration.
September 15, 2010: In Table 1.9, changed Buffer type for PCI Express from CML to PCIe differential
and changed reference clocks to HCSL
October 26, 2010: In Chapter 2, revised Clocking section on page 1 to remove reference to REFCLKM.
September 23, 2011: Added DDDNC (Disable Downstream Device Number Checking) bit to Switch
Control register in Chapter 8, Configuration Registers.
February 22, 2012: Added paragraph after Table 5.11 to explain use of DWord addresses.

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PES24T3G2 User Manual 6 February 22, 2012
Notes

Notes
PES24T3G2 User Manual i February 22, 2012
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................1
Numeric Representations ..............................................................................................................2
Data Units ......................................................................................................................................2
Register Terminology .....................................................................................................................3
Use of Hypertext ............................................................................................................................4
Reference Documents ...................................................................................................................4
Revision History .............................................................................................................................4
PES24T3G2 Device Overview
Introduction.....................................................................................................................................1-1
Features..........................................................................................................................................1-1
Logic Diagram — PES24T3G2.......................................................................................................1-4
Vendor ID........................................................................................................................................1-4
Device ID........................................................................................................................................1-5
Revision ID......................................................................................................................................1-5
JTAG ID..........................................................................................................................................1-5
SSID/SSVID....................................................................................................................................1-5
Pin Description................................................................................................................................1-6
Pin Characteristics........................................................................................................................1-10
Port Configuration.........................................................................................................................1-11
Clocking, Reset and Initialization
Clocking..........................................................................................................................................2-1
Initialization.....................................................................................................................................2-1
Reset...............................................................................................................................................2-2
Fundamental Reset................................................................................................................2-2
Hot Reset................................................................................................................................2-5
Upstream Secondary Bus Reset............................................................................................2-6
Downstream Secondary Bus Reset........................................................................................2-6
Downstream Port Reset Outputs....................................................................................................2-7
Power Enable Controlled Reset Output..................................................................................2-7
Power Good Controlled Reset Output....................................................................................2-8
Link Operation
Introduction.....................................................................................................................................3-1
Polarity Inversion............................................................................................................................3-1
Lane Reversal.................................................................................................................................3-1
Link Width Negotiation....................................................................................................................3-2
Dynamic Link Width Reconfiguration..............................................................................................3-3
Dynamic Link Width Reconfiguration Support in the PES24T3G2.........................................3-3
Link Speed Negotiation...................................................................................................................3-4
Link Speed Negotiation in the PES24T3G2............................................................................3-4
Software Management of Link Speed.....................................................................................3-5
Link Reliability.................................................................................................................................3-5

IDT Table of Contents
PES24T3G2 User Manual ii February 22, 2012
Notes
Autonomous Link Reliability Management .............................................................................3-6
Link Retraining................................................................................................................................3-7
Link Down.......................................................................................................................................3-8
Slot Power Limit Support................................................................................................................3-8
Upstream Port ........................................................................................................................3-8
Downstream Port....................................................................................................................3-8
Link States......................................................................................................................................3-8
Active State Power Management ...................................................................................................3-9
Link Status....................................................................................................................................3-10
De-emphasis Negotiation .............................................................................................................3-10
Low-Swing Transmitter Voltage Mode..........................................................................................3-10
Crosslink.......................................................................................................................................3-10
General Purpose I/O
Introduction.....................................................................................................................................4-1
GPIO Configuration ........................................................................................................................4-1
GPIO Pin Configured as an Input...........................................................................................4-1
GPIO Pin Configured as an Output........................................................................................4-2
GPIO Pin Configured as an Alternate Function......................................................................4-2
SMBus Interfaces
Introduction.....................................................................................................................................5-1
Master SMBus Interface.................................................................................................................5-2
Initialization.............................................................................................................................5-2
Serial EEPROM......................................................................................................................5-2
I/O Expanders.........................................................................................................................5-7
Slave SMBus Interface.................................................................................................................5-12
Initialization...........................................................................................................................5-13
SMBus Transactions ............................................................................................................5-13
Power Management
Introduction.....................................................................................................................................6-1
PME Messages...............................................................................................................................6-2
PCI-Express Power Management Fence Protocol.........................................................................6-2
Power Budgeting Capability............................................................................................................6-3
Hot-Plug and Hot-Swap
Hot-Plug..........................................................................................................................................7-1
Hot-Plug I/O Expander ...........................................................................................................7-4
Hot-Plug Interrupts and Wake-up...........................................................................................7-4
Legacy System Hot-Plug Support ..........................................................................................7-5
Hot-Swap........................................................................................................................................7-6
Configuration Registers
Configuration Space Organization..................................................................................................8-1
Upstream Port (Port 0) ...........................................................................................................8-2
Downstream Ports..................................................................................................................8-6
Register Definitions.......................................................................................................................8-10
Type 1 Configuration Header Registers...............................................................................8-10
PCI Express Capability Structure.........................................................................................8-20
Power Management Capability Structure.............................................................................8-36
Message Signaled Interrupt Capability Structure.................................................................8-37