Renesas IDT 89HPES48H12G2 User manual

®
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2013 Integrated Device Technology, Inc.
IDT®89HPES48H12G2
PCI Express®Switch
User Manual
April 2013

GENERAL DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
CODE DISCLAIMER
Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU-
LAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with
any applicable laws or regulations.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
PES48H12G2 User Manual 1 April 5, 2013
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES48H12G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES48H12G2 Device Overview,” provides a complete introduction to the performance
capabilities of the 89HPES48H12G2. Included in this chapter is a summary of features for the device as
well as a system block diagram and pin description.
Chapter 2, “Architectural Overview,” provides a high level architectural overview of the PES48H12G2
device.
Chapter 3, “Switch Core,” provides a description of the PES48H12G2 switch core.
Chapter 4, “Clocking,” provides a description of the PES48H12G2 clocking architecture.
Chapter 5, “Reset and Initialization,” describes the PES48H12G2 reset operations and initialization
procedure.
Chapter 6, “Switch Partitions,” describes how the PES48H12G2 supports up to 12 active switch parti-
tions.
Chapter 7, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 8, “SerDes,” describes basic functionality and controllability associated with the Serialiazer-
Deserializer (SerDes) block in PES48H12G2 ports.
Chapter 9, “Theory of Operation,” describes the general operational behavior of the PES48H12G2.
Chapter 10, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features
in the PES48H12G2.
Chapter 11, “Power Management,” describes the power management capability structure located in
the configuration space of each PCI-to-PCI bridge in the PES48H12G2.
Chapter 12, “General Purpose I/O,” describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 13, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES48H12G2.
Chapter 14, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.
Chapter 15, “Register Organization,” describes the organization of all the software visible registers in
the PES48H12G2 and provides the address space for those registers.
Chapter 16, “PCI to PCI Bridge and Proprietary Port Specific Registers,” lists the Type 1 configura-
tion header registers in the PES48H12G2 and provides a description of each bit in those registers.

IDT
PES48H12G2 User Manual 2 April 5, 2013
Notes
Chapter 17, “Switch Control and Status Registers,” lists the switch control and status registers in the
PES48H12G2 and provides a description of each bit in those registers.
Chapter 18, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
1234
high-to-low
transition low-to-high
transition
single clock cycle

IDT
PES48H12G2 User Manual 3 April 5, 2013
Notes
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Ter m Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

IDT
PES48H12G2 User Manual 4 April 5, 2013
Notes
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked
RWL Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only.
Fields with this attribute are implicitly SWSticky (i.e., their value is
preserved across all resets, except switch fundamental reset).
Sticky Sticky Register/bits with this designation take on their initial value as a
result of a switch fundamental reset or partition fundamental reset.
Other resets have no effect.
Switch Sticky SWSticky Register/bits with this designation take on their initial value as a
result of a switch fundamental reset. Other resets have no effect.
Table 2 Register Terminology

IDT
PES48H12G2 User Manual 5 April 5, 2013
Notes
Use of Hypertext
In Chapter 15, Tables 15.4, 15.5 and 15.6 contain register names and page numbers highlighted in blue
under the Register Definition column. In pdf files, users can jump from this source table directly to the regis-
ters by clicking on the register name in the source table. Each register name in the table is linked directly to
the appropriate register in the register section of Chapters 16 and 17. To return to the source table after
having jumped to the register section, click on the same register name (in blue) in the register section.
Reference Documents
[1] PCI Express Base Specification Revision 2.0., December 20, 2006, PCI-SIG.
[2] Multicast Engineering Change Notice to [1]., May 8, 2008, PCI-SIG.
[3] Internal Error Reporting Engineering Change Notice to [1]., April 24, 2008, PCI-SIG.
[4] SMBus Specification, Version 2.0, August 3, 2000, SBS Implementers Forum.
Revision History
October 6, 2008: Initial publication of preliminary user manual.
November 7, 2008: In Chapter 1, Table 1.5, added footnote advising users to connect unused port clock
pins to Vss.
January 12, 2009: On page 3-6, revised Port Arbitration section. On page 6-5, table reference was
changed from 15.5 to 15.4.
January 22, 2009: In Chapter 13, Table 13.16, changed the description for bit USA. In Chapter 16,
PCIEDCTL register, changed the description for bit ERO.
February 9, 2009: In Chapter 1: Table 1.4, for Port 0 Serial Data Receive/Transmit signals, deleted
statement that port 0 is the upstream port; Table 1.8, revised Description for SWMODE[3:0]; Table 1.10,
added “3.3V is preferred” for signal VDDI/O. In Chapter 7, deleted footnote in 2nd paragraph under section
Software Management of Link Speed.
February 18, 2009: In Chapter 7, added a note under L2/L3 Ready in Link States section. In Chapter
16, modified Description for REG and EREG fields in the ECFGADDR register, GADDR field in the
GASAADDR register, DATA field in the GASADATA register, and RSE field in the SECSTS register. In
Chapters 15 and 16, added PHYLSTATE0 (0x540) register.
March 18, 2009: In Table 13.12, the address value was changed from zero to 1 for bits 3 and 5.
April 6, 2009: In Chapter 5, revised text in Partition Hot Reset section and added text in several sub-
sections of Switch Mode Dependent Initialization section. Revised Chapter 6, Switch Partitions, including
new sections Partition State Change, and Partition and Port Configuration. Made changes in register fields
in Chapters 16 and 17 (Bridge and Switch Registers), to conform with device specification and validation.
April 21, 2009: In Table 1.8, deleted reference to pull-down value of 251K ohm resistor for all
PxMERGEN pins. In Footnote 1 for Table 1.11, internal resistor pull-down value was changed to 91K ohms.
In Chapter 17, changed “Bit x in this field corresponds to GPIO pin (x+31)” to “Bit x in this field corresponds
to GPIO pin (x+32)” in the GPIOFUNC1, GPIOCFG1, and GPIOD1 registers. Changed title for Table 13.12.
April 27, 2009: ZB silicon was added to Table 1.3.
May 6, 2009: In Chapter 5, under section Switch Fundamental Reset, deleted bullet referencing
SWFRST bit.
May 14, 2009: In Table 1.11, changed CML to HCSL for PCIe reference clocks.
May 28, 2009: In Chapter 7, revised Crosslink section. In Chapter 8, Tables 8.2, 8.3 and 8.4, changed
column title of TX_EQ_MODE to reflect the register field used to control TX equalization depending on the
operating mode of the link (e.g., TX_EQ_3DBG1). In Chapter 13, revised Introduction section and deleted

IDT
PES48H12G2 User Manual 6 April 5, 2013
Notes
references to LAERR bit in Table 13.2, Table 13.16, and Figure 13.8. In Chapter 15, added section Partial-
Byte Access to Word and DWord Registers. In Chapter 17, added bit BDISCARD to the Switch Control
register and changed bit 26 in the SMBus Status register from LAERR to Reserved.
June 16, 2009: In Chapter 5, revised Table 5.1 and revised text in sections Partition Hot Reset and Port
Mode Change Reset. In Chapter 6, revised text in the following sections: Partition State, Partition State
Change via Other Methods, Port Operating Mode Change via EEPROM Loading, Port Operating Mode
Change via Other Methods, and Dynamic Reconfiguration. Also, deleted section Hot Reset. In Chapter 7,
revised Crosslink section. In Chapter 17, revised the description of the STATE bit in the Switch Partition x
Control register and Switch Partition x Status register, and revised the description of the OMA bit in the
Switch Port x Control register. Also, removed reference to RDETECT bit in Hot-Plug Configuration Control
register.
June 22, 2009: In Table 1.11, System Pins section, changed CLKMODE[1:0] to pull-up and
CLKMODE[2] to pull-down.
July 30, 2009: In Chapter 17, Switch Registers, changed bits 19:18 in the SMBus Control register from
SSMBMODE to Reserved.
August 17, 2009: In Chapter 17, Switch Registers, revised the description for the RXEQZ and RXEQB
fields in the SerDes x Receiver Equalization Lane Control register.
September 22, 2009: Modified Chapter 4, Clocking. In Chapter 8, SerDes, modified Table 8.2 and
added Note before Figure 8.1. Modified section Transaction Layer Error Pollution in Chapter 9, Theory of
Operation. In Chapter 17, Switch Registers, modified description of the LANESEL field in the SxCTL
register and modified description of the RXEQZ and RXEQB fields in the SxRXEQLCTL register.
September 28, 2009: ZC silicon was added to Table 1.3.
November 6, 2009: In Chapter 3, Switch Core, modified text and figures in Operation section. In
Chapter 4, Clocking, modified sections Introduction, Port Clocking Modes, Local Port Clock Mode, and
Table 4.5. Added new section: Spread Spectrum Clocking (SSC) Support. In Chapter 6, Switch Partitions,
added new sections: Partition State Change Latency, Port Operating Mode Change Latency, and Dynamic
Reconfiguration. In Chapter 15, Register Organization, added new section Register Side-Effects. In
Chapter 16, Bridge Registers, modified description for DVADJ bit in the Requester Metering Control
register.
November 11, 2009: In Chapter 8, SerDes, deleted settings greater than 0x0F in Tables 8.7 and 8.8.
December 7, 2009: In Chapter 7, added reference in section Link width Negotiation to the MAXLNK-
WDTH field in the PCI Express Link Capabilities register. In Chapter 15, added new sub-section Limitations
under Register Side-Effects. In Chapter 16, modified Description for the MAXLNKWDTH field in the
PCIELCAP register and added field RCVD_OVRD to the SerDes Configuration register. In Chapter 17,
added field DDDNC to the Switch Control register and modified Description for the BLANK field in the
SMBus Status register.
December 14, 2009: Deleted all references to support for Weighted Round Robin arbitration.
January 21, 2010: Removed Preliminary from title.
February 10, 2010: In Chapter 5, added new Port Merging section. In Table 1.8, added reference to Port
Merging section in PxxMERGEN pin description.
December 8, 2010: In Chapter 4, Table 4.1, changed encoding bits 4 through 7 to Reserved. In Chapter
10, deleted reference to HPxRSTN in Port Reset Outputs section and deleted references to GPIO alternate
functions in Hot-Plug Signals section and Power Good Controlled Reset Output section. In Chapter 13,
corrected ports specified for I/O Expander 10 in Table 13.3. In Chapter 15, revised Figure 15.1. In Chapter
18, deleted PERSTN, GLK1, and SMODE from Table 18.1.
February 2, 2011: In Table 9.13, revised text in Action Taken column for ACS Source Validation. In
Chapter 16, added footnote to STAS bit in PCISTS and SECSTS registers.
February 17, 2011: In Table 13.9, changed Type from Output to Input.

IDT
PES48H12G2 User Manual 7 April 5, 2013
Notes
May 18, 2011: In Chapter 8, section Low-Swing Transmitter Voltage Mode, the reference in the first
paragraph to the LSE bit being in the SerDes Control register was changed to the SerDes Configuration
register.
June 28, 2011: In Chapter 17, added bit 26, TX_SLEW_C, to the SerDes x Transmitter Lane Control 0
register.
July 8, 2011: In Chapter 16, removed table footnotes from PCISTS and SECSTS registers, added
Reserved bits 31:24 to AERUEM and AERUESV registers, and added last sentence to each description in
the PCIESCTLIV register. In Chapter 17, added FEN and FCAPSEL fields to SWPART[x]CTL register and
SWPORT[x]CTL registers, added PFAILOVER and SFAILOVER fields to SWPART[X]STS register and
SWPORT[x]STS register, adjusted bit fields in GPIOCFG1 and GPIOD1 registers, and added SSMBMODE
field to the SMBUSCTL register.
August 31, 2011: In Chapter 2, page 2-1, added bullet to explain behavior of an odd numbered port
when it is merged with its even counterpart. In Chapter 6, added text to Downstream Switch Port section. In
Chapter 7, revised text in section Link Width Negotiation in the Presence of Bad Lanes. In Chapter 8,
revised Table 8.1 and text under this table, revised text in section Programmable De-emphasis Adjustment,
added headings to Figures 8.1 through 8.3, and added paragraph after Figure 8.3. In Chapter 14, revised
text in the Introduction section. In Chapter 16, changed type of MAXLNKSPD field in the PCIELCAP
register from RWL to RO, revised Description for MAXGROUP field in MCCAP register, changed lower to
upper in Description for MCBLKALLH and MCBLKUTH registers. In Chapter 17, deleted references to
Failover capability from several registers.
September 9, 2011: In Chapter 8, added additional reference in last paragraph of section Driver Voltage
Level and Amplitude Boost.
February 7, 2012: In Chapter 13, added footnote for RERR and WERR bits in Table 13.14.
February 23, 2012: Added paragraph after Table 13.14 to explain use of DWord addresses.
January 31, 2013: In Figure 13.8, changed No-ack to Ack between DATALM and DATAUM.
April 5, 2013: In Chapter 17, added USSBRDELAY register.

IDT
PES48H12G2 User Manual 8 April 5, 2013
Notes

Notes
PES48H12G2 User Manual i April 5, 2013
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................2
Numeric Representations .............................................................................................................. 2
Data Units ......................................................................................................................................2
Register Terminology ..................................................................................................................... 3
Use of Hypertext ............................................................................................................................ 5
Reference Documents ................................................................................................................... 5
Revision History .............................................................................................................................5
PES48H12G2 Device Overview
Introduction .....................................................................................................................................1-1
Features..........................................................................................................................................1-1
Logic Diagram.................................................................................................................................1-5
System Identification.......................................................................................................................1-6
Vendor ID................................................................................................................................1-6
Device ID ................................................................................................................................1-6
Revision ID .............................................................................................................................1-6
JTAG ID..................................................................................................................................1-6
SSID/SSVID............................................................................................................................1-6
Device Serial Number Enhanced Capability...........................................................................1-6
Pin Description................................................................................................................................1-7
Pin Characteristics........................................................................................................................1-13
Architectural Overview
Introduction .....................................................................................................................................2-1
Switch Partitioning ..........................................................................................................................2-2
Dynamic Reconfiguration................................................................................................................2-3
Switch Core
Introduction .....................................................................................................................................3-1
Switch Core Architecture ................................................................................................................3-1
Ingress Buffer .........................................................................................................................3-1
Egress Buffer..........................................................................................................................3-2
Crossbar Interconnect ............................................................................................................3-3
Datapaths ...............................................................................................................................3-3
Packet Ordering..............................................................................................................................3-4
Arbitration........................................................................................................................................3-5
Port Arbitration........................................................................................................................3-6
Cut-Through Routing ......................................................................................................................3-6
Request Metering............................................................................................................................3-8
Operation..............................................................................................................................3-10
Completion Size Estimation..................................................................................................3-12
Internal Errors ...............................................................................................................................3-13
Switch Time-Outs .................................................................................................................3-14
Memory SECDED ECC Protection.......................................................................................3-14

IDT Table of Contents
PES48H12G2 User Manual ii April 5, 2013
Notes
End-to-End Data Path Parity Protection ............................................................................... 3-14
Clocking
Introduction ..................................................................................................................................... 4-1
Port Clocking Modes....................................................................................................................... 4-2
Spread Spectrum Clocking (SSC) Support ............................................................................4-2
Global Clocked Mode .............................................................................................................4-4
Local Port Clocked Mode ....................................................................................................... 4-5
Modification of a Port’s Clock Mode .......................................................................................4-6
Reset and Initialization
Introduction ..................................................................................................................................... 5-1
Boot Configuration Vector............................................................................................................... 5-2
Switch Fundamental Reset............................................................................................................. 5-3
Switch Mode Dependent Initialization..................................................................................... 5-6
Port Merging ................................................................................................................................... 5-7
Partition Resets .............................................................................................................................. 5-8
Partition Fundamental Reset .................................................................................................. 5-8
Partition Hot Reset ................................................................................................................. 5-9
Partition Upstream Secondary Bus Reset .............................................................................. 5-9
Partition Downstream Secondary Bus Reset .......................................................................5-10
Port Mode Change Reset ............................................................................................................. 5-10
Switch Partitions
Introduction ..................................................................................................................................... 6-1
Switch Partitions ............................................................................................................................. 6-1
Partition Configuration ............................................................................................................ 6-1
Partition State .........................................................................................................................6-2
Partition State Change ........................................................................................................... 6-3
Switch Ports.................................................................................................................................... 6-4
Switch Port Mode ................................................................................................................... 6-4
Port Operating Mode Change......................................................................................................... 6-7
Common Operating Mode Change Behavior ......................................................................... 6-9
No Action Mode Change Behavior ....................................................................................... 6-14
Reset Mode Change Behavior ............................................................................................. 6-14
Hot Reset Mode Change Behavior.......................................................................................6-15
Partition and Port Configuration.................................................................................................... 6-15
Static Reconfiguration ..........................................................................................................6-15
Dynamic Reconfiguration ..................................................................................................... 6-16
Link Operation
Introduction ..................................................................................................................................... 7-1
Polarity Inversion ............................................................................................................................ 7-1
Lane Reversal................................................................................................................................. 7-1
Link Width Negotiation.................................................................................................................... 7-5
Link Width Negotiation in the Presence of Bad Lanes ...........................................................7-6
Dynamic Link Width Reconfiguration..............................................................................................7-6
Link Speed Negotiation................................................................................................................... 7-6
Link Speed Negotiation in the PES48H12G2 .........................................................................7-7
Software Management of Link Speed ....................................................................................7-8
Link Retraining................................................................................................................................ 7-9
Link Down ..................................................................................................................................... 7-10
Slot Power Limit Support ..............................................................................................................7-10

IDT Table of Contents
PES48H12G2 User Manual iii April 5, 2013
Notes
Upstream Port ...................................................................................................................... 7-10
Downstream Port.................................................................................................................. 7-10
Link States .................................................................................................................................... 7-11
Active State Power Management .................................................................................................7-11
L0s ASPM............................................................................................................................. 7-12
L1 ASPM .............................................................................................................................. 7-12
L1 ASPM Entry Rejection Timer ...................................................................................................7-13
Link Status .................................................................................................................................... 7-14
De-emphasis Negotiation ............................................................................................................. 7-14
Crosslink ....................................................................................................................................... 7-15
Hot Reset Operation on a Crosslink .................................................................................... 7-16
Link Disable Operation on a Crosslink .................................................................................7-16
Gen1 Compatibility Mode ............................................................................................................. 7-16
SerDes
Introduction ..................................................................................................................................... 8-1
SerDes Numbering and Port Association .......................................................................................8-1
SerDes Transmitter Controls .......................................................................................................... 8-1
Driver Voltage Level and Amplitude Boost ............................................................................. 8-1
De-emphasis ..........................................................................................................................8-2
Slew Rate ............................................................................................................................... 8-2
PCI Express Low-Swing Mode ............................................................................................... 8-2
Receiver Equalization ..................................................................................................................... 8-3
Programming of SerDes Controls................................................................................................... 8-3
Programmable Voltage Margining and De-Emphasis.....................................................................8-3
SerDes Transmitter Control Registers....................................................................................8-4
Transmit Margining using the PCI Express Link Control 2 Register............................................. 8-12
Low-Swing Transmitter Voltage Mode..........................................................................................8-13
Receiver Equalization Controls..................................................................................................... 8-14
SerDes Power Management.........................................................................................................8-15
Theory of Operation
Introduction ..................................................................................................................................... 9-1
Transaction Routing........................................................................................................................ 9-1
Interrupts......................................................................................................................................... 9-1
Downstream Port Interrupts....................................................................................................9-2
Legacy Interrupt Emulation..................................................................................................... 9-2
Access Control Services................................................................................................................. 9-3
Error Detection and Handling ......................................................................................................... 9-6
Physical Layer Errors ............................................................................................................. 9-7
Data Link Layer Errors............................................................................................................ 9-7
Transaction Layer Errors ........................................................................................................9-8
Routing Errors ...................................................................................................................... 9-16
Bus Locking .................................................................................................................................. 9-17
Hot-Plug and Hot-Swap
Introduction ................................................................................................................................... 10-1
Hot-Plug Signals ........................................................................................................................... 10-3
Port Reset Outputs .......................................................................................................................10-5
Power Enable Controlled Reset Output................................................................................ 10-5

IDT Table of Contents
PES48H12G2 User Manual iv April 5, 2013
Notes
Power Good Controlled Reset Output .................................................................................. 10-5
Hot-Plug Events............................................................................................................................ 10-6
Legacy System Hot-Plug Support.................................................................................................10-7
Hot-Swap ...................................................................................................................................... 10-8
Power Management
Introduction ................................................................................................................................... 11-1
PME Messages............................................................................................................................. 11-3
PCI Express Power Management Fence Protocol .......................................................................11-3
Upstream Switch Port or Downstream Switch Port Mode ....................................................11-3
Power Budgeting Capability.......................................................................................................... 11-4
General Purpose I/O
Introduction ................................................................................................................................... 12-1
GPIO Configuration ...................................................................................................................... 12-1
Configured as an Input ......................................................................................................... 12-1
Configured as an Output ......................................................................................................12-1
Configured as an Alternate Function .................................................................................... 12-1
SMBus Interfaces
Introduction ................................................................................................................................... 13-1
Master SMBus Interface ............................................................................................................... 13-1
Initialization........................................................................................................................... 13-1
Serial EEPROM.................................................................................................................... 13-1
Initialization from Serial EEPROM........................................................................................ 13-2
Programming the Serial EEPROM .......................................................................................13-5
I/O Expanders.......................................................................................................................13-5
Slave SMBus Interface ............................................................................................................... 13-13
Initialization......................................................................................................................... 13-14
SMBus Transactions .......................................................................................................... 13-14
Multicast
Introduction ................................................................................................................................... 14-1
Addressing and Routing ............................................................................................................... 14-1
Multicast TLP Determination ................................................................................................14-1
Multicast TLP Routing .......................................................................................................... 14-4
Multicast Egress Processing ................................................................................................14-4
Register Organization
Introduction ................................................................................................................................... 15-1
Partial-Byte Access to Word and DWord Registers .............................................................15-2
Register Side-Effects............................................................................................................ 15-2
Address Maps............................................................................................................................... 15-2
PCI-to-PCI Bridge Registers.................................................................................................15-3
Capability Structures ............................................................................................................ 15-3
IDT Proprietary Port Specific Registers.............................................................................. 15-10
Switch Configuration and Status Registers ........................................................................15-12

IDT Table of Contents
PES48H12G2 User Manual v April 5, 2013
Notes
PCI to PCI Bridge and Proprietary Port Specific Registers
Type 1 Configuration Header Registers .......................................................................................16-1
PCI Express Capability Structure ...............................................................................................16-11
Power Management Capability Structure ...................................................................................16-27
Message Signaled Interrupt Capability Structure .......................................................................16-29
Subsystem ID and Subsystem Vendor ID ..................................................................................16-31
Extended Configuration Space Access Registers ......................................................................16-31
Advanced Error Reporting (AER) Enhanced Capability..............................................................16-32
Device Serial Number Enhanced Capability............................................................................... 16-41
PCI Express Virtual Channel Capability ..................................................................................... 16-42
Power Budgeting Enhanced Capability ......................................................................................16-47
ACS Extended Capability ........................................................................................................... 16-49
Multicast Extended Capability..................................................................................................... 16-52
Proprietary Port Specific Registers............................................................................................. 16-57
Port Control and Status Registers ...................................................................................... 16-57
Internal Error Control and Status Registers........................................................................ 16-59
Physical Layer Control and Status Registers .....................................................................16-67
Power Management Control and Status Registers ............................................................16-70
Request Metering ...............................................................................................................16-70
Global Address Space Access Registers ........................................................................... 16-72
Switch Configuration and Status Registers
Switch Control and Status Registers ............................................................................................17-1
Internal Switch Timer .................................................................................................................... 17-4
Switch Partition and Port Registers .............................................................................................. 17-4
Protection...................................................................................................................................... 17-7
SerDes Control and Status Registers...........................................................................................17-8
General Purpose I/O Registers................................................................................................... 17-15
Hot-Plug and SMBus Interface Registers ...................................................................................17-17
JTAG Boundary Scan
Introduction ................................................................................................................................... 18-1
Test Access Point ......................................................................................................................... 18-1
Signal Definitions .......................................................................................................................... 18-1
Boundary Scan Chain................................................................................................................... 18-3
Test Data Register (DR) ............................................................................................................... 18-5
Boundary Scan Registers.....................................................................................................18-5
Instruction Register (IR)................................................................................................................ 18-7
EXTEST................................................................................................................................ 18-7
SAMPLE/PRELOAD............................................................................................................. 18-8
BYPASS ............................................................................................................................... 18-8
CLAMP ................................................................................................................................. 18-8
IDCODE................................................................................................................................ 18-8
VALIDATE ............................................................................................................................ 18-9
EXTEST_TRAIN................................................................................................................... 18-9
EXTEST_PULSE.................................................................................................................. 18-9
RESERVED.......................................................................................................................... 18-9
Usage Considerations .......................................................................................................... 18-9

IDT Table of Contents
PES48H12G2 User Manual vi April 5, 2013
Notes

Notes
PES48H12G2 User Manual vii April 5, 2013
List of Tables
®
Table 1.1 Initial Configuration Register Settings for PES48H12G2.....................................................1-4
Table 1.2 PES48H12G2 Device IDs....................................................................................................1-6
Table 1.3 PES48H12G2 Revision ID...................................................................................................1-6
Table 1.4 PCI Express Interface Pins..................................................................................................1-7
Table 1.5 Reference Clock Pins ..........................................................................................................1-8
Table 1.6 SMBus Interface Pins ..........................................................................................................1-8
Table 1.7 General Purpose I/O Pins....................................................................................................1-9
Table 1.8 System Pins.......................................................................................................................1-10
Table 1.9 Test Pins............................................................................................................................1-11
Table 1.10 Power, Ground, and SerDes Resistor Pins .......................................................................1-12
Table 1.11 Pin Characteristics.............................................................................................................1-13
Table 3.1 IFB Buffer Sizes...................................................................................................................3-1
Table 3.2 EFB Buffer Sizes .................................................................................................................3-2
Table 3.3 Replay Buffer Storage Limit.................................................................................................3-3
Table 3.4 Packet Ordering Rules in the PES48H12G2 .......................................................................3-5
Table 3.5 Conditions for Cut-Through Transfers .................................................................................3-7
Table 3.6 Request Metering Decrement Value..................................................................................3-11
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State............................................4-2
Table 4.2 GCLK and PxCLK Frequencies when PxCLK has SSC......................................................4-3
Table 4.3 Port Clocking Mode Requirements......................................................................................4-3
Table 4.4 Valid PES48H12G2 System Clocking Configurations .........................................................4-3
Table 4.5 Clock Frequency Limitations When Modifying a Port’s Clock Mode....................................4-6
Table 5.1 PES48H12G2 Reset Precedence........................................................................................5-1
Table 5.2 Boot Configuration Vector Signals.......................................................................................5-2
Table 5.3 Switch Mode Dependent Register Initialization ...................................................................5-6
Table 7.1 Crosslink Port Groups........................................................................................................7-15
Table 7.2 Gen1 Compatibility Mode: bits cleared in training sets......................................................7-17
Table 8.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers............8-5
Table 8.2 SerDes Transmit Driver Settings in Gen1 Mode..................................................................8-6
Table 8.3 SerDes Transmit Driver Settings in Gen2 Mode with -3.5dB de-emphasis.........................8-7
Table 8.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis.........................8-8
Table 8.5 Transmitter Slew Rate Settings .........................................................................................8-11
Table 8.6 PCI Express Transmit Margining Levels supported by the PES48H12G2 ........................ 8-12
Table 8.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed .................................. 8-13
Table 8.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed ..................................8-14
Table 9.1 Switch Routing Methods......................................................................................................9-1
Table 9.2 Downstream Port Interrupts.................................................................................................9-2
Table 9.3 Downstream to Upstream Port Interrupt Routing Based on Device Number.......................9-3
Table 9.4 Prioritization of ACS Checks for Request TLPs...................................................................9-5
Table 9.5 Prioritization of ACS Checks for Completion TLPs..............................................................9-6
Table 9.6 TLP Types Affected by ACS Checks...................................................................................9-6
Table 9.7 Physical Layer Errors...........................................................................................................9-7
Table 9.8 Data Link Layer Errors.........................................................................................................9-7
Table 9.9 Transaction Layer Errors associated with the PCI-to-PCI Bridge Function.........................9-9
Table 9.10 Conditions Handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge Function.9-11
Table 9.11 Ingress TLP Formation Checks Associated with the PCI-to-PCI Bridge Function.............9-11
Table 9.12 Egress Malformed TLP Error Checks................................................................................9-12
Table 9.13 ACS Violations for Ports Operating in Downstream Switch Port Mode ............................. 9-13
Table 9.14 Prioritization of Transaction Layer Errors ..........................................................................9-14

IDT List of Tables
PES48H12G2 User Manual viii April 5, 2013
Notes
Table 10.1 Port Hot Plug Signals ........................................................................................................ 10-3
Table 10.2 Negated Value of Unused Hot-Plug Output Signals.......................................................... 10-4
Table 11.1 PES48H12G2 Power Management State Transition Diagram ..........................................11-2
Table 12.1 GPIO Pin Configuration ..................................................................................................... 12-1
Table 12.2 General Purpose I/O Pin Alternate Function ..................................................................... 12-2
Table 12.3 GPIO Alternate Function Pins ........................................................................................... 12-2
Table 13.1 PES48H12G2 Compatible Serial EEPROMs ....................................................................13-2
Table 13.2 Serial EEPROM Initialization Errors ..................................................................................13-5
Table 13.3 I/O Expander Function Allocation ...................................................................................... 13-6
Table 13.4 I/O Expander Default Output Signal Value ........................................................................ 13-7
Table 13.5 Pin Mapping for I/O Expanders 0 through 7 ......................................................................13-9
Table 13.6 Pin Mapping I/O Expander 8 ...........................................................................................13-10
Table 13.7 Pin Mapping I/O Expander 9 ...........................................................................................13-10
Table 13.8 Pin Mapping I/O Expander 10 .........................................................................................13-11
Table 13.9 I/O Expander 11 - Partition Fundamental Reset Inputs................................................... 13-12
Table 13.10 I/O Expander 12 - Link Up Status....................................................................................13-12
Table 13.11 I/O Expander 13 - Link Activity Status ............................................................................. 13-13
Table 13.12 Slave SMBus Address..................................................................................................... 13-14
Table 13.13 Slave SMBus Command Code Fields ............................................................................. 13-15
Table 13.14 CSR Register Read or Write Operation Byte Sequence .................................................13-15
Table 13.15 CSR Register Read or Write CMD Field Description.......................................................13-16
Table 13.16 Serial EEPROM Read or Write Operation Byte Sequence .............................................13-17
Table 13.17 Serial EEPROM Read or Write CMD Field Description...................................................13-18
Table 15.1 Global Address Space Organization .................................................................................15-1
Table 15.2 Default PCI Capability List Linkage ................................................................................... 15-4
Table 15.3 Default PCI Express Capability List Linkage .....................................................................15-4
Table 15.4 PCI-to-PCI Bridge Configuration Space Registers ............................................................ 15-6
Table 15.5 Proprietary Port Specific Registers..................................................................................15-11
Table 15.6 Switch Configuration and Status .....................................................................................15-13
Table 18.1 JTAG Pin Descriptions ...................................................................................................... 18-2
Table 18.2 Boundary Scan Chain........................................................................................................ 18-3
Table 18.3 Instructions Supported by the JTAG Boundary Scan ........................................................18-7
Table 18.4 System Controller Device Identification Register ..............................................................18-8

Notes
PES48H12G2 User Manual ix April 5, 2013
List of Figures
®
Figure 1.1 PES48H12G2 Block Diagram ............................................................................................1-4
Figure 1.2 PES48H12G2 Logic Diagram ............................................................................................1-5
Figure 2.1 PES48H12G2 Block Diagram ............................................................................................2-1
Figure 2.2 Transparent PCIe Switch ...................................................................................................2-2
Figure 2.3 Partitionable PCI Express Switch ......................................................................................2-2
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers .................................................3-3
Figure 3.2 Architectural Model of Arbitration .......................................................................................3-6
Figure 3.3 PCIe Switch Static Rate Mismatch ....................................................................................3-9
Figure 3.4 PCIe Switch Static Rate Mismatch ....................................................................................3-9
Figure 3.5 Request Metering Count and Initial Value Loaded ..........................................................3-10
Figure 3.6 Decrement Value and Decrement Value Adjustment .......................................................3-11
Figure 3.7 Request Metering Counter Decrement Operation ............................................................3-12
Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation ...............................3-12
Figure 4.1 Logical Representation of the PES48H12G2 Clocking Architecture ..................................4-1
Figure 4.2 Clocking Connection for a Port in Global Clocked Mode, with a Common Clocked
Configuration ......................................................................................................................4-4
Figure 4.3 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked
Configuration ......................................................................................................................4-5
Figure 4.4 Clocking Connection for a Port in Local Port Clocked Mode, in a Common Clocked
Configuration ......................................................................................................................4-5
Figure 4.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common
Clocked Configuration ........................................................................................................4-6
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................5-5
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................5-5
Figure 6.1 Allowable Partition State Transitions .................................................................................6-2
Figure 7.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 ..........................................7-2
Figure 7.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 ..........................................7-2
Figure 7.3 Merged Port Lane Reversal for Maximum Link Width of x2 ...............................................7-3
Figure 7.4 Merged Port Lane Reversal for Maximum Link Width of x4 ...............................................7-4
Figure 7.5 Merged Port Lane Reversal for Maximum Link Width of x8 ...............................................7-5
Figure 7.6 PES48H12G2 ASPM Link Sate Transitions .....................................................................7-11
Figure 8.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................8-10
Figure 8.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................8-10
Figure 8.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB
Nominal de-emphasis ......................................................................................................8-11
Figure 9.1 ACS Source Validation Example .......................................................................................9-4
Figure 9.2 ACS Peer-to-Peer Request Re-direct at a Downstream Port ............................................9-4
Figure 9.3 ACS Upstream Forwarding Example .................................................................................9-5
Figure 9.4 Error Checking and Logging on a Received TLP .............................................................9-15
Figure 10.1 Hot-Plug on Switch Downstream Slots Application ..........................................................10-1
Figure 10.2 Hot-Plug with Switch on Add-In Card Application ............................................................10-2
Figure 10.3 Hot-Plug with Carrier Card Application ............................................................................10-2
Figure 10.4 Power Enable Controlled Reset Output Mode Operation ................................................10-5
Figure 10.5 Power Good Controlled Reset Output Mode Operation ...................................................10-6

IDT List of Figures
PES48H12G2 User Manual x April 5, 2013
Notes
Figure 10.6 PES48H12G2 Hot-Plug Event Signalling .........................................................................10-8
Figure 11.1 PES48H12G2 Power Management State Transition Diagram ........................................11-2
Figure 13.1 Split SMBus Interface Configuration ................................................................................13-1
Figure 13.2 Single Double Word Initialization Sequence Format ........................................................13-3
Figure 13.3 Sequential Double Word Initialization Sequence Format .................................................13-3
Figure 13.4 Configuration Done Sequence Format ............................................................................13-4
Figure 13.5 Slave SMBus Command Code Format ..........................................................................13-14
Figure 13.6 CSR Register Read or Write CMD Field Format ...........................................................13-16
Figure 13.7 Serial EEPROM Read or Write CMD Field Format ........................................................13-18
Figure 13.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled 13-18
Figure 13.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled .........................................................................................................................13-19
Figure 13.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled .........13-19
Figure 13.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled .....13-19
Figure 13.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ......13-19
Figure 13.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ..13-20
Figure 14.1 Multicast Group Address Ranges ....................................................................................14-2
Figure 14.2 Multicast Group Address Region Determination ..............................................................14-3
Figure 15.1 PCI-to-PCI Bridge Configuration Space Organization .....................................................15-5
Figure 15.2 Proprietary Port Specific Register Organization ............................................................15-10
Figure 15.3 Switch Configuration and Status Space Organization ...................................................15-12
Figure 18.1 Diagram of the JTAG Logic ..............................................................................................18-1
Figure 18.2 State Diagram of the TAP Controller ...............................................................................18-2
Figure 18.3 Diagram of Observe-only Input Cell .................................................................................18-5
Figure 18.4 Diagram of Output Cell ....................................................................................................18-6
Figure 18.5 Diagram of Bidirectional Cell ............................................................................................18-6
Figure 18.6 Device ID Register Format ...............................................................................................18-8