Samsung SGH-D730 User manual

MITs TELEPHONE
SGH-D730
MITs TELEPHONE CONTENTS
1. Specification
2. Flow Chart of Troubleshooting
3. Exploded Views and Parts List
4. Electrical Parts List
5. PCB Diagrams
6. Block Diagrams

1. SGH-D730 Specification
1-2
1-1. GSM General Specification
GSM900
Phase 1
EGSM 900
Phase 2
DCS1800
Phase 1 PCS1900
Freq. Band[MHz]
Uplink/Downlink
890~915
935~960
880~915
925~960
1710~1785
1805~1880
1850~1910
1930~1990
ARFCN range 1~124 0~124 &
975~1023 512~885 512~810
Tx/Rx spacing 45MHz 45MHz 95MHz 80MHz
Mod. Bit rate/
Bit Period
270.833kbps
3.692us
270.833kbps
3.692us
270.833kbps
3.692us
270.833kbps
3.692us
Time Slot
Period/Frame
Period
576.9us
4.615ms
576.9us
4.615ms
576.9us
4.615ms
576.9us
4.615ms
Modulation 0.3GMSK 0.3GMSK 0.3GMSK 0.3GMSK
MS Power 33dBm~13dBm 33dBm~5dBm 30dBm~0dBm 30dBm~0dBm
Power Class 5pcl ~ 15pcl 5pcl ~ 19pcl 0pcl ~ 15pcl 0pcl ~ 15pcl
Sensitivity -102dBm -102dBm -100dBm -100dBm
TDMA Mux 8 8 8 8
Cell Radius 35Km 35Km 2Km -

SGH-D730 Speclflcation
1-2
1-2. GSM Tx Power Class
TX Power
control level GSM900
5 33±2 dBm
6 31±2 dBm
7 29±2 dBm
8 27±2 dBm
9 25±2 dBm
10 23±2 dBm
11 21±2 dBm
12 19±2 dBm
13 17±2 dBm
14 15±2 dBm
15 13±2 dBm
16 11±3 dBm
17 9±3dBm
18 7±3 dBm
19 5±3 dBm
TX Power
control level DCS1800
0 30±3 dBm
1 28±3 dBm
2 26±3 dBm
3 24±3 dBm
4 22±3 dBm
5 20±3 dBm
6 18±3 dBm
7 16±3 dBm
8 14±3 dBm
9 12±4 dBm
10 10±4 dBm
11 8±4dBm
12 6±4 dBm
13 4±4 dBm
14 2±5 dBm
15 0±5 dBm
TX Power
control level PCS1900
0 30±3 dBm
1 28±3 dBm
2 26±3 dBm
3 24±3 dBm
4 22±3 dBm
5 20±3 dBm
6 18±3 dBm
7 16±3 dBm
8 14±3 dBm
9 12±4 dBm
10 10±4 dBm
11 8±4dBm
12 6±4 dBm
13 4±4 dBm
14 2±5 dBm
15 0±5 dBm

SAMSUNG Proprietary-Contents may change without notice
2. SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-1
This Document can not be used without Samsung's authorization
2-1.Baseband
2-1-1. Power ON
Check the current
consumtion more than
100mA
Check the Vbat(battery+O)
Voltagemorethan3.3V
Downloader again
NO
Charge the Battery
NO
Check CN304,C387
NO
YES
YES
YES
YES
'Power On' does not work
Check the pin
4 of Q303 is more
than 3.3V
Check the pin
1 of Q303 is more
than 3.3V
U100 pin A19
=3.0V
YES
Check Q303,Q305 and D302
NO
Check U308,U100 and C109
NO
U100 pin B14
=1.8V
YES
Check U308,U100 and C106
NO
U100 pin A15
=1.6V
YES
Check U304,U100 and C101
NO
'Power On' does not work
END
Check the clock signal
at pin1 of OSC100
Freq=12MHz
Check the clock generation circuit
(OSC100)
NO
YES
①
②
③
④
⑤
⑥

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-2
This Document can not be used without Samsung's authorization

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-3
This Document can not be used without Samsung's authorization
1
3
2
Q101
R129
C143
R111
VDD_30D
R109
TP103
R121
VDD_30DVDD_30D
R144
R123
R113
VDD_30D
VDD_18D
C102
1
3
2
C120
Q102
C141
VDD_18D
R122
R130
R165
VDD_30D
C103
C115
R120
VDD_15D
C140
VDD_30D
1
0
1
C
S
O
2
1
C142
TP101
C101
VDD_30D
VDD_30D
VDD_30D
C145
OSC100
GND1
2
GND2
4
1
HOT
HOT
3
R100
VDD_30D
VDD_15D
C144
R164
R108
TP104
R114
R166
R147
R168
R110
C100
R148
R139
R112
VDD_18D
VDD_18D
VDD_30D
33PFC715
R107
R126
C104
7
S
S
V
0
2
K
1
2
R8
S
S
V
9
S
S
V
0
2
W
W13
WA-KEUP_INT
WIRE_SCLK
V19
WIRE_SDI
U18
W21 WIRE_SDO
N14 Z_STATE1
Z_STATE2
P15
Z_STATE3
W16
5
1
S
S
V
2
U
1
N6
1
S
S
V
7
1
S
S
V
2
K
1
G8
1
S
S
V
9
1
S
S
V
1
B
7
B2
S
S
V
3
S
S
V
3
1
A
6
1
B4
S
S
V
5
S
S
V
1
2
A
0
2
F6
S
S
V
VDD_2
Y20
Y9 VDD_3
VDD_4
M2
W12 VDD_RTC
L1 VPP
1
S
S
V
5
B
1
2
A
A0
1
S
S
V
1
1
S
S
V
3
1
Y
7
A
A2
1
S
S
V
3
1
S
S
V
3
Y
1
A
A4
1
S
S
V
VDDSHV4_3 A7
A5
VDDSHV4_4 R1
VDDSHV5_1
VDDSHV5_2 H2
C2
VDDSHV5_3
VDDSHV6 AA11
Y16
VDDSHV7
VDDSHV8 L21
U21
VDDSHV9
VDDSHV_RTC V12
A15 VDD_1
VDD3_2
B20
J21 VDD3_3
VDD3_4
R20
VDDA
Y21 VDDSHV1_1 A19 E21
VDDSHV1_2
VDDSHV2 AA2
Y7
VDDSHV3
VDDSHV4_1 B14
B10
VDDSHV4_2
TMS
V17
Y15 UARTS_CLKIO
UARTS_CLKREQ
W15
R8
USB_DM
USB_DP P9
W4
USB_PUEN
AA3 VDD1
VDD2_1
A3
A9 VDD2_2
VDD2_3
E2
B13 VDD3_1
SDATA_5
C7
SDATA_6
C4
SDATA_7
D8
C10 SDATA_8
SDATA_9
D14
SDCLK
C9 SDCLKX
D9
SDCLK_EN
H12
W18 TCK
TDI
Y19
AA19 TDO
D6
SDATA_1
C6
SDATA_10
D11
SDATA_11
C13
SDATA_12
C11
SDATA_13
D13
SDATA_14
D12
SDATA_15
C12
C5 SDATA_2
SDATA_3
D7
SDATA_4
D5
SADD_4
G10
SADD_5
B9
SADD_6
G12
SADD_7
G11
SADD_8
G9
SADD_9
B12
SBANK_0
B3
C3 SBANK_1
SCL
T18
V20 SDA
SDATA_0
RX1
V14
R9 RX2
RX3
L14
SADD_0
A2
SADD_1
B2
B8 SADD_10
SADD_11
H10
SADD_12
H9
H11 SADD_13
SADD_2
B6
SADD_3
A1
H7
NSWE
H8
NTRST
Y18
ON_NOFF Y12
OSC1_IN Y2
W3
OSC1_OUT
3
1
vN
I
_
K
2
3
C
S
O
T
U
O
_
K
2
3
C
S
O
3
1
A
A
P12
RE-SET_MODE
5
eD
E
V
R
E
S
E
R
Y17 RTCK
NFCS_3 N8
NFOE U4
W1
NFRP
NFWE W2
V4
NFWP
NRE-SET_OUT
AA20
NRESPWRON R12
NSCAS
B4
NSDQML
C8
NSDQMU
D10
NSRAS
NC1 1
2
NC2
V16 NEMU0
NEMU1
W17
NFADV L4
L3
NFBE_0
NFBE_1 M8
NFCS_1 M3
NFCS_1B Y1
M4
NFCS_2
P3
NFCS_2B
Y10
AA9
MCSI2_DIN
MCSI2_DOUT W9
V9
MCSI2_SYNC
V11
MMC_CLK P11
MMC_CMD
MMC_DAT0 R11
MMC_DAT1 V10
W10
MMC_DAT2
MMC_DAT3 W11
MPU_NRE-SET
U20
MCBSP2_CLKR V7
Y6
MCBSP2_CLKX
MCBSP2_DIN P10
MCBSP2_DOUT AA5
W6
MCBSP2_RSYNC
W7
MCBSP2_XSYNC
P14 MCSI1_BCLK
V15 MCSI1_DIN
MCSI1_DOUT
W14
MCSI1_SYNC
AA17
MCSI2_CLK
LCD_PIX-EL_6
B19
C18 LCD_PIX-EL_7
LCD_PIX-EL_8
D17 LCD_PIX-EL_9
D16
B18 LCD_VSYNC
R
E
T
L
I
F
_
O
D
L
1
j
MCBSP1_BCLK
G21
G20 MCBSP1_CLKS
H20 MCBSP1_DIN
MCBSP1_DOUT
H18
H15 MCBSP1_SYNC
LCD_PIX-EL_10
C17 LCD_PIX-EL_11
B17 LCD_PIX-EL_12
G13 LCD_PIX-EL_13
A17 LCD_PIX-EL_14
C16 LCD_PIX-EL_15
D15
LCD_PIX-EL_2
C19
G14 LCD_PIX-EL_3
LCD_PIX-EL_4
H13
A20 LCD_PIX-EL_5
KBC_5
G19
G18 KBR_0
KBR_1
F19
H14 KBR_2
KBR_3
E20
E19 KBR_4
B15 LCD_AC
C20 LCD_HSYNC
LCD_PCLK
C15
LCD_PIX-EL_0
D18
B21 LCD_PIX-EL_1
GPIO_4 P20
GPIO_6 P19
M7
GPIO_62
GPIO_7 M15
GPIO_8 Y8
W8
GPIO_9
KBC_0
F18
D20 KBC_1
KBC_2
D19
E18 KBC_3
KBC_4
C21
T2
FRDY V2
GPIO_0 R18
GPIO_1 R19
GPIO_11 N20
GPIO_12 N18
GPIO_13 N19
GPIO_14 N21
M20
GPIO_15
GPIO_2 M14
P18
GPIO_3
FDATA_13 U3
T4
FDATA_14
V3
FDATA_15
FDATA_2 N7
FDATA_3 P2
P4
FDATA_4
FDATA_5 P7
R2
FDATA_6
FDATA_7 R3
R4
FDATA_8
FDATA_9
FADD_5
FADD_6 F4
E3
FADD_7
FADD_8 J7
FADD_9 F3
N3
FCLK
FDATA_0 N4
N2
FDATA_1
T3
FDATA_10
FDATA_11 P8
U1
FDATA_12
J4
J3
FADD_19
FADD_2 D3
F2
FADD_20
FADD_21 L8
K4
FADD_22
FADD_23 K3
L7
FADD_24
E1
FADD_25
C1
FADD_3
FADD_4 E4
D2
DQS_L
D4
J8
FADD_1
FADD_10 G4
G3
FADD_11
FADD_12 G2
K8
FADD_13
FADD_14 H4
H3
FADD_15
FADD_16 K7
J2
FADD_17
FADD_18
CAM_VS L18
CDD_DLL
A11
P13 CLK32K_IN
R13 CLK32K_OUT
COM_MCLK_OUT V5
COM_MCLK_REQ R10
V18 CONF
CS_SDRAM
G8
R14 CTS1
CTS2 Y5
DQS_H
C14
K14
CAM_D_2 K15
CAM_D_3 K19
K18
CAM_D_4
CAM_D_5 J14
CAM_D_6 J19
CAM_D_7 J18
CAM_EXCLK H19
CAM_HS L15
CAM_LCLK J15
CAM_RSTZ M19
M18
0_STATE5
U19 ARMIO_1
N15 ARMIO_2
V8 ARMIO_3
ARMIO_4
T19
T20 ARMIO_5
ARM_BOOT
J20
Y4
BDCLK2
W19 BVLZ
CAM_D_0 L19
CAM_D_1
U100
0_STATE1 AA15
Y14
0_STATE2 W5
0_STATE3
0_STATE4 V6
OPEN_SENSE
CAM_MCLK
CD_CLK_12M
UDQM
LDQM
SCLK
BP_VF
DEBUG_RXD
PH_PWR_ON
PDA_ACTIVE
PDA_WAKEUP
PH_WAKEUP
CLK32K_OMAP
BT_CTS
CAM_EN
BT_REQ
JIG_ON
KB_LED_EN
FA(14)
FA(16)
FA(17)
FA(18)
FA(19)
FA(20)
FA(21)
FA(22)
FA(23)
FA(24)
FA(25)
FA(13)
AP_AT_nDSR
LCD_BL_EN
FD(13)
FD(14)
FD(15)
FA(1:25)
FA(1)
FA(2)
FA(3)
FA(4)
FA(5)
FA(7)
FA(9)
FA(10)
FA(12)
SA(3)
SA(4)
SA(5)
SA(6)
SA(7)
SA(8)
SA(9)
SA(10)
SA(11)
SA(12)
SA(0)
FD(8)
FD(9)
FD(10)
FD(11)
FD(12)
SD(0)
CAM_SCL
FA(6)
FA(8)
FA(11)
FA(15)
nBAT_LOW
NFWE
NFOE
FD(0:15)
OMAP_RTCK
OMAP_TRST
SA(0:12)
SA(1)
SA(2)
IIS_LRCK
IIS_SDO
IIS_SDI
AP_AT_nDTR
CODEC_CSB
LCD_SCL
OMAP_EMU0
OMAP_EMU1
nSRAS
USB_DP
USB_D
M
LCD_VDD_EN
LCD_B2
LCD_B1
LCD_B0
LCD_HSYNC
KB_nSCAN(5)
KB_nSCAN(4)
KB_nSCAN(3)
KB_nSCAN(2)
KB_nSCAN(1)
KB_nSCAN(0)
KB_nIN(4)
KB_nIN(3)
KB_nIN(2)
KB_nIN(1)
KB_nIN(0)
IIS_SCLK
LCD_ENABLE
LCD_DOTCLK
LCD_VSYNC
LCD_R4
LCD_R3
LCD_R2
LCD_R1
LCD_R0
LCD_G5
LCD_G4
LCD_G3
LCD_G2
LCD_G1
LCD_G0
LCD_B4
LCD_B3
SD(2)
SD(3)
SD(4)
SD(5)
SD(6)
SD(7)
SD(8)
SD(9)
SD(10)
SD(11)
SD(12)
SD(13)
SD(14)
SD(15)
BT_RXD
AP_AT_RXD
OMAP_TCK
OMAP_TDI
OMAP_TDO
OMAP_TMS
PUEN
VDD_SHV2
CODEC_SCK
CODEC_SDO
CODEC_SDI
LCD_CS
VIB_EN
SD(0:15)
SD(1)
MMC_SCLK
MMC_CMD
MMC_DAT
SW_RST_INT
FLASH_EN
NFCS_3
OHP_nRESET
nSCAS
nSWE
SBANK_0
SBANK_1
CAM_SDA
SCKE
FD(4)
FD(5)
FD(6)
FD(7)
LCD_SDI
PH_OFF_nRDY
JACK_nSEND_END
FLIP_SENSE
ON_SW_SENSE
MMC_nInserted
USB_nINSERTED
JACK_SENSE
LCD_RESET
BT_nSHDN
PWR_HOLD
Y4
Y5
Y6
Y7
CAM_HSYNC
CAM_PCLK
CAM_RESET
CAM_VSYNC
nCS_SDRAM0
AP_AT_nCTS
FD(0)
FD(1)
FD(2)
FD(3)
PH_ACTIVE
BT_RTS
BT_TXD
AP_AT_nRTS
AP_AT_TXD
DEBUG_TXD
Y0
Y1
Y2
Y3

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-4
This Document can not be used without Samsung's authorization
C316
3
1
2
D302
U305
EMD6
2
5
6
3
1
4
V_IN
R332
VDD_30D
D301
3
1
2
R324
VRTC G
3
4S
Q303 1256
9
0
3
R
C308
C315
VBAT
C309
R336
Q306
13
2
Q305
1
3
2
RTC_nALARM ON_SW_SENSE
JIG_ON
PWR_ON_AP
PWR_HOLD
7
1
6
C
R613
8
1
6
C
VDD_15D
L600
6
3
11
GND
MODE/SYNC
8
4
NC
5
NC
9
PGND
SW
10
VIN
1
VOUT
V_IN
U604
7
AGND
2
AVIN
EN

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-5
This Document can not be used without Samsung's authorization
2-1-2. Initial
U400 pin C16
=1.8V
Check the
pin F4 of
U400 is "High"
Check U301
NO
Check the U400
NO
YES
YES
Initial Failure
U400 pin B14
=3.0V Check the U400
NO
YES
Check and resolder LCD connector CN303
if there is solder bridge between the pins
END
YES
YES
Check the U400
NO
YES
Check the clock
signals at
pin3 and pin5 of
OSC400
Freq=13MHz
Check the clock generation circuit
(OSC400)
NO
Check the pin C12
of U500 is "High" Check U500
NO
YES
Check the
pin 2 of
U301 is "High"
①
②
③
④
⑤
⑥

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-6
This Document can not be used without Samsung's authorization
①
②③④
⑤
⑥

SAMSUNG Proprietary-Contents may change without notice
SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams
2-7
This Document can not be used without Samsung's authorization
OSC401
VRTC
R413
DSP_TDI
TP405
TP403
R416
VCCD
TP407
VDD_18D
R414
VCCB
R410
C407
R441
R440
VDD_30D
C422
DSP_TMS
D12
0
1
F
F
E
R
V
X
C411
XPA6/BE1N
XPA7/IRQ1
M9
T5 XPA8/IRQ2
XPA9/IRQ3
P2
1
M
W
P
X
5
R
XRTCALARM_N
E8
K
L
C
_
0
M
S
X
0
1
N
2
1
UA
T
A
D
_
0
M
S
X
XTIC_MODE
N
0
S
C
_
2
3
A
P
X
7
1
NA
Q
E
R
_
T
_
3
3
A
P
X
B
Q
E
R
_
T
_
4
3
A
P
X
7
1
M
2
2
A
_
5
3
A
P
X3
1
L
5
1
N
N
5
S
C
_
3
2
A
_
6
3
A
P
X
XPA3/CS4N
N14
XPA4/OEN
P16
XPA5/WAITN
P15
T15
0
M
O
_
5
2
A
P
X
1
M
O
_
6
2
A
P
X
2
G
4
GK
L
C
_
1
M
S
_
7
2
A
P
X
0
M
O
I
_
8
2
A
P
X
5
G
1
M
O
I
_
9
2
A
P
X
1
F
M11 XPA2/CS3N
3
F0
M
I
_
0
3
A
P
X
1
M
I
_
1
3
A
P
X
1
E
4
1
H
I
S
O
M
_
P
C
/
9
1
A
P
X
2
L
M14 XPA1/CS2N
1
LO
S
I
M
_
P
C
/
0
2
A
P
X
4
KK
C
S
_
P
C
/
1
2
A
P
X
N
S
S
/
2
2
A
P
X
6
J
6
H2
M
W
P
/
3
2
A
P
X
3
M
W
P
/
4
2
A
P
X
5
H
3
M
X
R
A
D
R
I
/
1
1
A
P
X
5
K
1
NX
T
A
D
R
I
/
2
1
A
P
X
1
X
T
_
3
1
A
P
X
6
G
3
G1
X
R
_
4
1
A
P
X
0
X
T
/
5
1
A
P
X
4
H
3
L0
X
R
/
6
1
A
P
X
0
Q
R
D
_
7
1
A
P
X
4
E
K
C
A
_
T
_
8
1
A
P
X
3
1
P
7
D
O
D
T
_
P
C
X
3
1
D
S
M
T
_
P
C
X
8
G
9
F
N
T
S
R
T
_
P
C
X
C13 XCP_WEN
4
FB
T
S
R
F
X
C6
XOSC32OUT
XPA0/CS1N
M15
N2 XPA10/IRQ4
1
T3
N
I
S
/
3
B
K
_
P
C
X
2
R4
N
I
S
/
4
B
K
_
P
C
X
0
T
U
O
S
/
5
B
K
_
P
C
X
3
T
1
T
U
O
S
/
6
B
K
_
P
C
X
3
U
2
T
U
O
S
/
7
B
K
_
P
C
X
3
P
3
T
U
O
S
/
8
B
K
_
P
C
X
4
T
3
N4
T
U
O
S
/
9
B
K
_
P
C
X
K
C
T
_
P
C
X
XCP_D6
E7
D5 XCP_D7
C4 XCP_D8
XCP_D9
B4
7
C
I
D
T
_
P
C
X
0
N
I
S
/
0
B
K
_
P
C
X
4
L
1
N
I
S
/
1
B
K
_
P
C
X
5
L
2
N
I
S
/
2
B
K
_
P
C
X
4
M
XCP_D11
XCP_D12
C2
D2 XCP_D13
D3 XCP_D14
XCP_D15
E3
F8 XCP_D2
XCP_D3
F7
C5 XCP_D4
XCP_D5
D6
XCP_A8
B17
C17 XCP_A9
A13 XCP_CSRAMEN
XCP_CSROMEN
A12
XCP_D0
A6
B5 XCP_D1
XCP_D10
B3
C1
XCP_A2
E14
XCP_A20
L15
L16 XCP_A21
D15 XCP_A3
B15 XCP_A4
XCP_A5
C14
A16 XCP_A6
XCP_A7
A15
XCP_A12
G14
G13 XCP_A13
XCP_A14
G17
J12 XCP_A15
K12 XCP_A16
XCP_A17
K13
K14 XCP_A18
XCP_A19
L14
A11
XAG2 E11
D11
XAG3
XBSWN
B7
XCPTSTSTOP_CKO M12
B13 XCP_A0_BEON
F11 XCP_A1
D16 XCP_A10
XCP_A11
F14
1
1
H
7
J
S
S
V
6
K
S
S
V
0
1
E
A
S
S
V
5
1
E
L
L
P
D
_
S
S
V
X1RTC
A7
D10
X2RTC
B11
XAG0
XAG1
1
1
J
S
S
V
S
S
V9
L
3
A
S
S
V
6
F
S
S
V
S
S
V9
G
0
1
G
S
S
V
S
S
V7
H
S
S
V
L
L
P
D
_
D
D
V6
1
G
C
T
R
V8
D
S
S
V2
A
S
S
V7
K
S
S
V6
L
0
1
L
S
S
V
S
S
V7
M
8
L
S
S
V
4
1
B
E
D
D
V1
M
2
U
E
D
D
V
E
D
D
V8
P
5
1
U
E
D
D
V
E
D
D
V6
1
U
6
1
N
E
D
D
V
E
D
D
V6
1
E
7
1
E
E
D
D
V
D
D
V3
1
T
6
1
R
D
D
V
D
D
V7
1
R
5
A
D
D
V
D
D
V6
1
C
A
D
D
V1
1
C
1
B
E
D
D
V
E
D
D
V
H12
F12
TDO
G12
TMS
TRST F15
D
D
V2
E
7
1
L
D
D
V
1
G
D
D
V
D
D
V1
R
4
R
D
D
V
IO7
IOBIT#1 K11
IOBIT#2 L12
C
N1
2
C
N
B
T
S
R2
1
C
RWN U5
TCK H13
TDI
U7
DB#4
T7
DB#5
DB#6 R7
M6
DB#7
P7
DB#8
DB#9 N7
N4
INT#0 R12
DB#1
DB#10 N8
M8
DB#11
DB#12 U11
T11
DB#13
R11
DB#14
DB#15 P10
R6
DB#2
DB#3 P6
P12
AB#5
AB#6 R14
AB#7 T14
T17
AB#8
7
1
F
I
K
C
G15
CKO
DB#0 P5
U6
U400
U13
AB#0
AB#1 M10
R13
AB#2
N11
AB#3
AB#4 P11
R404
DSP_TDO
VCCD
C424C423
VS 1
R407
U402
GND
3
2VO
C406
R402
DSP_TCK
TP404
R408
VDD_18D
R415
VDD_18D
VBAT
R403
R409
TP406
VCCD
C410
SVC_BLUE
PH_PWR_OFF
CLK32K
JACK_SENSE
BP_VF
DSP_AB(8)
ARM_TRSTN
UP_SCLK
UP_CS
FLASH_RESET
VREF
CP_CSROM2EN
SW_RST_INT
A(23)
BT_REQ
SIMRST
T
C
E
T
E
D
_
C
L
D
RTC_nALARM
TR_RST
ARM_TCK
DSP_DB(0:15)
D(0:15)
A(0:20)
A(21)
AT_nRTS
DSP_AB(0:8)
UP_SDI
UP_SDO
ARM_TDO
ARM_TRSTN
ARM_TDI
ARM_TMS
PH_WAKEUP
AT_nDTR
PH_OFF_nRDY
AT_nDSR
PWR_KEEP
AT_TXD
AT_nCTS
PDA_WAKEUP
SDS_TXD
CP_INT
PDA_ACTIVE
AT_RXD
SDS_RXD
SIMDATA
SIMCLK
PH_ACTIVE
DSP_IO
DSP_RWN
DSP_INT
TR_RST
CLK13M_TR
DSP_DB(12)
DSP_DB(13)
DSP_DB(14)
DSP_DB(15)
DSP_DB(2)
DSP_DB(3)
DSP_DB(4)
DSP_DB(5)
DSP_DB(6)
DSP_DB(7)
DSP_DB(8)
DSP_DB(9)
A(22)
CP_CSROMEN
CP_CSRAMEN
CP_WEN
CP_OEN
UPPER_BYTE
A(20)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
DSP_DB(0)
DSP_DB(1)
DSP_DB(10)
DSP_DB(11)
DSP_AB(0)
DSP_AB(1)
DSP_AB(2)
DSP_AB(3)
DSP_AB(4)
DSP_AB(5)
DSP_AB(6)
DSP_AB(7)
A(0)
A(1)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(2)