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SGH-X450 CircuitDescription
2-5
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YMU762 includesaspeakeramplifierwith high rippleremovalratewhosemaximumoutput is550mW(SPVDD=3.6V).
Thedevice isalsoequippedwithconventionalfunction including avibartorand a circuit forcontrolling LEDs synchornous
withmusic.
Fortheheadphone,it isprovidedwithastereophonicoutput terminal.
Forthepurposeofenabling YMU762MA3to demonstarteitsfull capablities,Yamahapurposeto use"SMAF:Synthetic
musicMobileApplication Format"asadatadistribution format that iscompatiblewihtmultimedia.Since theSMAFtakes
astructurethatsetsimportance on thesynchronization betweensound and images,variouscontentscan bewrittenintoit
including incoming call melody withwordsthatcan beusedfortraning karaoke,and commercialchannel thatcombines
texts,imagesand sounds,and others.ThehardwaresequencerofYMU762MA3 directlyinterpretsand playsblocks
relevant tosysthesis(playing music and reproducing ADPCMwithFMsynthesizer) thatareincludedin datadistributedin
SMAF.
5)Memory
This systemusesSHARP'smemory,LRS1828.
It isconsisted of128Mbitsflashmemoryand 32MbitsSCRAM.Ithas16 bit dataline,D[0~15]whichisconnectedto
trident,LCDorCSP1093.Ithas22 bit address lines,A[1~22].Theyare connectedtoo.CP_CSROMENand
CO_CSROM2ENsignals,chipselectsignalsinthetridentenabletwomemories.They use3 volt supply voltage,VCCD.
During wrting process,CP_WENislowand it enableswriting process toflashmemoryand SCRAM.During reading
process,CP_OENislowand it output information whichislocatedat the address fromthetrident intheflashmemory or
SCRAMto datalines.Eachchipselectsignalsinthetridentselectmemoryamong 2 flashmemoryand SCRAM.Reading
orwriting procedureisprocessedafterCP_WENorCP_OENisenabled.MemoriesuseFLASH_RESET,whichisbuffered
signalofRESET fromPSC2106,forESDprotection.A[0]signalenableslowerbyteofSCRAMand UPPER_BYTE signal
enableshigherbyteofSCRAM.
6)Trident
Trident isconsisted ofARMcore and DSP core.Ithas20K*16bitsRAM144K*16bitsROMintheDSP.Ithas
4K*32bitsROMand 2K*32bitsRAMintheARMcore.DSP isconsisted oftimer,onebit input/outputunit(BIO),JTAG,
EMIand HDS(HardwareDevelopmentSystem).ARMcoreisconsisted ofEMI,PIC(ProgrammableInterruptController),
reset/power/clock unit,DMAcontroller,TIC(TestInterface Controller),peripheralbridge,PPI,SSI(SynchronousSerial
Interface),ACCs(Asynchronouscommunicationscontrollers),timer,ADC,RTC(Real-TimeClock)and keyboardinterface.
DSP_AB[0~8],address linesofDSP core and DSP_DB[0~15],datalinesofDSP core are connectedtoCSP1093.A[0~20],
address linesofARMcore and D[0~15],datalinesofARMcore are connectedtomemory,LCDand YMU762.
ICP(InterprocessorCommunication Port)controlsthe communication betweenARMcore and DSP core.
CSROMEN,CSRAMENand CS1NtoCS4NintheARMcore are connectedtoeachmemory.WENand OENcontrol the
process ofmemory.ExternalIRQ(InterruptReQuest)signalsfromeach units,suchas,YMU,Ear-jack,Ear-mic and
CSP1093,needthe compatibleprocess.