Sanyo LC78626KE User manual

Overview
The LC78626KE is a monolithic compact disk player
signal processing and servo control CMOS IC equipped
with an internal anti-shock control function. Designed for
total functionality including support for EFM-PLL, and
one-bit D/A converter, and containing analog low-pass
filter, the LC78626KE provides optimal cost-performance
for low-end CD players that provide anti-shock systems
by eliminating as many unnecessary features as possible.
The basic functions provided by this IC include
modulation of the EFM signal from the optical pick-up,
deinterleaving, detection and correction of signal errors,
prevention of a maximum of approximately 38 seconds of
skipping, signal processing such as digital filtering (which
is useful in reducing the cost of the player), and processing
of a variety of servo-related commands from the
microprocessor. The LC78626KE is an improved version
of the LC78626E. It provides 8×oversampling digital
filters and supports up to 16M of DRAM.
Functions
• When an HF signal is input, it is sliced to precise levels
and converted to an EFM signal. The phase is compared
with the internal VCO and a PLL clock is reproduced at
an average frequency of 4.3218 MHz.
• Precise timing for a variety of required internal timing
needs (including the generation of the reference clock) is
produced by the attachment of an external 16.9344 MHz
crystal oscillator.
• The speed of revolution of the disk motor is controlled
by the frame phase difference signal generated by the
playback clock and the reference clock.
• The frame synchronizing signal is detected, stored, and
interpolated to insure stable data read back.
• The EFM signal is demodulated and converted to 8-bit
symbolic data.
• The demodulated EFM signal is divided into subcodes
and output to the external microprocessor. (Three
general I/O ports are shared [exclusively] for this
purpose.)
• After the subcode Q signal passes the CRC check, it is
output to the microprocessor through a serial
transmission (LSB first).
• The demodulated EFM signal is buffered in the internal
RAM, which is able to absorb ±4 frame’s worth of jitter
resulting from variations in the disk rotation speed.
• The demodulated EFM signal is unscrambled to a
specific sequence, and deinterleaving is performed.
Package Dimensions
unit: mm
3151-QFP100E
21.6 0.8
3.0max
1.6 17.2
0.825
130
31
50
51
80
81
1.6
0.575
0.575 0.15
2.7
15.6
0.3
20.0
23.2
14.0 0.65 0.825
100
0.8
0.65
0.1
CMOS IC
21099RM(OT) No. 5995-1/34
SANYO: QFP100E (QIP100E)
[LC78626KE]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
DSP for Compact Disk Players
LC78626KE
Ordering number : EN5995
Continued on next page.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

No. 5995-2/34
LC78626KE
Continued from preceding page.
•Error detection and correction is performed, as is a flag
process. (C1: two error/C2: two error correction
method.)
•The C2 flag is set after referencing the C1 flag and the
results of the C2 check, where the signal from the C2
flag is interpolated or held at its previous level. The
interpolation circuit uses double interpolation. When
there are two or more C2 flags in a row, the previous
value is held.
•Command (such as track jump, start focus, disk motor
start/stop, muting on/off, track count, etc.) is are
executed after they are entered from the microprocessor.
(An 8-bit serial input is used.)
• The digital output is equipped internally.
•High speed access is supported through discretionary
track counting.
•Using the 8× oversampling digital filter, D/A converter
signals with improved continuity of output data are
produced.
• A ∆∑-type D/A converter using a 3-order noise shaper is
equipped internally. (An analog low-pass filter is
equipped internally.)
• Internal digital attenuator (8-bit-α; 239 steps.)
• Internal digital deemphasis
• Uses 0 cross mute.
• Bilingual compatibility
•General I/O ports: 4. (Three of these are shared,
exclusively, with the subcode output function.)
•Up to 38 seconds of skip prevention (when using 16M
of DRAM) through 5-bit ADPCM compression/
expansion processing. 1M/4M/4M × 2/16Μ bits DRAM
can be selected.
• Memory overflow detection output
• Free memory output
Features
• 100-pin QIP
• A single 3.2 V power supply
Pin Assignment
Top view

Equivalent Circuit Block Diagram
No. 5995-3/34
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Digital out
RAM address
generator
Interpolation mute
Shock
detector
Contact
detector
ADPCM encoder
Data width
changer
2K ×8-bit RAM
Digital
attenuator
4 ×oversampling digital filter
C1, C2 error detection and
correction flag process
VCO clock production
clock control
Slice level control
Sync detect
EFM
demodulation
CLV digital servo
Subcode partition
QCRC
Microprocessor
interface
Servo commands General ports
Disable
Crystal oscillator-system
timing generator
One-bit DAC
Low-pass
filter
ADPCM
decoder
DRAM control
Overflow process
initiation control

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Parameter Symbol Conditions Ratings Unit
Maximum power supply voltage VDD max VSS – 0.3 to VSS + 4.0 V
Input voltage VIN VSS – 0.3 to VDD + 0.3 V
Output voltage VOUT VSS – 0.3 to VDD + 0.3 V
Allowable power dissipation Pd max 400 mW
Operating temperature range Topr –20 to +75 °C
Storage temperature range Tstg –40 to +125 °C
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter Symbol Conditions Ratings Unit
min typ max
VDD1VDD, XVDD, LVDD, RVDD, VVDD:3.0 3.6 V
Power supply voltage ATT/DF/DAC to the normal speed
VDD2VDD, XVDD, LVDD, RVDD, VVDD:3.6 3.6 V
All functions guaranteed to 2×speed
VIH1I/O and input pins with the exception of 0.7 VDD VDD V
Input high-level voltage EFMI and DRAM0 to DRAM3
VIH2 EFMI 0.6 VDD VDD V
VIH3 DRAM0 to DRAM3 0.45 VDD VDD V
VIL1I/O and input pins with the exception of 0 0.3 VDD V
Input low-level voltage EFMI and DRAM0 to DRAM3
VIL2 EFMI 0 0.4 VDD V
VIL2 DRAM0 to DRAM3 0 0.2 VDD V
Data setup time tSU COIN, RWC: Figure 1 400 ns
Data hold time tHD COIN, RWC: Figure 1 400 ns
High level clock pulse width tWH SBCK, CQCK: Figures 1 to 3 400 ns
Low level clock pulse width tWL SBCK, CQCK: Figures 1 to 3 400 ns
Data read access time tRAC SQOUT, PW: Figures 2 and 3 0 400 ns
Command transfer time tRWC RWC: Figure 1 1000 ns
Subcode Q read enable time tSQE WRQ: Figure 2, no RWC signal 11.2 ms
Subcode ready cycle time tSC SFSY: Figure 3 136 µs
Subcode read enable time tSE SFSY: Figure 3 400 ns
Port input data setup time tCSU CONT2 to CONT5, RWC: Figure 4 400 ns
Port input data hold time tCHD CONT2 to CONT5, RWC: Figure 4 400 ns
Port input clock setup time tRCQ RWC, CQCK: Figure 4 100 ns
Port output data delay time tCDD CONT2 to CONT5, RWC: Figure 5 1200 ns
Input level VIN1 EFMI: slice level control, VDD = 3.0 V 0.8 Vp-p
VIN2 XIN: C coupling input 1.0 Vp-p
Range of operating frequencies fOP EFMI 10 MHz
Crystal oscillator frequency fXXIN, XOUT 16.9344 MHz
Allowable Operating Range at Ta = 25°C, VSS = 0V
Parameter Symbol Conditions Ratings Unit
min typ max
Current drain IDD VDD, XVDD, LVDD, RVDD, VVDD: 14 20 mA
VDD = 3.0 to 3.4 V with normal playback
DEFI, EFMI, HFL, TES, RWC, COIN, CQCK,
IIH1FMT, MR1, MR2, RES, TESD, WOK, 5 µA
PAUSE IN, SHOCK, TESCLK, TESA, TESB,
Input high-level current TESC, TESGB, TEST1: VIN = VDD
IIH2TAI, TEST2 to TEST5, CS 15 55 µA
VIN = VDD = 3.6 V
Electrical Characteristics at Ta = 25°C, VDD = 3.2 V, VSS = 0V
Continued on next page.

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Continued from preceding page.
Parameter Symbol Conditions Ratings Unit
min typ max
DEFI, EFMI, HFL, TES, RWC, COIN, CQCK,
FMT, MR1, MR2, RES, TESD, WOK,
Input low-level current IIL PAUSE IN, SHOCK, TESCLK, TESA, TESB, –5 µA
TESC, TESGB, TAI, TEST1 to TEST5, CS :
VIN = 0 V
EFMO, CLV+, CLV–, V/P, TOFF, TGL, JP+,
VOH1 JP–, PCK, FSEQ, EFLG, FSX, EMPH : 2.56 V
IOH = –1 mA
CONT2 to CONT5, SBSY, MUTEL, MUTER,
Output high-level current VOH2 C2F, WRQ, SQOUT, 16M/NGJ, 4.2M, EMPP, 2.56 V
OVF, CNTOK, NGJ : IOH = –0.5 mA
VOH3 DOUT : IOH = –12 mA 2.72 V
VOH4
OE, WE, CAS, RAS, AD10/CAS2, AD9 to AD0,
2.56 V
DRAM3 to DRAM0 : IOH = –0.5 mA
VOH5 MMC0 to MMC3 : IOH = –2 mA 2.24 V
VOL1EFMO, CLV+, CLV–, V/P, TOFF, JP+, JP–, 0.64 V
PCK, FSEQ, EFLG, FSX, EMPH : IOL = 1 mA
CONT2 to CONT5, SBSY, MUTEL, MUTER,
VOL2 C2F, WRQ, SQOUT, 16M/NGJ, 4.2M, EMPP, 0.32 V
Output low-level current OVF, CNTOK : IOL = 2 mA
VOL3 DOUT : IOL = 12 mA 0.48 V
VOL4
OE, WE, CAS, RAS, AD10/CAS2, AD9 to AD0,
0.44 V
DRAM3 to DRAM0 : IOL = 0.5 mA
VOL5 MMC0 to MMC3 : IOL = 2 mA 0.96 V
PDO, CLV+, CLV–, JP+, JP–,
IOFF1 CONT2 to CONT5, DRAM0 to DRAM3, 5 µA
Output off leakage current ASRES : VOUT = VDD
PDO, CLV+, CLV–, JP+, JP–,
IOFF2 CONT2 to CONT5, DRAM0 to DRAM3, –5 µA
ASRES : VOUT = 0 V
Charge pump output current IPDOH PDO : RISET = 68 kΩ30 42 54 µA
IPDOL PDO : RISET = 68 kΩ–54 –42 –30 µA
Parameter Symbol Conditions Ratings Unit
min typ max
Total harmonic distortion rate TRD+N LCHO, RCHO; 1 kHz: Uses the 0 dB data 0.035 0.038 %
input and the 20 kHz-LPF (in the AD725D)
LCHO, RCHO; 1 kHz: Uses the –60 dB data
Dynamic range DR input, the 20 kHz-LPF (in the AD725D), and 81 84 dB
the A filter
LCHO, RCHO; 1 kHz: Uses the 0 dB data
Signal to noise ratio S/N input, the 20 kHz-LPF (in the AD725D), and 87 92 dB
the A filter
Cross talk CT LCHO, RCHO; 1 kHz: Uses the 0 dB data 79 82 dB
input and the 20 kHz-LPF (in the AD725D)
One-bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = LVDD = RVDD = 3.2 V, VSS = L/RVSS = 0 V
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit.

Figure 1 Command Input
Figure 2 Subcode Q Output
Figure 3 Subcode Output
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No. 5995-7/34
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Figure 4 General Port Input Timing
Figure 5 General Port Output Timing

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Description of Pins
Pin Pin I/O Function Output pin states
No. Name during reset
1 DEFI I Defect detection signal (DEF) input. When not used, must be connected to 0 V. —
2 TAI I Test input. Equipped with internal pull-down resistor. Must be connected to 0V. —
3 PDO O Internal VCO control phase comparator output —
4 VVSS PFor the PLL Internal VCO ground. Must be connected to 0 V. —
5 ISET AI PDO output current adjustment resistor connection —
6 VVDD PInternal VCO power supply —
7 FR AI VCO frequency range adjustment —
8 VSS P Digital system ground. Must be connected to 0 V. —
9 TESCLK I Test clock input. Must be connected to VDD. —
10 TESA I Test operation mode control input. Must be connected to VDD. —
11 TESB I Test operation mode control input. Must be connected to VDD. —
12 TESC I Test operation mode control input. Must be connected to VDD. —
13 TESGB I Test operation mode control input. Must be connected to VDD. —
14 TEST5 I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V. —
15 CS I Chip select input. Equipped with internal pull-down resistor. When not controlled, must be connected to 0 V. —
16 TEST1 I Test input. Must be connected to 0 V. —
17 EFMO O For slice EFM signal output Undefined
18 EFMI I level control EFM signal input —
19 TEST2 I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V. —
20 CLV+ODisk motor control output. Can have a 3-state output depending on the command.
Low-level output
21 CLV–O
22 V/P O
Low-level output
23 HFL I Track detect signal input. Schmidt input. —
24 TES I Tracking error signal input. Schmidt input. —
25 TOFF O Tracking off output
High-level output
26 TGL O Tracking gain switch output. Gain is increased with low level. Undefined
27 JP+OTrack jump control output. Can be 3-state output depending on the command.
Low-level output
28 JP–O
29 PCK O EFM data playback clock monitor. 4.3218 MHz during phase lock.
Low-level output
30 FSEQ O Undefined
31 VDD PDigital system power supply —
32 ASRES I(I/O) Input mode
33 CONT2 I/O Input mode
Continued on next page.
Rough servo/phase control automatic switching monitor output. If a high level then rough servo mode.
If a low level then phase control mode.
Sync signal detect output. A high level when the sync signal detected from the EFM signal matches the
internally generated sync signal.
Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when
this pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e.,
connected to 0 V) if when using software control on the anti-shock part alone through the anti-shock part
only reset disable/release command ($F4) or the anti-shock only reset enable/inrush command ($F5).
Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O
pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always “0,” and
the output driver is not turned ON.
General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as
an input port and connect to 0 V, or set this as an output port and leave it open.

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Continued from preceding page.
Pin Pin I/O Description Output pin states
No. Name during reset
34 CONT3/SBCK I/O Input mode
35
CONT4/SFSY I/O Input mode
36
CONT5/PW I/O Input mode
37 SBSY O Subcode block sync signal output Undefined
38 TEST3 I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V. —
39 DOUT O Digital output. EIAJ format. Undefined
40 TEST4 I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V. —
41 16M/NGJ O Clock output
42 4.2M O 4.2336 MHz output Clock output
43 EFLG O C1, C2, one error, two error error correction monitor output Undefined
44 FSX O 7.35 kHz sync signal output (frequency divided from the crystal oscillator). Undefined
45 EMPH O Deemphasis monitor output. When high level, a deemphasis disk is being played back.
Low-level output
46 C2F O C2 flag output Undefined
47 TOUT O Test output. Under normal operation, this should be left open. Undefined
48 MR1 I DRAM switch: high : 1M, low : 4M —
49 MR2 I 1 M: high, low 4 M: low, low 16 M: low, high 4 M X 2: high, high (MR1, MR2)
50 TESD I Test input. Must be connected to 0V. —
51 MUTESL O L channel mute output
High-level output
52 LVDD PL channel power supply —
53 LCHO AO L channel output —
54 L/RVSS PFor the one-bit D/A L/R channel ground. Must be connected to 0 V. —
55 RCHO AO converter R channel output —
56 RVDD PR channel power supply —
57 MUTER O R channel mute output
High-level output
58 XVDD PCrystal oscillator power supply —
59 XOUT O 16.9344 MHz crystal oscillator connection —
60 XIN I
61 XVSS P Crystal oscillator ground. Must be connected to 0 V. —
62 RWC I Read/write control input. Schmidt input. —
63 COIN I Microcontroller command input —
64 CQCK I Input pin for the command input latch clock and the subcode readout clock. Schmitt input. —
65 SQOUT O Subcode Q output Undefined
66 WRQ O Subcode Q output standby output Undefined
67 FMT I Operating mode switch: high: shock proof, low: through. —
68 EMPP O DRAM empty (an RZP pulse is output when the DRAM is empty).
Low-level output
69 RES I External reset input: low reset (all internal blocks are reinitialized). —
Continued on next page.
General I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or
set this as an output port and leave it open.
General I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
General I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with
the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
Shared function pin that functions either as the 16.9344 MHz output (16M) or as the C2 flag data continuity check
start signal (detection start is indicated by a low to high transition). Controlled by microcontroller commands.

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Continued from preceding page.
Pin Pin I/O Description Output pin states
No. Name during reset
70 MMC0 O Remaining DRAM output Low-level output
71 MMC1 O Remaining DRAM output Low-level output
72 MMC2 O Remaining DRAM output Low-level output
73 MMC3 O Remaining DRAM output Low-level output
74 OVF O DRAM write terminated. (An RZP pulse is output when there is an overflow or a shock.) Low-level output
75 CNTOK O Data contact point detection complete signal: low→high: detection complete. (DRAM write start). High-level output
76 WOK I DRAM write enable signal input: high: write enable. —
77 PAUSE IN I Pause signal input: high: pause. —
78
AD10/CAS2 O Undefined
79 EMPN O Remaining DRAM alarm output: low: memory low.
Low-level output
80 SHOCK I C2F shock detect pause signal input: low: pause shock detection. —
81 DRAM3 I/O DRAM data bus Input mode
82 DRAM2 I/O DRAM data bus Input mode
83 DRAM1 I/O DRAM data bus Input mode
84 DRAM0 I/O DRAM data bus Input mode
85 OE O DRAM control signal
Low-level output
86 WE O DRAM control signal High-level output
87 CAS O DRAM control signal Undefined
88 RAS O DRAM control signal Undefined
89 AD9 O DRAM address bus
Low-level output
90 AD8 O DRAM address bus Low-level output
91 AD7 O DRAM address bus Low-level output
92 AD6 O DRAM address bus Low-level output
93 AD5 O DRAM address bus Low-level output
94 VSS P Digital system ground. Must be connected to 0 V. —
95 AD4 O DRAM address bus
Low-level output
96 AD3 O DRAM address bus Low-level output
97 AD2 O DRAM address bus Low-level output
98 AD1 O DRAM address bus Undefined
99 AD0 O DRAM address bus Undefined
100 VDD PDigital system power supply —
Shared function pin that functions either as a 16M DRAM address output (AD10) or as a DRAM control
signal (CAS2) used when 8M of DRAM (two 4M DRAM chips) is used. The function is switched by the
DRAM selection pins MR1 and MR2.

Pin Applications
The HF Signal Input Circuit Pin 18: EFMI, Pin 17: EFMO, Pin 1: DEFI, and Pin 20: CLV+
When an HF signal is input to the EFMI, an EFM signal (NRZ),
sliced at the optimal levels, is obtained.
As a countermeasure against defects, when the DEFI pin (Pin 1)
is high, the slice level control output EFMO pin (Pin 17) goes to
a high impedance state, and the slice level is held. However, this
is only enabled when the CLV is in phase-control mode, or in
other words, when the V/P pin (Pin 22) is low. This can be
structured from a combination with the DEF pin of LA9230/
40/50 series ICs.
* When the EFMI and CLV+signal lines are close to each other
then the error rate due to unnecessary radiation may increase.
It is recommended that these two lines be separated by a
ground line or by a VDD line as a shield line.
The PLL Clock Playback Circuit Pin 3: PDO, Pin 5: ISET and Pin 7: FR
The VCO circuit is equipped internally, and the PLL circuit is
structured using external resistors and external capacitors. The
ISET is the reference current for the charge pump. The PDO is
the loop filter for the VCO circuit, and the FR is the resistor that
determines the frequency range of the VCO.
Reference Values
R1 = 68 kΩC1 = 0.1 µF (standard speed)
C1 = 0.047 µF (2×speed)
R2 = 680 ΩC2 = 0.1 µF
R3 = 1.2 kΩ
* It is recommended that a carbon coated resistor with a
tolerance of ±5.0% be used for R3.
The VCO Monitor Pin 29: PCK
This is the monitor pin with an average frequency of 4.3218 MHz, which is a 1/2 frequency division from VCO.
The Sync Detect Monitor Pin 30: FSEQ
The EFM signal goes high when the frame sync signal (the true sync signal) from the PCK matches the timing (the
interpolated sync signal) generated by the counter. This serves as the sync detect monitor (holding the high level over a
single frame).
No. 5995-11/34
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HF Signal
Frequency
and phase
comparator
Charge pump

The Servo Command Functions Pin 62: RWC, Pin 63: COIN, Pin 64: CQCK
Various commands can be executed by setting RWC to high and by inputting the command from COIN synchronized
with the CQCK clock. The commands are executed beginning with the falling edge of RWC.
Focus start
Track jump
Mute control Single-byte commands
Disk motor control
Other control
Track check Two-byte command (two sets of RWC)
Digital attenuator Two-byte commands (once set of RWC)
General port I/O settings
• Single-byte commands
• Two-byte commands (RWC 2 set: for the track count)
• Two-byte commands (RWC 1 set: digital attenuation and setting the general I/O port)
• Eliminating command noise
This command makes it possible to reduce the noise that is mixed into the CQCK clock. This is effective for noise of
less than 500 ns; however, the CQCK timing must be set to have 1 µs or more for tWL, tWH, and tSU.
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Code COMMAND RES = low
$EF Command input noise reduction mode
$EE Resets the command input noise reduction mode ●●
Command ($F0, $F8) Data ($08 to $FE), command ($FF)
At least 1 µs
Data Commands ($81 to $87, $DB, $DC)

The CLV Servo Circuit Pin 20: CLV+, Pin 21: CLV-, Pin 22: V/P
CLV+is the signal for accelerating the disk in the forward direction, while CLV–is the signal for decelerating the disk.
Depending on the commands from the microcontroller, one of the following four modes is selected: Accelerate,
decelerate, CLV, or stop. The CLV+and CLV–outputs for each mode are as shown in the table below.
* The CLV servo control command is such that the TOFF pin is low only when the CLV mode is in effect, and it is high
otherwise. The TOFF pin control by the command is only active when the CLV mode is in effect.
• CLV mode
In the CLV mode the rotation of the disk is detected from the HF signal, and a precise linear speed of rotation is
derived by exerting the respective forms on control when the internal modes of the DSP change. The PWM frequency
is 7.35 kHz. The V/P has a high output when the internal mode is the rough servo, and a low output when the internal
mode is phase control.
• Switching the rough servo gain
When the internal mode is the rough servo, the CLV control gain for the 8 cm disk can be reduced by 8.5 dB from the
level for the 12 cm disk.
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Code COMMAND RES = low
$04 DISC MOTOR START (Accelerate)
$05 DISC MOTOR CLV (CLV)
$06 DISC MOTOR BRAKE (Decelerate)
$07 DISC MOTOR STOP (Stop) ●●
MODE CLV+CLV–
Accelerate High Low
Decelerate Low High
CLV Pulse output Pulse output
Stop Low Low
Internal mode CLV+CLV–V/P
Rough servo (when the rotational speed is determined to be low) High Low High
Rough servo (when the rotational speed is determined to be high) Low High High
Phase control (when the PCK clock is running) PWM PWM Low
Code COMMAND RES = low
$A8 DISC 8 cm Set
$A9 DISC 12 cm Set ●●

• Switching the phase control gain
By changing the frequency division value of the first-stage frequency divider of the phase comparator it is possible to
change the phase control gain.
• CLV 3-state output
The CLV 3-state output command makes it possible to control the CLV with a single pin. However, because this will
cause the spindle gain to fall by 6 dB, it will be necessary to increase the gain on the servo side.
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Code COMMAND RES = low
$B1 CLV phase comparator 1/2 frequency division
$B2 CLV phase comparator 1/4 frequency division
$B3 CLV phase comparator 1/8 frequency division
$B0 CLV phase comparator, no frequency division ●●
Code COMMAND RES = low
$B4 CLV 3-state output
$B5 CLV 2-state output (traditional method) ●●
Phase
comparator
2-state output
3-state output
Acceleration Deceleration
High impedance output

• Internal brake mode
* The internal brake mode is turned on by inputting the internal brake on command ($C5). When in this mode, when
the brake command ($06) is executed it becomes possible to monitor the state of deceleration of the disk using the
WRQ pin.
* In this mode, the status of deceleration of the disk is determined by counting the density of the EFM signals in a
single frame, and the CLV–is low if the number of EFM signals is 4 or less. At the same time, the WRQ signal is
put to high as the break complete monitor. The microcontroller issues the STOP command if it senses that the
WRQ signal is high, and thus brings the disk to a complete stop. In the internal break continuous mode the CLV–=
high brake operation continues even when the break complete monitor WRQ goes high.
When noise in the EFM signal causes the deceleration status to be judged incorrectly, it may be advisable to use the
internal break control command ($A3) to change the EFM signal count from 4 to 8.
* In the TOFF output inhibited mode ($CD), TOFF is low while the internal break is in operation. Its use is
recommended because it is effective in preventing incorrect detection at the mirrored surface of the disk.
* When there is a loss of focus during the execution of an internal break command it will be necessary to reissue the
internal brake command after the focus has been reestablished.
* Because there is a risk that the EFM signal will be discerned incorrectly depending on the playback status
(scratched disks, access processes, etc.), use in conjunction with the microcontroller is recommended.
* When the internal brake mode is in effect, then it is possible to monitor the disk deceleration status at the WRQ Pin
by executing the DISC MTR BRAKE command ($06) in this DSP. However, if another command is executed
while this command is in process, then the command will be aborted. When you wish to prevent the function from
being aborted, then, after issuing the DISC MTR BRAKE command ($06), do not issue any other commands until
a high WRQ signal is detected and the DISC MTR STOP command ($07) is issued.
The Track Jump Circuit Pin 23: HFL, Pin 24: TES, Pin 25: TOFF, Pin 26: TGL, Pin 27: JP+, Pin 28: JP–
• Types of track counters
The following two track count modes have been provided.
The conventional track counter uses the TES signal itself as the internal track counter clock. In the new track count
method, however, the TES signal is combined with the HFL signal to reduce the amount of noise, producing a more
accurate track count through reducing the number of miscounts due to noise in the rising edge and falling edge of the
TES signal. However, when the HFL signal is absent because of dust, scratches, etc., there is the danger that there
will be no track count pulse, and thus caution is required when using this method.
No. 5995-15/34
LC78626KE
Code COMMAND RES = low
$C5 Internal Break ON
$C4 Internal Break OFF ●●
$A3 Internal brake control
$CB Internal brake continuous mode
$CA Internal brake continuous mode reset ●●
$CD Internal brake TON mode
$CC Internal brake TON mode reset ●●
Code COMMAND RES = low
$22 The new track count (a combination of TES and HFL) ●●
$23 The conventional track count (direct count of the TES signal)
EFM signal
$06 command

• The TJ command
When the track jump command is input to the servo command an acceleration pulse is generated (period a), following
which a deceleration pulse is generated (period b), after which the specific jump is completed after the brake period
(period c) elapses. In this break period the beam slip direction is detected through the TES and HFL inputs, and the
segment of the TES signal that propagates the internal slip is cut by TOFF. Moreover, by increasing the servo gain
using TGL, it is possible to lock onto the track that is the jump destination. In the JP pulse interval TOFF output
mode, TOFF is high during the interval when the JP pulse is generated.
* The TOFF pin is only low when the CLV mode is active when related to the disk control mode, and this terminal is
high during start, stop, and break control. Moreover, the TOFF pin can be turned on and off independently using
commands. However, the disk motor control is only enabled when the CLV mode is active.
No. 5995-16/34
LC78626KE
Code COMMAND RES = low
$A0 The conventional track jump ●●
$A1 The new track jump
$11 1 TRACK JUMP IN #1
$12 1 TRACK JUMP IN #2
$31 1 TRACk JUMP IN #3
$52 1 TRACK JUMP IN #4
$10 2 TRACK JUMP IN
$13 4 TRACK JUMP IN
$14 16 TRACK JUMP IN
$30 32 TRACK JUMP IN
#15 64 TRACK JUMP IN
$17 128 TRACK JUMP IN
$19 1 TRACK JUMP OUT #1
$1A 1 TRACK JUMP OUT #2
$39 1 TRACK JUMP OUT #3
$5A 1 TRACK JUMP OUT #4
$18 2 TRACK JUMP OUT
$1B 4 TRACK JUMP OUT
$1C 16 TRACK JUMP OUT
$38 32 TRACK JUMP OUT
$1D 64 TRACK JUMP OUT
$1F 128 TRACK JUMP OUT
$16 256 TRACK CHECK
$0F TOFF
$8F TON ●●
$8C TRACK JUMP BRAKE
$21 JP pulse period TOFF output mode
$20 JP pulse period TOFF output mode reset ●●
(Brake period)
(JP pulse period)

• TJ mode
The relationships between the acceleration pulse, deceleration pulse, and brake interval are as shown in the table
below.
* The 256 TRACK CHECK does not produce an actuator drive signal as shown in the table above, rather because the
mode is such that the TES signal is counted when the tracking loop is off, it is necessary to provide a feed to the feed
motor.
* When the track jump sequence (a, b, c) is completed, the servo command register is reset automatically.
* When a new command has been input when the track jump is in process, that command is executed at that instant.
* In the 1 TRACK JUMP #3 command there is no brake period (period c), but rather caution is warranted because it is
necessary to generate the brake mode using an external circuit.
* Although in the 2TRACK JUMP IN (OUT) of the new track jump mode the brake period (period c) did not exist for
the LC78620E/21E/25E ICs, in this IC period C has been changed to 60 ms.
No. 5995-17/34
LC78626KE
Command When in the conventional track jump mode When in the new track jump mode
a b c a b c
1 TRACK JUMP IN (OUT) #1 233 µs 233 µs 60 ms Same as in the conventional mode
1 TRACK JUMP IN (OUT) #2 0.5 TRACK 233 µs 60 ms 0.5 TRACK The same 60 ms
JUMP period JUMP period as for a
1 TRACK JUMP IN (OUT) #3 0.5 TRACK 233 µs This period 0.5 TRACK The same This period
JUMP period does not exist JUMP period as for a does not exist
1 TRACK JUMP IN (OUT) #4 0.5 TRACK 233 µs 60 ms TOFF =“L” 0.5 TRACK The same 60 ms TOFF =“L”
JUMP period during period C JUMP period as for a during period C
2 TRACK JUMP IN (OUT) None 1 TRACK The same 60 ms
JUMP period as for a
4 TRACK JUMP IN (OUT) 2 TRACK 466 µs 60 ms 2 TRACK The same 60 ms
JUMP period JUMP period as for a
16 TRACK JUMP IN (OUT) 9 TRACK 7 TRACK 60 ms 9 TRACK The same 60 ms
JUMP period JUMP period JUMP period as for a
32 TRACK JUMP IN (OUT) 18 TRACK 14 TRACK 60 ms Same as in the conventional mode
JUMP period JUMP period
64 TRACK JUMP IN (OUT) 36 TRACK 28 TRACK 60 ms Same as in the conventional mode
JUMP period JUMP period
128 TRACK JUMP IN (OUT) 72 TRACK 56 TRACK 60 ms Same as in the conventional mode
JUMP period JUMP period
TOFF is high during the period over
256 TRACK JUMP IN (OUT) which 256 tracks elapse and pulses a 60 ms Same as in the conventional mode
and b are not produced
TRACK JUMP BRAKE There is no a or b period 60 ms Same as in the conventional mode
Slip detector
High during the brake interval

The THLD signal is generated on the LA9230M, 9240M, 9250M Series side, and causes the tracking error signal to
be held during the JP pulse period.
* The tracking brake
The relationship between the TES, HFL, and TOFF signals during the track jump period c is as shown below. The
TOFF signal is generated from the HFL signal with the changing edge of the TES signal. The high of the HFL signal
is for the mirrored area, while the low is for the pitted area. As the beam sweeps from the mirrored surface to the
pitted area, TOFF becomes high, and as the beam sweeps from the pitted area to the mirrored surface, TOFF is made
low in the gain-enhanced state (TGL low), and the brake is applied.
• JP 3-state Output
Using the JP 3-state command, the track jump can be controlled with a single pin, however, the gain must be
increased on the servo side because the kick gain will decrease by 6 dB.
• Track check mode
After the track check IN or track check OUT command has been entered, then when a discretionary number between
8 and 254 is entered as binary data, a track count of the specified number + 1 will be performed.
No. 5995-18/34
LC78626KE
Code COMMAND RES = low
$B6 JP 3-state output
$B7 JP 2-state output (conventional method) ●●
Code COMMAND RES = low
$F0 Track check IN
$F8 Track check OUT
$FF Two byte command reset ●●
TES (when moving towards the outside)
TES (when moving towards the inside)
HFL
TOFF output
2-state output
3-state output High impedance output
The number of desired track checks = the number of track checks input + 1
Command
Track check
Track check
In/Out command Binary input of the desired
number of tracks +1 Double byte
command reset
Rising edge at the
number of tracks/2 Goes low when the track
check is complete.
Brake command

* When the desired number of tracks is entered as a binary number, the track check operation begins with the falling
edge of the RWC.
* During the track check the TOFF pin becomes high and the tracking loop turns off, and thus there is the need to
provide a feed to the feed motor.
* When the track check In/Out commands are entered, the WRQ signal changes from the subcode Q standby monitor
that it is during normal times to become the track check monitor. This signal becomes high when half of the number
of tracks have been checked, and becomes low when the check is complete. The microcontroller sees that the WRQ
signal has become low and determines that the check has been completed.
* If the two-byte reset command is not entered, the track check operation begins again. In other words, if you wished to
advance 20,000 tracks, then a single 201 track check code would be sent and then when 100 cycles of the WRQ have
been counted, then there have been 20,000 track checks.
* When the track check is performed, the brake command is used to lock the pickup to a track.
The Error Flag Output Pin 43: EFLG, Pin 44: FSX
The FSX is the 7.35 kHz frame sync signal that is created by frequency dividing the crystal clock. For each frame, the
error correction status is output to EFLG. It is easy to tell the quality of the playback by the number of high pulses that
appear in the EFLG signal.
The Subcode P, Q and R to W Output Circuits Pin 34: SBCK, Pin 35: SFSY/CONT4, Pin 36: PW/CONT5, Pin 37: SBSY
PW is the subcode signal output pin. (Note: Pin 35 and Pin 36 are, respectively, a general I/O pin and an exclusively
shared pin, and the selection of the pin depends on commands from the micro controller. See the item “General I/O
Ports” on page 24.) By applying 8 clocks to SBCK within 136 µs of the falling edge of SFSY, it is possible to read all
codes until P, Q, and R to W. The signal that appears at the PW pin changes with the rising edge of SBCK. When no
clock is applied to SBCK, the “P” code is output to PW. SFSY is a signal that is output for each subcode frame, and the
falling edge of this signal indicates that the subcode symbol (P to W) output is in standby. The subcode data P is output at
the falling edge of this signal.
SBSY is a signal output for each subcode block. This signal becomes high during sync signals S0 and S1, and its falling
edge indicates the end of the subcode sync signal and the beginning of the data in subcode block (in EIAJ format).
No. 5995-19/34
LC78626KE
1 correction
2 correction
Correction
function
No errors

The Subcode Q Output Circuit Pin 66: WRQ, Pin 62: RWC, Pin 65: SQOUT, Pin 64: CQCK, Pin 15 CS
It is possible to read the subcode Q from the SQOUT pin by inputting a clock into the CQCK pin. Of the 8-bit subcodes,
the “Q” signal is useful in accessing musical selections, in displays, etc. WRQ is only high when the CRC has been
passed and the address in the subcode Q format is “1.” (See Note 1.) When the microcontroller detects this high level, it
can transmit a CQCK signal to read the data from SQOUT in the order shown below. When the CQCK transmission
begins, data changes in the internal registers of the DSP are inhibited. Once the microcontroller has completed its read,
RWC temporarily goes high, enabling data updating. At this time, WRQ goes low. Because WRQ goes low after being
high for 11.2 ms, the CQCK input starts during the interval when WRQ is high. The data can be read beginning with the
least significant bit.
Note 1: This conditions is ignored if an address-free command is sent (corresponding to the CDV).
The items within the parentheses are for the read-in area.
* The WRQ pin normally indicates the subcode Q standby; however, when in the track counter mode and when there is
an internal bake, it becomes a different monitor. (See the track count and internal brake items.)
* This IC becomes active when the CS pin is low, and the subcode Q data is output from the SQOUT pin. When the CS
pin is high, the SQOUT pin enters a high impedance state.
No. 5995-20/34
LC78626KE
Code COMMAND RES = low
$09 ADDRESS FREE
$89 ADDRESS 1 ●●
CONT ADR
TNO
INDEX (POINT)
MIN
SEC
FRAME
ZERO
AMIN (PMIN)
ASEC (PSEC)
AFRAME (PFRAME)
Sub Q data