Semtech SH3000 User manual

SH3000UM version 0.95 2002-08
Copyright ©2002 Semtech Corporation
SH3000 User Manual
Preliminar
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Using the SH3000 MicroBuddy™

SH3000UM version 0.95 2002-08
Copyright ©2002 Semtech Corporation
SH3000 User Manual
Preliminar
y
MicroBuddy, mBuddy, and mB are trademarks of Semtech Corporation. Semtech is a
registered trademark of Semtech Corporation. All other trademarks are the property of
their respective owners.

SH3000 User Manual
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SH3000UM version 0.95 2002-08
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Document Revision History
Revision Date Reason for Changes
Rev. 0.95 2002-08-09 Preliminary draft

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SH3000UM version 0.95 2002-08
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Table of Contents
1. Introduction ............................................................................................................................................ 1
2. CPU Supervisor ..................................................................................................................................... 4
2.1 Low VDD Reset ............................................................................................................................... 5
2.2 Watchdog Timer ............................................................................................................................. 7
2.3 CPU Supervisor Registers.............................................................................................................. 8
3. High-Frequency (HF) Oscillator ........................................................................................................... 10
3.1 Auto Clock Detect Mode ............................................................................................................... 12
3.2 Programmable Spread Spectrum ................................................................................................. 13
3.3 High-Frequency (HF) Oscillator Registers.................................................................................... 14
4. Low-Frequency (LF) Oscillator............................................................................................................. 17
4.1 Low-Frequency (LF) Oscillator Registers ..................................................................................... 18
5. Real-Time Clock (RTC) ....................................................................................................................... 21
5.1 Real-Time Clock (RTC) Registers ................................................................................................ 22
6. Periodic Interrupt/Wake-up Timer........................................................................................................ 23
6.1 Periodic Interrupt/Wake-up Timer Registers ................................................................................ 24
7. Serial Interface ..................................................................................................................................... 25
7.1 Serial Communications Interface.................................................................................................. 25
7.2 Interrupt Interface ......................................................................................................................... 28
7.3 Serial Communication/Interrupt Registers.................................................................................... 28
8. Auxiliary Functions ............................................................................................................................... 30
8.1 Scratchpad RAM and ID number.................................................................................................. 30
8.2 Write Protect Logic ....................................................................................................................... 31
8.3 Voltage Regulator ......................................................................................................................... 33
8.4 Backup Power............................................................................................................................... 33
9. Registers .............................................................................................................................................. 34

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List of Tables
Table 1: SH3000 MicroBuddy™ Pin Descriptions.......................................................................................3
Table 2: Programmable VBO Values (Volts)................................................................................................5
Table 3: Operating Parameters for FLL ....................................................................................................11
Table 4: EMI reduction with Spectrum Spreading .....................................................................................13
Table 5: Load Capacitance Settings .........................................................................................................18
Table 6: Minimum/Maximum Serial Bit Timing..........................................................................................26
Table 7: SH3000 MicroBuddy™ Registers 0x00 to 0x0F..........................................................................34
Table 8: SH3000 MicroBuddy™ Registers 0x10 to 0x17 ..........................................................................35
Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F..........................................................................37
List of Figures
Figure 1: SH3000 MicroBuddy™ Block Diagram ........................................................................................2
Figure 2: CPU Supervisor ...........................................................................................................................4
Figure 3: Operation of Low VDD / Brownout Detector .................................................................................6
Figure 4: Noise Filtering ..............................................................................................................................6
Figure 5: High-Frequency (HF) Oscillator .................................................................................................10
Figure 6: Low-Frequency (LF) Oscillator...................................................................................................17
Figure 7: Real-Time Support: Real-Time Clock (RTC), Periodic Interrupt, & Wake-up Timer .................21
Figure 8: Serial Communication Timing Diagram .....................................................................................27

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1. Introduction
The programmable SH3000 MicroBuddy™ (µBuddy™) provides all mandatory microcontroller support
functions:
· CPU Supervisor
· Clock Management System
· Real-Time Support
· Auxiliary functions
Three components make a complete system: any microcontroller, the SH3000, and a bypass capacitor.
This low-cost system would consume very little power and have clock-frequency accuracy of ±0.5%. A
fourth component, a 32.768 kHz watch crystal, raises the clock frequency accuracy to ± 0.0256% (± 256
ppm).
The SH3000 can operate completely stand-alone, or under control of the microcontroller. A single-wire
interface handles both bi-directional communications and the interrupt / wake-up signal from the SH3000.
The SH3000 stores all configuration, calibration, parameters, and status information in a 36-byte bank of
control registers. On reset, most of these are reloaded with defaults from the factory-set One-Time-
Programmable (OTP) memory. The microcontroller can change any settings on the fly. If some of the
settings must remain fixed, a comprehensive set of write-protect bits is provided for several related groups
of registers (with both permanent write-inhibit and lock/unlock capabilities).
A backup power source may also be connected to the SH3000. The IC can directly accommodate 2/3-cell
zinc-carbon/alkaline, 2/3-cell mercury, 2/3/4-cell NiCd/NiMH, 1-cell Li/Li+ batteries, or a super cap.

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CLK32
Microcontroller
V+
V
DD
32
K
H
Z
X
IN
X
OUT
R
ESET
I/O
PIN
CLK
SEL
V
BA
K
V
REG
LF Oscillator
Select
Logic
Reset Drivers
& Logic
V
DD
Monitor
Watchdog
HF Oscillator
& FLL
Real Time Clock
Periodic Interrupt
/ Wake-up Timer
X
TAL
Oscillator
RC
Oscillator
Regulators &
Battery Back-up
OTP Memory
Calibration &
Default Settings
Serial I/O
Control Logic
8
Clock Driver &
Start/Stop Logic
Post-scaler
2 3
4
9
10
11
12
5
6
7
13
14
1516
Interrupt
V
DD
V
SS
X
IN
X
OUT
Voltage
Reference
CLK
OUT
CLK
IN
R
REF
RST
N
RST
T
EST
IO/I
NT
SH3000 µBuddy™
1
V
SS
Figure 1: SH3000 MicroBuddy™ Block Diagram

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Table 1: SH3000 MicroBuddy™ Pin Descriptions
Pin Name Type Function
1 VSS Power Ground, 0 V. All VSS pins and TEST (VSS)pin must be connected together.
2 VREG Power
Output of internal voltage regulator, 2.2 V nominal. This pin can power external
loads of <5 mA. If load is “noisy,” it requires a bypass capacitor. May be left
unconnected or used as a high logic level signal for CLKSEL pin (see below).
3 VDD Power Main power supply, +2.3 to +5.5 V.
4 VBAK Power
Backup power supply for real-time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical).
This voltage can be higher or lower than VDD. Connect a backup battery or backup
capacitor (with external recharge circuit). Connect to VDD if not used.
5 XIN Analog In
6 XOUT Analog Out
Oscillator pins for an optional external low-frequency crystal, typically a 32.768 kHz
watch crystal with nominal 12.5 pF load capacitance. Keep open or connect to VSS
if not used.
7 CLKSEL Digital In
A logic low level selects the internal 32 kHz RC oscillator (CLKSEL tied to VSS). A
high state on this pin selects the 32 kHz crystal oscillator (CLKSEL is connected to
VREG). The SH3000 always starts up using the internal 32 kHz RC oscillator. If
CLKSEL is high, the internal 32 kHz clock switches to the crystal oscillator once it
has stabilized, and RC oscillator is disabled for power conservation.
Do not connect CLKSEL to any signals except VSS or VREG. CLKSEL must not be
left open.
8 VSS Power Ground, 0 V. All VSS pins and TEST (VSS)pin must be connected together.
9 RREF Analog Optional 1 MOhm external bias resistor for the internal 32 kHz RC oscillator. Can
be used to set, trim or modulate the internal RC oscillator. Keep open if not used.
10 NRST Digital Out
Active low system reset output. Asserted with a strong low state when a reset
condition occurs. Weakly pulled to VDD internally when not active. This signal is
valid for VDD as low as 1 V. Keep open if not used.
11 RST Digital Out
Active high system reset output. Asserted with a strong high state when a reset
condition occurs. Weakly pulled to VSS internally when not active. This signal is
valid for VDD as low as 1 V. Keep open if not used.
12 TEST (VSS) Digital In Factory test enable. All VSS pins and TEST (VSS)pin must be connected together.
13 CLK32 Digital Out
Buffered internal 32 kHz clock, derived according to the CLKSEL pin setting. This pin
uses backup power for the buffer when VDD is not present. When driving high, this
signal is either at VBAK or VDD (if VDD is higher than the reset threshold). When
enabled, this signal runs continuously independent of CLKOUT activity. Minimize the
external load to reduce power consumption during backup operations. When
disabled, this pin is driven to VSS. Keep open if not used.
14 IO/INT I/O
Serial communications interface and interrupt output pin. This pin is internally
weakly pulled to the opposite of the programmed interrupt polarity. For example, if
interrupt is programmed to be active low, this pin is weakly pulled to VDD when
inactive. Keep open if not used.
15 CLKIN Digital In
Clock activity sense input. Used to detect when the target microcontroller enters
stop mode (which disables its clock). Connect to the microcontroller’s clock output
or oscillator output pin. Connect to VSS when not used. CLKIN must not be left
open.
16 CLKOUT Digital Out Programmable high-frequency clock output. Connect to the target microcontroller’s
clock input or oscillator input pin. Keep open if not used.

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2. CPU Supervisor
The SH3000 has two CPU Supervisor functions that manage the reset of the host microcontroller, a low-
VDD monitor (brownout detector) and a watchdog timer (see Figure 2).
Both functions are integrated with the Clock Management System to provide a more complete system
solution than stand-alone components.
The SH3000 has both active high and active low reset output pins. Both are driven strong in the active
state, and weak in the inactive state. This eliminates the need for external pull-ups and allows various
reset sources to be connected together in a wire-OR configuration. (this makes it simple to set up a
manual rest circuit.)
A set of flags in the ResetEvent register (R0x1B) indicates the source of the reset to the system software.
Noise Filter
1
V
DD
V
HIGH
V
LOW
Threshold
D/A
4.40
V
2.30 V
Hysteresis
50mV
TYP
.
Reset Logic
&
Minimum
Duration Timer
PWR
OK
Temperature-
compensated
Voltage
Reference
10
N
RST
11
RST
V
DD
20
K
20
K
U
NDERFLOW
1→0
32kHz
/256
32kHz
CLK
OUT
7-bit Down Counter
/128
Mode6-bit Value 7-bit Watchdog
Timeout Value
Watchdog
Reload Control
Alternating Codes
Logic
0x5A / 0xC3
Load
From / To
Serial I/O
Write-once
Initialization Logic
Lock Logic
R
ESET
R
ESET
Figure 2: CPU Supervisor

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2.1 Low VDD Reset
The SH3000 drives the reset pins active whenever VDD is below the value of VBO, the brownout reset
threshold. VBO can be set using bits 0:5 of the VBOValue register (R0x10). VBO can be set to a value
from 2.30 V to 4.40 V in average increments of 33.33 mV–see Table 2.
Table 2: Programmable VBO Values (Volts)
4.400 4.367 4.333 4.300 4.267 4.233 4.200 4.167
4.133 4.100 4.067 4.033 4.000 3.967 3.933 3.900
3.867 3.833 3.800 3.767 3.733 3.700 3.667 3.633
3.600 3.567 3.533 3.500 3.467 3.433 3.400 3.367
3.333 3.300 3.267 3.233 3.200 3.167 3.133 3.100
3.067 3.033 3.000 2.967 2.933 2.900 2.867 2.833
2.800 2.767 2.733 2.700 2.667 2.633 2.600 2.567
2.533 2.500 2.467 2.433 2.400 2.367 2.333 2.300
The default VBO value is loaded on power-up from the factory-programmed OTP nonvolatile memory. It
can be re-programmed at any time or it can be permanently protected from any changes by setting the
VBO lock flag or an OTP write-protect flag.
On power up, both the active high and active low reset pins are driven active. These outputs are typically
valid for a VDD level of at least 0.5 V, and guaranteed to be valid for a VDD level of 1.0 V.
The reset output pins remain active until VDD rises and stays above the level of VBO + VHYST, where
VHYST is a small fixed amount of hysteresis, nominally 50 mV. This hysteresis is added to prevent false
triggering from noise or small power glitches.
At the threshold level (VBO + VHYST), the power supply is considered valid. On initial power up, the reset
lines become inactive 3–5 ms after power is valid. In the case of brownout, the reset is released after a
delay of 6 ms, but no less than 12 ms from the moment brownout has been detected.
Such a fast reset is possible because the SH3000 provides a fast-starting clock that is free of crystal start-
up time delays. This gives the SH3000 an advantage over other external reset circuits, which must have a
long reset pulse duration to accommodate long and unpredictable crystal start-up times.
The SH3000 guarantees that before the reset signals are inactive a valid and stable clock is available for
at least 1 ms on power up, or 2 ms after brownout, so that internal synchronous reset and initialization of
the host microcontroller can proceed normally.
With the clock becoming active 1-2 ms before the reset lines become inactive, considerable energy is
conserved since the clock is not active during the whole reset period.

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When a brownout event occurs, the SH3000 continues to provide the clock to the host microcontroller, but
at a reduced frequency between 500 kHz and 1.0 MHz. After a delay of 2 ms this clock is stopped,
automatically lowering the energy consumption of the whole system; see Figure 3.
A noise filter prevents the reset lines from going active due to noise and power glitches on the VDD line.
Figure 4 shows typical behavior for the VDD level just above VBO for negative-going spikes of various
duration and amplitude.
VDD
RST
NRST
CLKOUT
1V
V
BO
V
BO
+ V
HYST
3-5ms
12ms minimum
2ms2ms1ms
Undefined
Normal
FOUT
Reduced FOUT
0.5-1.0 MHz
6ms
0
5
10
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.
5
Amplitude, V
Duration, µs
Guaranteed NO reset
Guaranteed reset
Duration
Amplitude
Figure 3: Operation of Low VDD / Brownout Detector Figure 4: Noise Filtering
When VDD power is removed from the chip, the following sequence of events occurs:
1. When VDD drops below the programmed reset threshold, NRST and RST are asserted. Both
reset lines are guaranteed to become active within 5 µs after VDD has crossed the VBO threshold.
2. If VBATT is above 1.5 V to 2.2 V, then the chip switches on to VBATT operation; NRST and RST
remain asserted
3. CLKOUT continues to run at a reduced rate (500 kHz to 1 MHz), provided that VDD stays above
approximately 2.25 V. If VDD falls below this threshold at any time, then CLKOUT is stopped
immediately. If CLKOUT was inactive when the reset condition occurred, it is activated at this
time.
4. If enabled, the CLK32 output continues normal operations when VDD is absent and backup power
is available.
5. 2 ms after VDD drops below the VBO threshold, CLKOUT switches off.
The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in the
ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared
individually by writing a “1” to the relevant bit position; they are not cleared automatically. On a power-on
reset (bit 0), the brownout flag (bit 3) is invariably set also.

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2.2 Watchdog Timer
The Watchdog Timer is part of the CPU Supervisor function of the SH3000. Whereas the low-VDD
Brownout Detector monitors supply voltage, the watchdog timer monitors behavior of the host
microcontroller. It is based on a programmable timer that must be restarted periodically by the host. If the
host does not send a command to restart the timer (which is likely when the host firmware has hung or
failed), the watchdog resets the host.
The watchdog is disabled after reset occurs. It stays disabled until initialized by the host microcontroller.
The initialization requires the watchdog clock mode to be selected (see Figure 2) and the 7-bit time-out
value to be set. Once the time-out value is written, the watchdog begins operations and cannot be
stopped; the time-out value and clock source can no longer be changed.
The two clock sources available for the watchdog are the internal 32 kHz clock and the CLKOUT signal.
The time-out interval can be set with bits 0:6 of the WdogPeriod register (R0x1D). When operating from
the 32 kHz source, the time-out interval is programmable from 7.8125 ms to 1000 ms with a resolution of
7.8125 ms. Since the internal 32 kHz clock is running all the time, the time-out period is fixed and
predictable.
When operating from the CLKOUT signal, the time-out period is programmable between 256 and 32768
cycles with a resolution of 256 cycles. The actual time-out duration is variable; it depends both on the
frequency of CLKOUT and the amount of time the host microcontroller spends in the STOP mode, when
the CLKOUT signal is also stopped. When the CLKOUT signal is stopped, the watchdog is suspended.
These two clock modes, together with the programmable time-out value, allow the SH3000 exceptional
flexibility previously unattainable by discrete watchdog solutions.
The watchdog timer is kept from timing out by periodic writing of a code to the WdogCode register
(R0x1C). As a safety measure, the code values must be alternated between 0x5A and 0xC3. The first
code written to the register must be 0x5A; at the next period, the code 0xC3 must be used, and so forth.
The timer is reloaded after every write of the correct one of these codes.
If the watchdog code is not written before the time-out period expires, or if the code is incorrect or out of
sequence, the SH3000 issues a reset to the microcontroller by asserting both the RST (pin 11) and NRST
(pin 10) lines. The reset state is asserted for 6 ms.

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2.3 CPU Supervisor Registers
RESET
EVENT
RESET
VALUE
ADDRESS
NAME
PowerOn
WDog
BrownOut
HEX
BINARY
DESCRIPTION
P 1 b7 XTALtune Rewrite-Once Enable (see notes for use)
PWB 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1.
PWB 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions.
PWB 0b4CLK
OUT
source. 1 = 32 kHz, 0 = HFCLK.
PWB 1b3CLK
OUT
Enable. 1 = enable, 0 = disable.
PWB 0 b2 WdogClkSelect. 1 = CLK
OUT
, 0 = 32 kHz.
PWB 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.
0x0E
Config
PWB
0x88
0 b0 Interrupt Enable. 1 = enable, 0 = disable.
INIT
EVENT
INIT
VALUE
WRITE
PROTECT
ADDRESS
PAGE
NAME
PowerOn
WDog
BrownOut
HEX
BINARY
IDCode
Calibration
Application
V
BO
Value
Xtal REWRITE-once
DESCRIPTION
-0- b7 Reserved, not used
-0- b6 Reserved, not used
P W ?
V b5
P W ?
V b4
P W ?
V b3
P W ?
V b2
P W ?
V b1
0x10 0 VBOValue
P W
0x??
?V b0
VBO Threshold Value, 2.3 V to 4.4 V in
~33.33 mV steps.
P W ? b7
IDCode Write Protect, 1 = no writes.
P W ?b6 Calibration Write Protect, 1 = no writes.
P W ?b5
A
pplication Write Protect, 1 = no writes.
P W ?b4 VBO Value Write Protect, 1 = no writes.
P W B ? Ab3 CLK32 enable, 1 = enable, 0 = disable.
P W B ? Ab2
P W B ? Ab1
0x17 0 WP_PostScale
P W B
0x??
? Ab0
DCO Post-Scaler, 8 (eight) setting:
/1, 2, 4, 8, 16, 32, 64, 128.

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Note: The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in
the ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared
individually by writing a “1” to the relevant bit position; they are not cleared automatically. On a power-on
reset (bit 0), the brownout flag (bit 3) is invariably set also.
RESET
EVENT
RESET
VALUE
ADDRESS
NAME
PowerOn
WDog
BrownOut
HEX
BINARY
DESCRIPTION
-0- b7
-0- b6
-0- b5
-0- b4
Reserved, not used
P B 0/1 b3 VDD dropped below VBO threshold (brown-out).
W 0/1 b2 Watchdog code violation caused the reset.
W 0/1 b1 Watchdog timeout caused the reset.
0x1B
ResetEvent
P
0x02
0x04
0x08
or
0x09
0/1 b0 Power-on caused the reset.
0x1C
WDogCode P W B
0x00
Alternate writes of code-Bytes 0x5A and 0xC3 are required
to prevent timeout. Watchdog is reloaded after every write
(only one code has to be written to reload the watchdog, but
the value of the code-Byte has to alternate between 0x5A
and 0xC3).
-0- b7 Reserved, not used
P W B 0b6
P W B 0b5
P W B 0b4
P W B 0b3
P W B 0b2
P W B 0b1
0x1D
WDogPeriod
P W B
0x00
0b0
Watchdog timeout value. Depending on WdogClkSelect bit
in the Config register (R0x0E, b2), the watchdog will be
decremented by either a 32 kHz clock or the signal on the
CLKOUT pin (in which case the watchdog will be suspended
when the HFCLK stops). The Watchdog is disabled after the
reset and started by writing to WDogPeriod. Once started,
the clock selection or timeout value cannot be changed.

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3. High-Frequency (HF) Oscillator
The frequency synthesizer in the SH3000 is constructed from the 2:1 digitally-tunable 8.0–16.0 MHz High-
Frequency (HF) oscillator followed by a programmable binary post-divider; see Figure 5.
Post-scaler
(Divide by 1, 2, 4,
8, 16, 32, 64, 128)
32.768 kHz
START/STOP
16
15
CLKOUT
CLKIN
Clock Buffer
and Glue
Logic
HF Digitally
Controlled
Oscillator
8-16 MHz
18-bit
DCO Code
Register
Clock On
Force
DCO On
Clock Source
1
0
Spectrum
Spreading
Controls
Frequency Locked Loop
Logic
13-bit
Frequency
Set value
/16 2048 Hz
8-bit Pseudo
Random Noise
Generator
FLL Enable
From / To
Serial I/O
Figure 5: High-Frequency (HF) Oscillator
The Clock Source selector and the programmable Post-scaler allow instantaneous switching between
the 32 kHz internal clock and the divided-down HF oscillator output. There is no settling or instability when
the switch occurs.
The SH3000 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32 kHz
reference. This architecture has several advantages over the common PLL (Phase Lock Loop) systems,
including the ability to stop and re-start without frequency transients and instability, and with instant settling
to a correct frequency. The conventional PLL approach invariably includes a low-pass filter that requires a
long settling time on restart.
When the HF oscillator is operating without FLL control, it can set the frequency of the clock on the
CLKOUT pin to ±0.025%, and maintain it to ±0.5% over temperature.
When the HF oscillator is operating under FLL control, the absolute accuracy and stability of the HF clock
depends on the quality of the 32.768 kHz internally generated clock. An external 32.768 kHz watch crystal
used as a reference provides excellent accuracy and stability for the SH3000.
The primary purpose of the FLL is the maintenance of the correct frequency while the ambient
temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action
from the FLL system is also small and gradual, in proportion with the changes in temperature.
To set a new frequency for the FLL, the host microcontroller writes the 13-bit Frequency Set value to the
appropriate bits in registers SS_FreqSet (R0x15) and FreqSetLSB (R0x16); it may also update the post-
scaler setting in the WP_PostScale register (R0x17). The resulting output frequency is calculated using
simple formulas [1] and [2] (reference frequency is 32.768 kHz):
FOSC = 2048 Hz * (Frequency Set value + 1) [1]
FOUT = FOSC / (Post-divider setting) [2]

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For example, a post-divider setting of /8 and the Frequency Set value of 4000 (0x0FA0) produce an output
frequency of 1.024 MHz. Table 3 shows the available frequencies with the corresponding resolution at
high and low frequency limits.
Table 3: Operating Parameters for FLL
Frequency Range
Post-
divider
Frequency
Resolution
Hz
High
(Guaranteed)
Hz
Low
(Guaranteed)
Hz
Low
(Typical)
Hz
/1 2048 16,777,216 7,999,488 6,144,000
/2 1024 8,388,608 3,999,744 3,072,000
/4 512 4,194,304 1,999,872 1,536,000
/8 256 2,097,152 999,936 768,000
/16 128 1,048,576 499,968 384,000
/32 64 524,288 249,984 192,000
/64 32 262,144 124,992 96,000
/128 16 131,072 62,496 48,000
Dec 8191 3905 2999
Frequency Set
value Hex 0x1FFF 0x0F41 0x0BB7
% 0.01221 0.02560 0.03333
Resolution ppm 122 256 333
When the Frequency Set value changes, the FLL synthesizer needs some settling time to lock the new
frequency. There are several possible methods for decreasing this time:
1. The host microcontroller may simply wait for the FLL to lock, checking the FLL lock flag (bit 0) in
the Status register (R0x1A). This approach is the simplest but also the slowest. Depending on
the frequency step it may take up to two seconds to obtain the lock. The frequency change from
the old to the new value is slow and gradual.
2. The host may issue a Coarse Lock command by setting the coarse lock bit (bit 1) in the
FLLcontrol register (R0x0F). The SH3000 performs a successive approximation algorithm on
the 18-bit DCO (digitally controlled oscillator) code value (contained in registers R0x13, R0x14,
and R0x18) and finds a locked setting in approximately 25 ms. The clock may experience
frequency fluctuations of up to 2:1.
3. If the frequency step is small (less than 256 kHz at the undivided output of the HF oscillator), the
host may issue a fine lock command by setting the fine lock bit (bit 2) in the FLLcontrol register.
The SH3000 performs a successive approximation algorithm on the 7 least significant bits of the
18-bit DCO code value, and finds a locked setting in approximately 5 ms. The clock may
experience the maximum frequency fluctuations of only 3.2%.
4. The host may write the new value into the DCO code registers to directly control the frequency of
the HF oscillator. This method is preferable and results in minimum settling time. The 18-bit
DCO code value can be obtained from programming the HF oscillator to a correct frequency using
method 2 or 3 above (at start-up or at some point in the operation), reading the value from the
DCO code registers, and storing the value in the host’s memory. This calibration should be
performed for each of the frequencies to be employed. This method allows the locking time to be
as small as 1 or 2 ms, independent of the frequency step.

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5. The host may perform a custom or proprietary algorithm for frequency control; the SH3000
provides all of the information, reference, and timing signals needed.
During each of the settling methods described above, the processor clock can be switched to 32 kHz, and
would be completely free of any frequency fluctuations or instabilities. Since the SH3000 automatically
shuts down the HF oscillator when 32 kHz is selected as the output frequency, the HF oscillator should be
forced to an active state by setting the Force DCO On bit (bit 5) in the Config register (R0x0E).
Systems requiring a very stable clock for short periods of time (controlling an integrating D/A converter, for
example), may stop the FLL action in the SH3000 by resetting the FLL enable bit (bit 0) in the FLLcontrol
register (R0x0F).
3.1 Auto Clock Detect Mode
The SH3000 HF oscillator block has two main modes with which to operate.
1. Mode 1 provides a system clock source. In this mode the CLKOUT pin supplies a clock at the
frequency configured by the register settings. It can be enabled/disabled by setting/resetting the
CLKOUT pin enable bit (bit 3) of the Config register (R0x0E).*
2. Mode 2 provides a CPU oscillator source. In this mode, the CLKOUT pin supplies a clock
frequency configured by the register settings. It can be enabled/disabled by setting/resetting the
CLKOUT pin enable bit of the Config register.* When the host microcontroller enters stop mode,
the SH3000 CLKIN pin detects the absence of transitions from the host oscillator output pin, and
shuts down the CLKOUT pin within four clock cycles to save power. At this time the SH3000
configures the CLKOUT pin in such a way that as soon as the host exits stop mode via a reset or
interrupt signal, the CLKIN pin receives a transition. When this occurs, the SH3000 restarts the
clock within 2 ms. This happens much faster than with a standard crystal or a ceramic resonator,
faster even than with an LC tank circuit. This is a key feature of low-power operation of the
SH3000.
The operating mode is determined by CLKIN. If the SH3000 detects at least four transitions on the CLKIN
pin, it assumes Mode 2 is in effect and configures itself to auto-clock detect. This also sets the
corresponding bit (bit 4) in the Status register (R0x1A).
* As programmatically disabling the CLKOUT pin causes the clock to be irrecoverable, the periodic timer
must be set and enabled before this is done. The SH3000 does not disable the clock unless the periodic
timer is enabled.

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3.2 Programmable Spread Spectrum
The SH3000 offers a technique for reducing electromagnetic interference (EMI). It can be a part of the
initial design strategy, or it can be applied in the prototype stage to fix problems identified during
compliance testing. This feature of the SH3000 may greatly reduce the requirements for radio frequency
(RF) shielding, and permits the use of simple plastic casings in place of expensive RFI-coated or metal
casings.
The SH3000 employs programmable spectrum spreading to reduce RF emissions from the processor’s
clock. There are five possible settings; see Table 4 for operating and performance figures in the 8–16
MHz range.
Spectrum spreading is implemented by varying the frequency of the HF oscillator with a pseudo-random
sequence (with a zero-average DC component). The Maximum-Length Sequence (MLS) 8-bit random
number generator, clocked by 32 kHz, is used. Only 4, 5, 6, or 7 bits of the generated 8-bit random
number are used, according to the configuration setting.
Maximum fluctuations of the frequency depend on the selected frequency range and the position within
the range. Selecting the HF oscillator frequency near the high end of the range limits the peak variations
to ±0.1%, ±0.2%, ±0.4%, or ±0.8%.
The spread spectrum values are set in the SS_FreqSet register (R0x15). Bit 5 enables spectrum
spreading, and bits 7:6 specify the spreading bandwidth.
Table 4: EMI reduction with Spectrum Spreading
Setting
En
b5
CFG1
b7
CFG0
b6
Spreading
Bandwidth
kHz
Peak EMI
Reduction
(guaranteed)
db
Peak EMI
Reduction
(measured)
db
0 X X Off 0 0
1 0 0 32 -3 -3
1 0 1 64 -6 -7
1 1 0 128 -9 -10
1 1 1 256 -12 -15

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3.3 High-Frequency (HF) Oscillator Registers
RESET
EVENT
RESET
VALUE
ADDRESS
NAME
PowerOn
WDog
BrownOut
HEX
BINARY
DESCRIPTION
P XTALtune Rewrite-Once Enable (see notes for use)
PWB 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1.
PWB 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions.
PWB 0b4CLK
OUT source. 1 = 32 kHz, 0 = HFCLK.
PWB 1b3CLK
OUTEnable. 1 = enable, 0 = disable.
PWB 0 b2 WdogClkSelect. 1 = CLKOUT, 0 = 32 kHz.
PWB 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.
0x0E
Config
PWB
0x88
0 b0 Interrupt Enable. 1 = enable, 0 = disable.
-0- b7 Reserved, not used
-0- b6 Reserved, not used
-0- b5 Reserved, not used
-0- b4 Reserved, not used
-0- b3 Reserved, not used
PWB 0 b2 Start FLL fine frequency lock (~5 ms to achieve lock).
PWB 0 b1 Start FLL coarse frequency lock (~25 ms to achieve lock).
0x0F
FLLcontrol
PWB
0x00
or
0x01
0/1 b0 Enable FLL. 1 = enabled, 0 = disabled. On Reset =pin CLKSEL.
1 b7
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