Siemens C75 Setup guide

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Service Repair Documentation
Level 2.5e – C75 Release 1.0
Service Repair Documentation
Level 2.5e – C75
Release Date Department Notes to change
1.0 05.08.2005 ICM MP CCQ GRM T New document

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Level 2.5e – C75 Release 1.0
Table of Contents:
1List of available level 2,5e parts C75 4
2Required Equipment for Level 2,5e 5
3Required Software for Level 2,5e 5
4Radio Part 6
4.1 BLOCK DIAGRAM RF PART 7
4.2 POWER SUPPLY RF-PART 7
4.3 FREQUENCY GENERATION 8
4.4 RECEIVER 11
4.5 TRANSMITTER 12
4.6 BRIGHT IC OVERVIEW 13
4.7 ANTENNA SWITCH (ELECTRICAL/MECHANICAL) 15
4.8 TRANSMITTER:POWER AMPLIFIER 17
5Logic / Control 18
5.1 OVERVIEW HARDWARE STRUCTURE C75 18
5.2 SGOLDLITE 18
5.2.1 Digital Baseband 18
5.2.2 SDRAM 22
5.2.3 FLASH 23
5.2.4 SIM 23
5.2.5 Vibration Motor 23
5.2.6 Camera 23
5.2.7 Display 23
5.2.8 Camera, Display ASIC 24
6IRDA 24
7Power Supply 25
7.1 ASIC MOZART /TWIGO4 25
7.1.1 Battery 25
7.1.2 Charging Concept 25
8Illumination 28
9Interfaces 29
9.1 MICROPHONE (XG1901) 29
9.2 LOUDSPEAKER (XG1702-XG1703) 30
9.3 BATTERY (X1400) 30

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9.4 CAMERA SOCKET (X3651) 31
9.5 IRDA (V2650) 32
9.6 INTERFACE SIM MODULE 32
9.7 IO CONNECTOR WITH ESD PROTECTION 33
9.8 VIBRATION MOTOR (XG2100) 36
9.9 DISPLAY 36
9.10 BOARD TO BOARD CONNECTOR 37

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Level 2.5e – C75 Release 1.0
1 List of available level 2,5e parts C75
(according to Component Matrix V1.06 - check C-market for updates)
Product RF
Chipset ID Order Number Description CM
C75 HIT C1329 L36344-F1225-M12 CAPACITOR 2*2U2 (Cap-Type7)
C75 HIT C1330 L36344-F1225-M12 CAPACITOR 2*2U2 (Cap-Type7)
C75 HIT C1332 L36344-F1225-M12 CAPACITOR 2*2U2 (Cap-Type7)
C75 HIT C1363 L36377-F6225-M CAPACITOR 2U2 (Cap-Type4)
C75 HIT D1000 L50610-G6196-D670 IC SGOLDLITE PMB8875 V1X PB-FREE
C75 HIT D1300
L50645-J4683-Y22 IC ASIC D1094ED-MOZART+ TWIGO4+
C75 HIT D3601 L50620-U6053-D670 IC CAMERA INTERFACE S1D13716B02 PB FREE
C75 HIT D902
L50645-K80-Y308 IC FEM MURATA GSM900 1800 1900 (Fem-Type6)
C75 HIT D903 L50620-L6170-D670 IC TRANCEIVER HD155165BP PB Free
C75 HIT L1300 L36140-F2100-Y6 COIL 0603 (Co-Type4)
C75 HIT L1301 L36151-F5103-M3 COIL 10U (Co-Type1)
C75 HIT L1302 L36151-F5472-M1 COIL 4U7 (Co-Type3)
C75 HIT L1303 L50640-F100-Y10 COIL 1206 (Co-Type5)
C75 HIT L1318 L36140-F2100-Y6 COIL 0603 (Co-Type4)
C75 HIT L1331 L36140-F2100-Y6 COIL 0603 (Co-Type4)
C75 HIT N1501 L36810-B6132-D670 IC LOGIC DUAL BUS SWITCH US8
C75 HIT N3600 L506810-C6153-D670 IC ANA RE 2.9V USMD5 PB FREE
C75 HIT N901 L50651-Z2002-A82 IC MODUL PA PF0814 (PA-Type2)
C75 HIT R955 L36120-F4223-H RESISTOR TEMP 22K (Res-Type7)
C75 HIT V1305 L36830-C1107-D670 TRANSISTOR SI5933 (Tra-Type2)
C75 HIT V1400 L36840-D66-D670 DIODE BAV99T (Di-Type5)
C75 HIT V1500 L36840-C4057-D670 TRANSISTOR EMD12 EMT6 (Tra-Type8)
C75 HIT V1605 L36840-D3088-D670 DIODE SC89 (Di-Type2)
C75 HIT V2100 L50640-D5084-D670 DIODE RB548W (Di-Type8)
C75 HIT V2302 L36840-C4014-D670 TRANSISTOR BC847BS BC846S (Tra-Type7)
C75 HIT V2821 L36830-C1112-D670 TRANSISTOR SI1902 (Tra-Type4)
C75 HIT V950 L36840-D61-D670 DIODE 1SV305 (Di-Type4)
C75 HIT Z1000 L50645-F102-Y40 QUARZ 32,768KHZ (Q-Type4)
C75 HIT Z1500 L50620-L6151-D670 FILTER EMI (Fi-Type5) PB Free
C75 HIT Z950 L36145-F260-Y17 QUARZ 26MHZ (Q-Type4)

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Level 2.5e – C75 Release 1.0
2 Required Equipment for Level 2,5e
- GSM-Tester (CMU200 or 4400S incl. Options)
- PC-incl. Monitor, Keyboard and Mouse
- Bootadapter 2000/2002 (L36880-N9241-A200)
- Adapter cable for Bootadapter due to new Lumberg connector (F30032-P226-A1)
- Troubleshooting Frame A62/A65(C75/A75) (F30032-P405-A1)
- Power Supply
- Spectrum Analyser
- Active RF-Probe incl. Power Supply
- Oscilloscope incl. Probe
- RF-Connector (N<>SMA(f))
- Power Supply Cables
- Dongle (F30032-P28-A1) if USB-Dongle is used a special driver for NT is required
- BGA Soldering equipment
Reference: Equipment recommendation V1.6
(downloadable from the technical support page)
3 Required Software for Level 2,5e
- Windows XP
- X-Focus version XX or higher
- GRT Version 3 or higher
- Internet unblocking solution (JPICS)

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Level 2.5e – C75 Release 1.0
4 Radio Part
The radio part is realizes the conversion of the GMSK-HF-signals from the antenna to the
baseband and vice versa.
In the receiving direction, the signals are split in the I- and Q-component and led to the D/A-
converter of the logic part. In the transmission direction, the GMSK-signal is generated in an
Up Conversion Modulation Phase Locked Loop by modulation of the I- and Q-signals which
were generated in the logic part. After that the signals are amplified in the power amplifier.
Transmitter and Receiver are never active at the same time. Simultaneous receiving in the
EGSM900 and GSM1800 band is impossible. Simultaneous transmission in the EGSM900
and GSM1800 band is impossible, too. However the monitoring band (monitoring timeslot) in
the TDMA-frame can be chosen independently of the receiving respectively the transmitting
band (RX- and TX timeslot of the band).
The RF-part is dimensioned for triple band operation (EGSM900, DCS1800, PCS19000)
supporting GPRS functionality up to multiclass 10.
The RF-circuit consists of the following components:
•Hitachi Bright 6E chip set (HD155165BP) with the following functionality:
oPLL for local oscillator LO1 and LO2 and TxVCO
oIntegrated local oscillators LO1, LO2
oIntegrated TxVCO
oDirect conversion receiver including LNA, DC-mixer, channel filtering and
PGC-amplifier
o26 MHz reference oscillator
•Transmitter power amplifier with integrated power control circuitry
•Frontend-Module including RX-/TX-switch and EGSM900 / DCS1800 / PCS 1900
receiver SAW-filters
•Quartz and passive circuitry of the 26MHz VCXO reference oscillator

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Level 2.5e – C75 Release 1.0
4.1 Block diagram RF part
4.2 Power Supply RF-Part
The voltage regulator for the RF-part is located inside the ASIC D1300. It generates the
required 2,8V “RF-Voltages” named VDD_RF1 and VDD_RF2. VDD_RF2 is passed via a 0Ω
resistor and renamed as VDD_BRIGHT as operating voltage for the BRIGHT. The voltage
regulator is activated as well as deactivated via VCXOEN_UC (Functional F23) provided by the
SGOLDlite. The temporary deactivation is used to extend the stand by time.

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Level 2.5e – C75 Release 1.0
4.3 Frequency generation
The C75 mobile is using a reference frequency of 26MHz. The generation of the 26MHz
signal is done via a VCO (Z950). TP (test point) of the 26MHz signal is the TP 820
The oscillator output signal 26MHz_RF is directly connected to the BRIGHT IC (ball B9) to be
used as reference frequency inside the Bright (PLL). The signal leaves the Bright IC as
RF_SIN26M (ball G9)to be further used from the SGOLDlite (D1000(Functional AE15)).
VCXO Out
SGOLDlite In
Bright 6E
To compensate frequency drifts (e.g. caused by temperature) the oscillator frequency is
controlled by the (RF_AFC) signal, generated through the internal SGOLDlite (D1000 (A10))
PLL. Reference for the “EGOLD-PLL” is the base station frequency received via the
Frequency Correction Burst.
The required voltage VDD_RF2 is provided by the ASCI D1300
Waveform of the AFC_PNM signal from SGOLDlite to Oscillator
SGOLDlite
GND GND
R2
RF_AFC
Signalform
C1
C2
AFC_PNM
GND
C3
R3
1 2 3
1 2 3
R1

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Synthesizer: LO1
First local oscillator (LO1) consists of a PLL and VCO inside Bright (D903) and an internal
loop filter
RF PLL
The frequency-step is 400 kHz in GSM1800 mode and 800kHz in EGSM900 mode due to the
internal divider by two for GSM1800 and divider by four for EGSM900. To achieve the
required settling-time in GPRS operation, the PLL can operate in fastlock-mode a certain
period after programming to ensure a fast settling. After this the loopfilter and currents are
switched into normal-mode to get the necessary phasenoise-performance. The PLL is
controlled via the tree-wire-bus of Bright VI E.
RFVCO (LO1)
The first local oscillator is needed to generate frequencies which enable the transceiver IC to
demodulate the receiver signal and to perform the channel selection in the TX part. The VCO
module is switched on with the signal PLLON. The full oscillation range is divided into 256
sub-bands To do so, a control voltage for the LO1 is used, gained by a comparator. This
control voltage is a result of the comparison of the divided LO1 and the 26MHz reference
Signal. The division ratio of the dividers is programmed by the SGOLDlite, according to the
network channel requirements.

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Matrix to calculate the TX and RX frequencies C75:
Band RX / TX Channels RF frequencies LO1 frequency IF freq.
EGSM 900 Receive: 0..124 935,0 - 959,8 MHz LO1 = 4*RF
EGSM 900 Transmit: 0..124 890,0 - 914,8 MHz LO1 = 4*(RF+IF) 80,0 MHz
EGSM 900 Receive: 975..1023 925,2 - 934,8 MHz LO1 = 4*RF
EGSM 900 Transmit: 975..1023 880,2 - 889,8 MHz LO1 = 4*(RF+IF) 82,0 MHz
GSM 1800 Receive: 512..661 1805,2 - 1835,0 MHz LO1 = 2*RF
GSM 1800 Transmit: 512..661 1710,2 - 1740,0 MHz LO1 = 2*(RF+IF) 80,0 MHz
GSM 1800 Receive: 661..885 1835,0 - 1879,8 MHz LO1 = 2*RF
GSM 1800 Transmit: 661..885 1740,0 - 1784,8 MHz LO1 = 2*(RF+IF) 82,0 MHz
GSM 1900 Receive: 512..810 1930,2 - 1989,8 MHz LO1 = 2*RF
GSM 1900 Transmit: 512..810 1850,2 - 1909,8 MHz LO1 = 2*(RF+IF) 80,0 MHz
Synthesizer: LO2
The second local oscillator (LO2) consists of a PLL and VCO inside Bright (D903) and an
internal loop filter. Due to the direct conversion receiver architecture, the LO2 is only used for
transmit-operation. The LO2 covers a frequency range of at least 16 MHz (640MHz –
656MHz).
Before the LO2-signal gets to the modulator it is divided by 8. So the resulting TX-IF
frequencies are 80/82 MHz (dependent on the channel and band). The LO2 PLL and power-
up of the VCO is controlled via the tree-wire-bus of Bright (SGOLDlite signals RF_DAT;
RF_CLK; RF_STR). To ensure the frequency stability, the 640MHz VCO signal is compared
by the phase detector of the 2nd PLL with the 26Mhz reference signal. The resulting control
signal passes the external loop filter and is used to control the 640/656MHz VCO.
The required voltage VDD_BRIGHT is provided by the ASIC D1300

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Level 2.5e – C75 Release 1.0
4.4 Receiver
Receiver: Filter to Demodulator
The band filters are located inside the frontend module (D902). The filters are centred to the
band frequencies. The symmetrical filter output is matched to the LNA input of the Bright .The
Bright 6E incorporates three RF LNAs for GSM850/EGSM900, GSM1800 and GSM1900
operation. The LNA/mixer can be switched in High- and Low-mode to perform an
amplification of ~ 20dB. For the “High Gain“ state the mixers are optimised to conversion gain
and noise figure, in the “Low Gain“ state the mixers are optimised to large-signal behavior for
operation at a high input level. The Bright performs a direct conversion mixers which are IQ-
demodulators. For the demodulation of the received GSM signals the LO1 is required. The
channel depending LO1 frequencies for 1800MHz/1900MHz bands are divided by 2 and by 4
for 850MHG/900MHz band. Furthermore the IC includes a programmable gain baseband
amplifier PGA (90 dB range, 2dB steps) with automatic DC-offset calibration. LNA and PGA
are controlled via SGOLDlite signals RF_DAT; RF_CLK; RF_STR (RF CTRL B10, C8, B12). The
channel-filtering is realized inside the chip with a three stage baseband filter for both IQ
chains. Only two capacitors which are part of the first passive RC-filters are external. The
second and third filters are active filters and are fully integrated. The IQ receive signals are
fed into the A/D converters in the EGAIM part of SGOLDlite. The post-switched logic
measures the level of the demodulated baseband signal and regulates the level to a defined
value by varying the PGA amplification and switching the appropriate LNA gains.
From the antenna switch, up to the demodulator the received signal passes the following
blocks to get the demodulated baseband signals for the SGOLDlite:
Demodulator PGC
LNA
Filter
D903 Bright(D903)
The required voltage VDD_BRIGHT is provided by the ASIC D1300

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Level 2.5e – C75 Release 1.0
4.5 Transmitter
Transmitter: Modulator and Up-conversion Loop
The generation of the GMSK-modulated signal in Bright (D903) is based on the principle of
up conversion modulation phase locked loop. The incoming IQ-signals from the baseband
are mixed with the divided LO2-signal. The modulator is followed by a lowpass filter (corner
frequency ~80 MHz) which is necessary to attenuate RF harmonics generated by the
modulator. A similar filter is used in the feedback-path of the down conversion mixer.
With help of an offset PLL the IF-signal becomes the modulated signal at the final transmit
frequency. Therefore the GMSK modulated rf-signal at the output of the TX-VCOs is mixed
with the divided LO1-signal to a IF-signal and sent to the phase detector. The I/Q modulated
signal with a center frequency of the intermediate frequency is send to the phase detector as
well.
The output signal of the phase detector controls the TxVCO and is processed by a loop filter
whose components are external to the Bright. The TxVCO which is realized inside the Bright
chip generates the GSMK modulated frequency.
TxVCO
Filter PD
Modulator
Bright(D903)
The required voltage VDD_BRIGHT is provided by the ASIC D1300

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4.6 Bright IC Overview
BRIGHT 6E
IC Overview

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IC top view (ball overview)

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4.7 Antenna switch (electrical/mechanical)
Internal/External <> Receiver/Transmitter
The C75 mobile have two antenna switches.
a) The mechanical antenna switch for the differentiation between the internal and
external antenna.
b) The electrical antenna switch, for the differentiation between the receiving and
transmitting signals.
To activate the correct tx pathes of this diplexer, the SGOLDlite signals RF_FE_DTR_GSM
and RF_FE_DTR_DCS are required.
Internal/External antenna switch
The electrical antenna switch

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Level 2.5e – C75 Release 1.0
Top View :
Switching Matrix:
select mode Vsw 1 Vsw 2
GSM900/DCS1800/PCS1900 RX Low Low
EGSM TX high Low
DCS1800/PCS1900 TX Low High
Pin assignment:
1 Antenna 15 EGSM900 RX1
2 GND 16 EGSM900 RX2
3 Vsw2 (DCS1800/PCS1900 TX control) 17 DCS1800 RX1
4 GND 18 DCS1800 RX2
5 DCS1800/PCS1900 TX 19 PCS1900 RX1
6 GND 20 PCS1900 RX2
7 GND 21 GND
8 GND 22 GND
9 GND 23 GND
10 GND 24 GND
11 GND 25 GND
12 GND 26 Vsw1 (EGSM900 TX control)
13 GND 27 EGSM900 TX
14 28 GND

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4.8 Transmitter: Power Amplifier
The output signals (PCN_PA_IN , and GSM_PA_IN) from the TxVCO are led to the power
amplifier. The power amplifier is a PA-module N901 from Hitachi. It contains two separate 3-
stage amplifier chains GSM850/EGSM900 and GSM1800/GSM1900 operation. It is possible
to control the output-power of both bands via one VAPC-port. The appropriate amplifier chain
is activated by a logic signal RF_BAND_SW (TDMA Timer A10) which is provided by the SGOLDlite.
To ensure that the output power and burst-timing fulfills the GSM-specification, an internal
power control circuitry is use. The power detect circuit consists of a sensing transistor which
operates at the same current as the third RF-transistor. The current is a measure of the
output power of the PA. This signal is square-root converted and converted into a voltage by
means of a simple resistor. It is then compared with the RF_RAMP1 (Analoq Interface L24) signal.
The N901 is activated through the signal RF_TXONPA (TDMA Timer A17).
The required voltage BATT+ is provided by the battery.

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Level 2.5e – C75 Release 1.0
5 Logic / Control
5.1 Overview Hardware Structure C75
5.2 SGOLDLITE
5.2.1 Digital Baseband
Baseband Processor SGOLDlite (PMB8875)
S-GOLDliteTM is a GSM single chip mixed signal baseband IC containing all analog and
digital functionality of a cellular radio. The integrated circuit contains a ARM926EJ-S CPU
and a TEAKLite DSP core. The ARM926EJ-S is a powerful standard controller and
particularly suited for wireless systems. It is supported by a wide range of tools and
application SW. The TEAKLite is an established DSP core for wireless applications with
approved firmware for GSM signal processing. The package is a P-LFBGA-345 (264
functional pins + 81 thermical balls).

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Level 2.5e – C75 Release 1.0
Supported Standards
•GSM speech FR, HR, EFR and AMR-NB
•GSM data 2.4kbit/s, 4.8kbit/s, 9.6kbits, and 14.4kbit/s
•HSCSD class 10
•GPRS class 12
Processing cores
•ARM926EJ-S 32-bit processor core with operating frequency up to 125 MHz for
controller functions
•TEAKLite DSP core with operating frequency 104 MHz.
ARM-Memory
•8 kByte Boot ROM on the AHB
•96 kByte SRAM on the AHB, flexibly usable as program or data RAM
•8 kByte Cache for Program (internal)
•8 kByte tightly coupled memory for Program (internal)
•8 kByte Cache for Data (internal)
•8 kByte tightly coupled memory for Data (internal)
TEAKLite-Memory
•80 kwords Program ROM
•4 kwords Program RAM
•48 kwords Data ROM
•27 kwords Data RAM
Shared Memory Blocks
•1.5 kwords Shared RAM (dual ported) between controller system and TEAKLite.
Functional Hardware blocks
•CPU and DSP Timers
•Programmable PLL with additional phase shifters for system clock generation
•GSM Timer Module that off-loads the CPU from radio channel timing
•GMSK Modulator according to GSM-standard 05.04 (5/2000)
•Hardware accelerators for equalizer and channel decoding
•Advanced static and dynamic power management features including TDMA-Frame
synchronous low-power mode and enhanced CPU modes (idle and sleep modes)

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Level 2.5e – C75 Release 1.0
•
Interfaces and Features
•Keypad Interface for scanning keypads up to 6 rows and 4 columns
•Pulse Number Modulation output for Automatic Frequency Correction (AFC)
•Serial RF Control Interface; support of direct conversion RF
•2 USARTs with autobaud detection and hardware flow control
•IrDA Controller integrated in USART0 (with IrDA support up to 115.2 kbps)
•1 Serial Synchronous SPI compatible interfaces in the controller domain
•1 Serial Synchronous SPI compatible interface in the TEAKLite domain
•I2C-bus interface (e.g. connection to S/M-Power)
•2 bidirectional and one unidirectional I2S interface accessible from the TEAKLite
•USB V1.1 mini host interface for full speed devices with up to 5 interfaces and 10
endpoints configurable supporting also USB on-the-go functionality
•ISO 7816 compatible SIM card interface
•Enhanced digital (phase linearity, adj/ co-channel interference) baseband filters,
including analog prefilters and high resolution analog-to-digital converters.
•Separate analog-to-digital converter for various general purpose measurements like
battery voltage, battery, VCXO and environmental temperature, battery technology,
transmission power, offset, onchip temperature, etc.
•Ringer support for highly oversampled PDM/PWM input signals for more versatility in
ringer tone generation
•RF power ramping functions
•DAI Interface according to GSM 11.10 is implemented via dedicated I2S mode
•26 MHz master clock input
•External memory interface:
–1.8V interface
–Data bus: 16 bit non-multiplexed and multiplexed, 32 bit multiplexed
–Supports synchronous devices (SDRAMs and Flash Memory) up to 62.4 MHz
–For each of the 4 address regions 128 MByte with 32-bit access or 64 MByte with a
16-bit access are addressable
–Supports asynchronous devices (i.e. SRAM, display) including write buffer for
cache line write
•Port logic for external port signals
•Comprehensive static and dynamic Power Management
–Various frequency options during operation mode
–32 kHz clock in standby mode
–Sleep control in standby mode
–RAMs and ROMs in power save mode during standby mode
–Additional leakage current reduction in standby mode possible by switching off the
power for the TEAKLite subsystem.