Siemens SMP16-CPU06 Series User manual

SICOMP Industrial Microcomputer
(4)J31069-D2085-U001-A2-7618
Technical Description
Order No.: 6AR1930-0AA07-2CA0 February 2001
SMP16-CPU06x
SMP16-CPU065, SMP16-CPU066
SMP16-AT CPU Boards with Pentium II/III Processor

SMP16-CPU06x
©Siemens AG 2001, All Rights Reserved
2(4)J31069-D2085-U001-A2-7618
List of changes to the technical description
Release 1) Overview of Changes Date of
Release
A0 First edition 11/99
A1 Addition of KS02 functions 07/00
A2 Addition of theSMP16-CPU066 02/01
1Is the 4th block of digits of the drawing number in the footer
Explanation of the notation
* / # An asterisk or a pound character behind the name of a signal indicates a low-active signal
(e.g., IOR* / FRAME#).
/A slash between two signal names separates two level-dependent functions of a signal.
(Example: C/D* means high level for a "command" and low level for "data").
–Connections indicated with a dash in a plug connector allocation table (bus or I/O interface)
are reserved.
Signal Special signals not included in the specifications are shown in bold type in the signal
allocation tables and then explained at the end (e.g., NMI).
Notes:
SICOMP® is a registered brand of Siemens AG.
IBM AT® and IBM PC® are registered brands of International Business Machines Corp.
INTEL® is a registered brand of INTEL Corp.
MS-DOS®, Windows® and Windows NT® are registered brands of Microsoft.
All other designations in this documentation may be brands whose use by third parties for their own purposes may violate the
rights of the owner.
Passing on and duplication of this document as well as use and revelation of its contents is not permitted without express
permission. Violators will be subject to damage claims. All rights reserved, particularly in the event a patent is granted or a utility
model is registered.
With respect to freedom from rights of third parties, no liability is assumed for the specified circuits, descriptions and tables.
Technical descriptions specify products but do not guarantee characteristics. The product described in this documentation may
require licensing. Please check with your Siemens office.
Subject to delivery capacity and technical changes without prior notice TD1/Ka/WW8.0/VS5.0/A4

SMP16-CPU06x
©Siemens AG 2001, All Rights Reserved
(4)J31069-D2085-U001-A2-7618 3
Notes on safety for SICOMP boards
Qualified personnel
A device may only be commissioned and operated by qualified personnel. For the purposes of the
safety notes in this manual, qualified personnel are persons who are authorized to commission,
ground and tag devices, systems and electrical circuits in accordance with safety standards.
ESD protective measures
Caution
Always adhere to ESD (Electrostatic Sensitive Device) guidelines when handling boards
and other components
marked with this symbol.
•Never touch the boards unless necessary work makes this unavoidable.
•When handling the boards, use a conductive and grounded work surface.
•Wear a grounding bracelet.
•Never touch chip pins, component connections or circuit board conductors when handling the boards.
•Never allow boards or components to touch chargeable objects (plastics).
•Never place components or boards in the vicinity of cathode ray tube units or television sets (minimum
distance: 10 cm).
•Leave the boards in their special packaging until you are ready to use them. Do not take the boards out of
their packaging or touch them when registering them and so on.
•Boards may only be installed or removed when the power is off.
Wiring of bus backplanes
System-related signal wiring is done with wrap connections for SICOMP board systems. The power
supply cables are plug-in or screw-type connections which are bundled together with cable binders.
Attention
Keep all signal wiring (particularly the interrupt signal lines) as short as possible. If long signal cables
cannot be avoided, use twisted pair wiring.
Related SICOMP literature
See the SICOMP IMC system manual for more information on installing and handling SICOMP
boards.

SMP16-CPU06x
©Siemens AG 2001, All Rights Reserved
4(4)J31069-D2085-U001-A2-7618

SMP16-CPU06x
©Siemens AG 2001, All Rights Reserved
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Table of Contents
1Introduction 9
2Technical Data 11
3Initial Commissioning 15
3.1 Settings on the Hardware 16
3.2 Layout and Special Wiring of the Bus Backplane 17
3.2.1 SMP16-CPU065 17
3.2.2 SMP16-CPU066 18
3.3 Switching from SMP16-CPU055 to SMP16-CPU065 19
3.4 Scope of Delivery 21
4Features 23
4.1 Microprocessor 26
4.2 Memory 26
4.2.1 BIOS 26
4.2.2 Working Storage 26
4.2.3 Serial EEPROM 26
4.2.4 SRAM Memory 26
4.3 Chip Set 27
4.3.1 Power Management 27
4.3.2 System Management Bus 27
4.3.3 Counters and Timers 27
4.3.4 DMA Controller 28
4.3.5 Interrupt Controller 28
4.3.6 NMI Generation 31
4.3.7 Bus Timing 32
4.3.8 Addressing the Loudspeaker 32
4.4 Drive Controller 33
4.5 LAN Controller 34
4.6 VGA Graphics Expansion 34
4.7 Realtime Functions 41
4.7.1 Additional Counter/Timer Block 41
4.7.2 Additional Interrupt Controller 43
4.7.3 Digital Inputs/Outputs 44
4.8 Safety Functions 45
4.8.1 Voltage Monitoring 45
4.8.2 Battery Buffering 45
4.8.3 Watchdog 45
4.8.4 Temperature Monitoring 46
4.8.5 Password Protection 46
4.8.6 LEDs 46
4.9 Operation without Fan 48
4.9.1 Setting via Setup 48
4.9.2 Regulated Operation 48

SMP16-CPU06x
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4.10 Operational Values 49
4.10.1 Operational Values of theSMP16-CPU06x 49
4.11 System Configuration 50
4.11.1 System Layout of the SMP16-CPU065 50
4.11.2 System Layout of the SMP16-CPU066 52
4.11.3 Operation of SMP16 Boards 53
4.12 Overview of the Interfaces 55
4.13 Ambient Conditions 56
4.14 Recommended Accessories/Replacement Parts 57
4.15 Recommended Reading 58
5Interfaces 60
5.1 Bus Interfaces 60
5.1.1 Signals of the IPCI Socket Strip 60
5.1.2 Signals of the CPCI Socket Strip 61
5.1.3 Signals on the SMP16 Bus 63
5.1.4 Special Signals of the SMP16 Bus 64
5.2 Drive Interfaces 66
5.2.1 Signals of the UNI-I/O Interface (SMP16-CPU065) 66
5.2.2 Signals of the Rear Panel I/O Interface (SMP16-CPU066) 67
5.2.3 Signals of the Hard Disk Interface (40-Pin) 68
5.2.4 Signals of the Hard Disk Interface (44-Pin) 69
5.2.5 Signals of the Floppy Disk Interface (34-Pin) 70
5.3 Front Plate Interfaces 71
5.3.1 USB Bus Interfaces 71
5.3.2 Signals of the Keyboard Interface 71
5.3.3 Signals of the Serial Interfaces - COM A / COM B 72
5.3.4 Signals of the LAN Interface (RJ45) 72
5.3.5 Parallel Interface - LPT1 73
5.3.6 CRT/LVDS Connection 74
5.3.7 PanelLink Connection 75
6Commissioning 76
6.1 Wiring of the Power Supply 76
6.2 Settings on the Hardware 77
6.3 Deleting the CMOS Configuration 81
6.4 Wiring of the Interrupts 82
6.5 Changing the Fuses 82
7Notes on Programming 84
7.1 Memory Address Areas 84
7.2 Input/Output Address Areas 86
7.2.1 Input/Output for Internal Board Registers 88
7.2.2 Manual Throttling Register 103
7.2.3 General Purpose Ports (GPP) 104
7.2.4 SMB Register Set 105
7.2.5 Memory Input/Output on the SMP16 Bus 108
7.2.6 Direct Input/Output for SMP16 AT Boards 109

SMP16-CPU06x
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7.2.7 Direct Input/Output for SMP16 I/O Boards 110
8Driver Software 112
8.1 LAN Drivers 112
8.2 Graphics Drivers 112
8.3 IOS 113
8.4 LAN Boot BIOS 113
8.5 Board Support Package 113
9BIOS 114
9.1 BIOS Setup 114
9.1.1 Starting Setup 114
9.1.2 Exiting Setup 117
9.1.3 Setup Page - "Standard CMOS Setup" 118
9.1.4 Setup Page - "BIOS Features Setup" 121
9.1.5 Setup Page - "Chipset Features Setup" 124
9.1.6 Setup Page - "Power Management Setup" 126
9.1.7 Setup Page - "PNP/PCI Configuration" 128
9.1.8 Setup Page - "Load BIOS Defaults" and "Load Setup Defaults" 130
9.1.9 Setup Page - "Integrated Peripherals" 131
9.1.10 Setup Page - "IMC Miscellaneous" 133
9.1.11 Setup Page - "Password Setting" 135
9.1.12 Setup Page - "IDE HDD Auto Detection" 135
9.1.13 Setup Page - "Save & Exit Setup" 136
9.1.14 Setup Page - "Exit Without Saving" 137
9.1.15 Setup - Default Setting 138
9.2 LAN Boot BIOS 141
9.3 BIOS Flash Memory 142
9.4 ROM-BIOS Interrupts 143
9.5 BIOS Data Area 145
10 BIOS Update 148
10.1 System BIOS 148
10.2 The AWDFLASH.EXE Service Program 148
10.3 How To Update Your BIOS 149
10.3.1 System with Graphics Card 149
10.3.2 System with Console Rerouting without Graphics Card 149
11 BSP-CPU06x: RMOS on the SMP16-CPU06x 150
11.1 RMOS and Power Management/Fanless Operation 150
11.2 Installation Program 151
11.3 RMOS Configuration for the SMP16-CPU06x 152
11.3.1 Support of the Secondary EIDE Controller 152
11.3.2 TCP/IP Connection 157
11.3.3 Extra Interrupt Controller 158
11.3.4 SRAM Driver 159
11.3.5 System Generation 162

SMP16-CPU06x
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8(4)J31069-D2085-U001-A2-7618
11.4 Additional Functions 165
11.4.1 Temperature Monitoring 165
11.4.2 Use of the BIOS Flash Memory 166
11.4.3 Use of the Serial EEPROM 176
11.4.4 Use of the Buffered SRAM 178
11.4.5 Description of test program TEST6x.386 192
12 Appendix 193
12.1 Notes on the Different Operating Systems 193
12.1.1 Windows NT 193
12.1.2 Win9x 193
12.1.3 RMOS 193
12.2 Layout of the CMOS RAM and the CDT 194
12.3 Use of the CDT during BIOS Startup 195
12.4 POST Codes 196
12.5 View of the Front Plate of the SMP16-CPU06x 198
12.6 Abbreviations and Terms 200

SMP16-CPU06x Introduction
©Siemens AG 2001, All Rights Reserved
(4)J31069-D2085-U001-A2-7618 9
1Introduction
The functions of the two SICOMP IMC SMP16 CPU boards are the same. The only difference is the
PCI bus connection with the applicable I/O expansions.
A description of the functionality of the SMP16-CPU066 has been added to the existing technical
description (release A1, July 2000).
Another difference is the decoupling of the secondary EIDE channel and floppy via the I/CPCI
backplane. With the CPCI backplane, the signals for the secondary EIDE channel and the floppy disk
drives are assigned to the area for the rear panel I/O.
An adapter is required to decouple these signals (see chapter 4.14).
Use of the SMP16-CPU065 varies depending on the specific models of the individual boards, while
such differentiation does not apply with the SMP16-CPU066!
The SMP16-CPU066 does not have a PCI-PCI bridge which means that the CPCI backplane bus is
PCI bus 0 of the SMP16-CPU066.

Introduction SMP16-CPU06x
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10 (4)J31069-D2085-U001-A2-7618

SMP16-CPU06x Technical Data
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2Technical Data
SMP16-CPU06x without AGP option
Processor Pentium II starting at 266 MHz
(333 MHz SMP16-CPU066)
Pentium III starting at 500MHz
Numeric processor Integrated in the processor
Cache 32 kbytes integrated in the processor
256/512-Kbyte, synchronous, second-level cache -
external or integrated dep. on processor
Main memory 64 to 256-Mbyte SDRAM (dep. on availability)
1 slot for 64/128/256-Mbyte -modules
JEDEC 144 pin SO DIMM, 3,3V
ROM memory (flash EPROM) Total of 1 Mbyte
256 kbytes for system and LAN-BIOS
768 kbytes for user data
SRAM memory 128 kbytes buffered, briefly via gold CAP,
otherwise via battery on system rack
Network AMD 79C793 10/100 MBaud network controller
Automatic 10BaseT/100BaseT2 switchover
Realtime expansions
•Interrupt system Interrupt controller 82C59A,
Five inputs accessible by SMP16 bus
Five inputs accessible by SMP16 bus
•Counter/timer Timer 82C54,
Outputs connected to interrupts
Gate and clock pulse inputs configurable
Connections
•PS/2 mouse/keyboard connection Mini DIN socket, 6-pin
•Parallel interface Socket, 25-pin, bidirectional, EPP/ECP capability
•Two serial interfaces Plug connector, 9-pin, 16550-compatible
•USB (Universal Serial Bus)
•LAN (Local Area Network) RJ45 socket
•SMP16 Bus 96-pin pin strip, in acc. w. DIN 41694,
allocated in acc. w. SMP16 bus spec. V1.0
•Hard disk interfaces 40-pin pin strip (channel 0) and
(EIDE, UDMA33) Expansion of the I/CPCI bus (channel 1)
•Floppy disk interfaces 34-pin pin strip (drive A) and
Expansion of the I/CPCI bus (drive B)

Technical Data SMP16-CPU06x
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•16 digital inputs/outputs 2 10-pin socket strips, AMP Micro Match,
parameterizable, TTL level
•SMP16-CPU065
- IPCI bus 180-pin socket strip
Allocated in acc. w. IPCI bus spec. V1.51, July 1998
UNI-IO allocation for hard disk interface (secondary
channel) and
floppy disk interface (drive B)
•SMP16-CPU066:
- CPCI bus 220-pin socket strip
Allocated in acc. w. CPCI spec. PICMG 2.0 R3.0
RPIO allocation for hard disk interface (secondary
channel) and
floppy disk interface (drive B)
AGP option
Monitor screen controller Silicon Motion LYNX E/EM
Video memory (SG-RAM) 4 Mbytes
Monitor screen resolution supported 1024 x 768/16.7 million colors at 75 Hz
Connections
•Analog monitor screen/ Socket, 15-pin, high density
LVDS display Can be switched for display
Resolution: 640x480 / 800x600 / 1024x768
•PanelLink display Socket, 26-pin HDP
Resolution: 640x480 / 800x600 / 1024x768
•USB

SMP16-CPU06x Technical Data
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(4)J31069-D2085-U001-A2-7618 13
Power consumption Starting at 20 W
Permissible ambient temperature
•Operation 0 °C to 55 °C
With fan, 3 x 100 m3/h
With "no fan" setting in BIOS Setup
•Transportation -40° C to 70° C
Physical stress
•Vibration Operation 2 g, 20 cycles per axis, 1 octave per min
In acc. w.: DIN EN 60068-2-6 Test Fc
•Shock Operation 30 g, half-sine 11 msec, pos. and neg.,direction:
3 shocks per axis
In acc. w.: DIN EN 60068-2-27 Test Ea
Storage 25 g, half-sine, 6 msec, pos. and neg., direction:
1000 shocks per axis
In acc. w.: DIN EN 60068-2-29 Test Eb
Electromagnetic compatibility Generic standard (EMC for industry)
In acc. w.: EN50081-2:1993
EN50082-2:1995
Dimensions (width, depth, height) 40/60 mm, 180 mm, 130 mm
Weight Approx. 1.5 kg with AGP option
Approx. 1.3 kg without AGP option
Reliability (MTBF) With AGP, with SMP16 26.2 years
With AGP, without SMP16 29.4 years
Without AGP, with SMP16 30.3 years
Without AGP, without SMP16 34.7 years

Technical Data SMP16-CPU06x
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14 (4)J31069-D2085-U001-A2-7618

SMP16-CPU06x Initial Commissioning
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(4)J31069-D2085-U001-A2-7618 15
3Initial Commissioning
The flowcharts on the next few pages illustrate the procedure recommended for initial commissioning
of the board.
Layout and special wiring
of the bus backplane
BIOS settings
(see chapter 6.2)
Settings on the hardware
End
Initial commissioning

Initial Commissioning SMP16-CPU06x
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3.1 Settings on the Hardware
Settings on the hardware
Delete BIOS settings on CMOS RAM:
Close switch S1-2 (ON), wait 30 seconds, and
then return it to OFF position.
Since the Setup settings are also stored on the
CDT in flash and these are still valid, pin 2 and
pin 12 must be connected on the LPT plug
connector the next time the system is started
(so that both the CMOS content and CDT are
invalid).
End

SMP16-CPU06x Initial Commissioning
©Siemens AG 2001, All Rights Reserved
(4)J31069-D2085-U001-A2-7618 17
3.2 Layout and Special Wiring of the Bus Backplane
3.2.1 SMP16-CPU065
Wire required interrupts for (SMP16) I/O
boards.
Wire required DMA channels for (SMP16)
I/O boards.
Wire special signals for (SMP16) I/O boards
(e.g., AEN).
Connect backup battery to bus backplane
(SMP16 or IPCI).
End
Layout and special wiring of the bus backplane
SMP16-CPU065:
Wire power supply on SMP16 bus backplane.
Install SMP16-CPU065 CPU board and mass
storage insert for IPCI system in the system
rack.
Install and wire IPCI bus backplane.
Set V I/O to 3.3 V.
Connect SMP16-CPU065 CPU board to mass
storage insert for SMP16 system, and install
both together in the system rack.
Yes
Use PS adapter (5 V only).
No
Operation with
IPCIbackplane?
PS 330 1) in
system?
No
Insert F2/F4 fuses.
Yes
1) PS 330 is required if PCI boards need 3.3 V.

Initial Commissioning SMP16-CPU06x
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3.2.2 SMP16-CPU066
Wire required interrupts for (SMP16) I/O
boards.
Wire required DMA channels for (SMP16)
I/O boards.
Wire special signals for (SMP16) I/O boards
(e.g., AEN).
Connect backup battery to bus backplane
(SMP16 or IPCI).
End
Layout and special wiring of the bus backplane
SMP16-CPU066:
Wire power supply on SMP16 bus backplane.
Install and wire IPCI bus backplane.
Set V I/O to 3.3 V.
Connect SMP16-CPU065 CPU board to mass
storage insert for SMP16 system, and install
both together in the system rack.
Yes
Use PS adapter (5 V only).
No
Operation with
IPCIbackplane?
PS 330 1) in
system?
No
Insert F2/F4 fuses.
Yes
1) PS 330 is required if PCI boards need 3.3 V.

SMP16-CPU06x Initial Commissioning
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(4)J31069-D2085-U001-A2-7618 19
3.3 Switching from SMP16-CPU055 to SMP16-CPU065
Keep the following points in mind when switching from an SMP16-CPU055 to an SMP16-CPU065 in
an existing SMP16 system.
•The SMP16-CPU065can be installed directly in the slot of the SMP16-CPU055.
•The IPCI bus plug connector must at least be powered with the PS adapter (only 5 V required).
•When an IPCI backplane and IPCI cards are used, the backplane must be wired. Remember that
the 3.3volts from the SMP16-CPU065 are not available to the IPCI bus.
•The VIO (reference voltage for the signal level on the IPCI bus) must be set to 3.3 V. All IPCI I/O
boards must use the VIO of the backplane bus.
•When an IPCI backplane with HD/FD-UNI-I/O wiring is used, one slot should be left free on the
left side to leave room for the new design (new drive insert).
The table below shows the differences between the SMP16-CPU065 and the
SMP16 CPU055
Function SMP16-CPU055 SMP16-CPU065
3.3 volt power supply Required from external source. Feed
in over PS adapter or IPCI
backplane.
On board
SMP16 register can be
read back. No All registers can be read back in the area 0178h to 017Fh.
Starting with KS02:
Area 0138h to 013Ch
SMP16 bus interface
can be switched off. No Set R178 bit 7 = 1. (Also switch off SYSCLK/OSC)
Switch off clock pulses
on the SMP16 bus
(8.33 MHz and
14.318 MHz)
No Set R178 bit 6 = 1.
(Bit 7 = 0 required)
Starting with KS02:
R13B bit 6, 7 - single enable
possible
Watchdog can be read
back. No R17E bit 7 = 1 after restart (no power on) indicates that a watchdog reset took place.
Writing R17E bit 7 = 1 deletes the bit.
Watchdog time can be
set. Two times (approx. 100 msec, 1 sec) Adjustable between 96 msec and 960 msec
R17E Bit 3,4,5
Additional counter block No Access via R134-R137
R17C Bit 3, 4 Input clock pulse counter,
ZZ0 and ZZ1 can be set.
Bit 4 Cascading of
counters ZZ0 and ZZ1
possible
R17C Bit 2 Counter enable
Starting with KS02:
R13B Bits 0,1,2 Clock pulses can be
enabledseparately.
Bits 3, 4, 5 Gates can be addressed
separately.
R13C Bits 0,1,2 Clock pulses can be
addressed with DI.
Bits 4,5,6 Gates can be addressed
with DI.

Initial Commissioning SMP16-CPU06x
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20 (4)J31069-D2085-U001-A2-7618
Function SMP16-CPU055 SMP16-CPU065
Interrupt matrix for
additional interrupt block No Electronicinterrupt matrix
R178 Bit 0,1,2 Interrupt enable and
selection
Additional interrupt block No Controller for various events (outputs of
additional counters, DREQ signals of the
SMP16 bus)
R130/131 Registers of the extra
8259 (ICW, OCW)
R133 read INTA add. 8259
Cascaded interrupts on
the SMP16 bus No Starting with KS02: Additional interrupt controller on SMP16 bus
can be cascaded.
R178 Bit 3 Enable CAS_EN
Buffered SRAM No Maximum of 128 kbytes
R17A Base address
R17D Bit 5, 6, 7 Enable and length
of the window.
Digital inputs/outputs,
TTL level No Starting with KS02: wo 8-bit ports can be parameterized as input
or output.
R138/9 Data ports
R13A Control register
Port 0 can also be set as clock pulse and gate
inputs of the additional counter.
R13C Parameterization
Serial EEPROM Access via GPP2 of the FDC37C932
(0EAh/0EBh bits 0 to 2: DI, DO,
CLK)
Access via GPP2 of the PIIX4E
R4035 Bit 2: Clock pulse for ser.
EEPROM (GPO10)
R4035 Bit 1 Data for ser. EEPROM
(GPO9)
R4032 Bit 1 Datafrom ser.EEPROM
(GPI17)
USER LED Two LEDs can be addressed via
GPIO of the FDC37C932, can be
used (via jumper) for the hard disk
channels to indicate access.
Four LEDs can be used for on-board
indications (via BIOS Setup or SW).
R17C Bit 0-3 Default USER
USER LED can be address via GPO of
PIIX4E.
R4034 Bit 0 LED 0 (GPO0)
R4035 Bit 1 LED 1 (GPO8)
R4037 Bit 3 LED 2 (GPO27)
R4037 Bit 4 LED 3 (GPO28)
SMP_INT Fixed on IRQ15 For PC compatibility's sake, IRQ15 is
permanently assigned to the secondary EIDE
channel.
SMP_INT can only be fed in with one of the
SMP_IRQs.
Starting with KS02:
Depending on the EIDE channel
SMP_INT is assigned to
IRQ14 or IRQ15 (or neither of the two).