Silicon Laboratories AN725 User manual

Rev. 0.1 9/12 Copyright © 2012 by Silicon Laboratories AN725
AN725
ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX
DEVICES
1. Introduction
The system power budget of a low power system has two components: active and low power mode. Active mode
periods include an active core executing code or a larger number of active peripherals. In low power mode periods,
the core enters a sleep state and fewer peripherals are active.
Figure 1. Defining the Power Budget—Active and Low Power Modes
SiM3L1xx devices have several features to address reducing power consumption in all operational modes to
achieve a longer product lifetime in battery-operated systems. This document addresses each of these features
and provides guidelines for achieving low power consumption in a variety of configurations and applications.
2. Key Points
This key topics of this document are as follows:
How to reduce active mode time and power consumption
How to reduce low power mode power consumption
Measuring the low power modes on an SiM3L1xx MCU card
General power-saving tips
3. Relevant Documentation
Precision32™ Application Notes are listed on the following website: www.silabs.com/32bit-appnotes.
AN666: Usage Guide for e SiM3U1xx,SiM3C1xx, and SiM3L1xx DMA and DTM Modules
AN720: Precision32™ Optimization Considerations for Code Size and Speed
AN667: Getting Started with the Silicon Labs Precision32 IDE
AN670: Getting Started with the Silicon Labs Precision32 AppBuilder
Active Mode
Low Power
Mode

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4. Reducing Active Mode Power Consumption
In active mode, the core is fetching instructions from memory and executing those instructions, and a large number
of peripherals may be active at once. This section discusses ways to reduce the SiM3L1xx device power
consumption in active mode (Normal, PM1, PM4, or PM5).
4.1. Dynamic AHB/APB Clock Scaling
One of the easiest ways to reduce overall system power consumption is to reduce the active mode time, which
maximizes the amount of time spent in the low power mode.
If the longest path to the next low power mode is the execution of code (e.g., a math algorithm), then it is typically
beneficial to run the AHB clock at the fastest speed possible to reduce the time spent in active mode.
If the longest path to the next low power mode is the transfer or collection of data through a peripheral, it is best to
run the clock at the lowest speed required for the peripheral. For example, if using the UART at 115200 baud and
the core is waiting for data to finish transferring, then running the AHB and APB at the slowest clock to achieve
115200 baud may be the lowest power configuration. However, if data is being transferred memory to memory by
the DMA, running the clocks at the fastest speed possible yields the lowest power consumption.
Due to the clock system of the SiM3L1xx devices, the AHB and APB clocks can be dynamically changed quickly
and easily using the CLKCTRL module based on the needs of the application.
4.2. Using the DMA and DTM Modules
The Direct Memory Access (DMA) and Data Transfer Manager (DTM) modules help move data without core
intervention. This reduces overall power consumption by removing the power consumed during flash accesses.
Additionally, since the Cortex-M3 is a load-store architecture where data is loaded into and out of registers only,
multiple instructions are required to move data from one area of memory to another, so the DMA and DTM may be
faster than data moves by the core, depending on the AHB load.
Instead of performing the data moves, the core can either sleep using wait-for-interrupt (WFI) or wait-for-event
(WFE) instructions, or the core can perform other tasks in parallel, reducing the active mode time.
For more information on how to use the DMA and DTM modules, see “AN666:Usage Guide for e
SiM3U1xx,SiM3C1xx, and SiM3L1xx DMA and DTM Modules” on the Silicon Labs 32-bit application notes website:
www.silabs.com/32bit-appnotes.
4.3. Code Optimization
There are several different coding techniques, compiler, and library options available for the Precision32 devices.
These options will change both code size and execution speed, which may result in power consumption savings in
systems which aim to execute code in active mode as quickly as possible before entering a low power state. In
addition to getting to the low power mode more quickly, changing the project settings may lead to smaller code
footprints, compacting the code into a smaller area with fewer memory accesses. The power consumption benefits
of code optimization for speed or size will vary depending on the project requirements and code.
For more information on how to write efficient code and the various optimization settings, see”AN720:
Precision32™ Optimization Considerations for Code Size and Speed” on the Silicon Labs 32-bit application notes
website: www.silabs.com/32bit-appnotes.

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4.4. Code Dependency
In addition to dynamic clock management, the power consumption of the SiM3L1xx device will vary with the type of
code the core executes. For example, if the core executes a complex math routine with branches, the pipeline will
miss every time a branch is taken and new instructions must be fetched. This stall and fetch period causes more
flash accesses, which increases power consumption. In addition, the core executes a wide variety of instructions
and activates the memory bus to fetch data from RAM or flash for use in these routines. In contrast, a string of NOP
instructions will take less power because the core isn’t executing complex instructions.
The data shown in Figure 2 does not use adaptive voltage scaling or any other techniques to change power
consumption. All of these measurements were taken using the PLL as the clock source with a higher SPMD setting
(i.e., reduced flash access frequency) at AHB frequencies above 40 MHz. The APB clock is equal to the AHB
clock, when the APB is enabled.
As shown by the data, the flash access frequency (SPMD) has a direct effect on the code that includes branches,
since the core stalls when waiting for the new instructions, resulting in reduced power consumption. This means
that it may be more efficient to run at a faster frequency with the same current consumption to reduce overall time
spent in active mode. For the code that is a long string of NOPs, the core never has a pipeline miss and never
stalls, so there is no change in power consumption with a different flash speed mode.
For power sensitive applications, experimenting with various code styles and instruction mixes may result in
reduced power consumption in active mode.
Figure 2. Power Consumption Code Dependency
AHB and APB Clock (MHz)
Current
20 25 30 40 504535
NOP code, no APB clocks enabled, all LDOs at 1.8 V
NOP code, all APB clocks enabled, all LDOs at 1.8 V
complex code, no APB clocks enabled, all LDOs at 1.8 V
complex code, all APB clocks enabled, all LDOs at 1.8 V
SPMD = 1 SPMD = 2

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4.5. Adaptive Voltage Scaling
SiM3L1xx devices have scalable LDOs powering the digital and memory modules on the device. These LDO
outputs are factory calibrated to 1.8 V to handle all process and temperature variations, but this voltage is often
much higher than the minimum voltage required by the digital and memory circuits. During normal operation, these
LDO outputs can be set to a value less than 1.8 V to reduce the amount of excess power consumed by these
circuits with some buffer to ensure correct operation.
When the digital or memory LDOs are sourced from the dc-dc converter, adaptive voltage scaling can also allow
the LDOs to track the dc-dc output voltage to utilize the higher efficiency of the dc-dc converter and reduce the
losses in the regulators.
Figure 3. Reducing Power Consumption with Adaptive Voltage Scaling
AHB Clock (MHz)
Power (mW)
0
10
20
30
40
50
70
60
0 1020304050
Digital LDO output fixed at 1.8 V
Digital LDO output scaled once at production test
Digital LDO output scaled adaptively by firmware

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4.6. DC-DC Load and Power Efficiency
The DCDC0 module on SiM3L1xx devices is a dc-dc buck converter with an input range of 1.8 to 3.8 V and an
output range of 1.25 to 3.8 V. The efficiency of this regulator changes based on load and the converter
configuration, as shown in Figure 4. The converter configuration can be changed dynamically or bypassed
according to the anticipated demands of the application to maintain the highest power efficiency and reduce power
consumption.
Figure 4. Reducing Power Consumption with the DC-DC Buck Converter
There are three ranges of operation for the dc-dc converter corresponding to three different load sizes:
1. Loads less than 5 mA
2. Loads between 5 and 15 mA
3. Loads greater than 15 mA
When operating with loads less than 5 mA, the dc-dc converter is most efficient when configured for light loads:
1. Power switch size set to 0 (PSMD = 0)
2. Asynchronous mode enabled (ASYNCEN = 1)
3. Minimum pulse width set to 40 ns (MINPWSEL = 3)
For loads between 5 and 15 mA, the converter should be set in a middle configuration:
1. Power switch size set to 0 (PSMD = 0)
2. Synchronous mode enabled (ASYNCEN = 0)
3. Minimum pulse width disabled (MINPWSEL = 0)
Current (mA)
Power Efficiency (%)
50%
55%
60%
65%
70%
75%
85%
80%
0 1020304050
90%
10090807060
Configured for Low Loads
Configured for High Loads

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To configure the converter for loads greater than 15 mA:
1. Power switch size set to 3 (PSMD = 3)
2. Synchronous mode enabled (ASYNCEN = 0)
3. Minimum pulse width disabled (MINPWSEL = 0)
Table 1 shows a summary of these settings for each load configuration.
After configuring the dc-dc converter for the load size, switch the appropriate LDOs to the converter output to
reduce system power. Each of the three LDOs (memory, digital, and analog) can be switched to the battery voltage
(VBAT) or the dc-dc converter output independently.
The firmware can adjust the dc-dc converter configuration based on the anticipated load for the active time. For
example, if only a few peripherals will be active and the core will halt for a period of time, then the load may be less
than 5 mA. Firmware can adjust the dc-dc converter appropriately during this period. If the core is fetching
instructions from flash at full speed and executing a math routine, then switching to the high load configuration will
yield lower power consumption.
For extremely light loads (less than 2-3 mA), the dc-dc converter will be less efficient than the LDOs at ~50%
efficiency, depending on the VBAT voltage and LDO bias settings. When this occurs, the dc-dc converter should be
bypassed (BEN = 1), which connects VBATDC to VDC, or disabled (DCDCEN = 0).
Table 1. DC-DC Load Configurations
Load Power Switch Size
(PSMD)
Synchronous or
Asynchronous
(ASYNCEN)
Minimum Pulse
Width (MINPWSEL)
less than 5 mA 0 Asynchronous (1) 40 ns (3)
5 mA to 15 mA 0 Synchronous (0) disabled (0)
greater than 15 mA 3 Synchronous (0) disabled (0)

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5. Reducing Power Consumption in Low Power Modes
In low power mode, the device core halts and the number of active peripherals typically reduces to the minimum
required by the application (i.e., real time clock). This section discusses techniques to reduce the SiM3L1xx device
power consumption in low power modes (PM2, PM3, PM6, and PM8).
5.1. SiM3L1xx Low Power Mode Overview
The SiM3L1xx devices feature seven low power modes in addition to normal operating mode. Several peripherals
provide wake up sources for these low power modes, including the Low Power Timer (LPTIMER0), RTC0 (alarms
and oscillator failure notification), Comparator 0 (CMP0), Advanced Capture Counter (ACCTR0), LCD VBAT
monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake.
In addition, all peripherals can have their clocks disabled to reduce power consumption with the clock control
(CLKCTRL) registers whenever a peripheral is not being used.
The SiM3L1xx devices have the power modes defined in Table 2.
5.1.1. Normal Mode (Power Mode 0)
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will
vary depending on AHB/APB clock speeds, the settings of CLKCTRL and the peripherals, and the dc-dc converter
and LDO settings.
5.1.2. Power Mode 1
Power Mode 1 occurs when the core executes code from RAM instead of flash. The power consumption of the
device is less than normal mode when in PM1.
5.1.3. Power Mode 2
In Power Mode 2, the core halts and the peripherals run at full speed. To place the device in this mode, the clock
settings in CLKCTRL should remain the same as Normal or Power Mode 1 and the core should execute a WFI or
WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device
from PM2 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB
(Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to
ensure all bus access is complete.
5.1.4. Power Mode 3 Fast Wake
Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0TCLK. The core
and the peripherals are halted in this mode. The available wake up sources to wake from PM3 are controlled by the
Power Management Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0
(alarms and oscillator failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT
monitor (LCD0), UART0, and PMU Pin Wake. Any reset event will also wake the device from PM3.
If the WFI instruction that wakes the device from PM3 Fast Wake is called from an interrupt service routine, the
interrupt that wakes the device from PM3FW must be of a sufficient priority to be recognized by the core.
By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low
Power Oscillator, the device can wake up faster than in standard Power Mode 3 at the expense of higher power
consumption.
5.1.5. Power Mode 3
Power Mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted. Waking from
PM3 requires one of the PMU wake sources described in “5.1.4. Power Mode 3 Fast Wake” to be properly
configured.
If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must
be of a sufficient priority to be recognized by the core.
5.1.6. Power Mode 4
Power Mode 4 is the same as normal operation except the AHB clock operates at a slower speed. The power
consumption of the device in this mode will vary depending on the AHB/APB clock speeds, the settings of
CLKCTRL and the peripherals, and the dc-dc converter and LDO settings.

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5.1.7. Power Mode 5
Power Mode 5 is the same as PM1 with a slower AHB clock source selected. The core executes code from RAM
instead of flash. The power consumption of the device in PM5 is slightly less than PM4.
5.1.8. Power Mode 6
In Power Mode 6, the core halts and the peripherals run at a slower speed than PM2. To place the device in this
mode, the clock settings in CLKCTRL should remain the same as PM4 or PM5, and the core should execute a WFI
or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the
device from PM6 must be of a sufficient priority to be recognized by the core.
5.1.9. Power Mode 8
In Power Mode 8, the core and most peripherals are halted, most clocks are stopped, and registers retain their
state. In addition, the LDO regulators are disabled, so all active circuitry operates directly from VBAT. Alternatively,
the PMU has a specialized VBAT-divided-by-2 low power mode charge pump that can power some internal
modules while in PM8 to save power. The fully operational functions in this mode are: LPTIMER0, RTC0, UART0
running from RTC0TCLK, port match, advanced capture counter, and the LCD controller.
This mode provides the lowest power consumption for the device, but requires an appropriate wake up source or
reset to exit. The available wake up or reset sources to wake from PM8 are controlled by the Power Management
Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator
failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT monitor (LCD0),
UART0, low power mode charge pump failure, and PMU Pin Wake. The available reset sources are: RESET pin,
VBAT supply monitor, Comparator 0, Comparator 1, low power mode charge pump failure, RTC0 oscillator failure,
or PMU wake event.
To enter this mode, firmware must write the SLEEPDEEP bit in the ARM System Control Register. Firmware must
then execute a WFI or WFE instruction. The core will remain in PM8 until an enabled wake up or reset source
occurs.

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Table 2. SiM3L1xx Power Modes
Mode Description Mode Entrance Mode Exit
Normal Core operating at full speed
Code executing from flash
Power Mode 1
(PM1)
Core operating at full speed
Code executing from RAM Execute code from RAM Jump to code in flash
Power Mode 2
(PM2)
Core halted
AHB and APB operate at full
speed for peripherals WFI or WFE instruction NVIC or WIC wakeup
Power Mode 3
Fast Wake
(PM3FW)
All clocks stopped except LFOSC0
or RTC0TCLK
AHB and APB set to Low Power
Oscillator
Core clock set to LFOSC0 or
RTC0TCLK
DMACTRL0 disabled
Fast wake mode
enabled in PM3CN
AHB switched to Low
Power Oscillator
WFI or WFE instruction
Requires a wake up
source or reset defined by
the PMU
Power Mode 3
(PM3) All clocks stopped
DMACTRL0 disabled
Clocks disabled in
PM3CN
WFI or WFE instruction
Requires a wake up
source or reset defined by
the PMU
Power Mode 4
(PM4)
Core operating at slower speed
Code executing from flash
Set the AHB clock to a
slower source Set the AHB clock to a
faster source
Power Mode 5
(PM5)
Core operating at slower speed
Code executing from RAM
Set the AHB clock to a
slower source
Execute code from RAM
Set the AHB clock to a
faster source or jump to
code in flash
Power Mode 6
(PM6)
Core halted
AHB and APB operate at a slower
speed for peripherals
Set the AHB clock to a
slower source
WFI or WFE instruction NVIC or WIC wakeup
Power Mode 8
(PM8)
Low power sleep
The LDO regulators are disabled
and all active circuitry operates
directly from VBAT
The following functions are
available:ACCTR0,RTC0,UART0
running from RTC0TCLK,
LPTIMER0, port match, and the
LCD controller
Register state retention
SLEEPDEEP set in the
ARM System Control
Register
WFI or WFE instruction Requires a wake up
source or reset defined by
the PMU

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5.2. Measuring Power
This section discusses the hardware setup and code required to reproduce the power specifications reported by
the SiM3L1xx data sheet.
5.2.1. Hardware Setup
To measure the power on the SiM3L1xx MCU Card with a fixed 3.3 V VBAT:
1. Connect a USB Debug Adapter to the 10-pin CoreSight connector (J14).
2. Remove the three shorting blocks from J7.
3. Remove the JP2 Imeasure shorting block and put a multimeter across (positive side on the bottom pin).
4. Move the VBAT Sel switch (SW2) to the middle +3.3 V_VREG position.
5. Move the VIO Sel (SW8) and VIORF Sel (SW9) switches to the bottom VBAT position.
6. Connect the 9 V power adapter to POWER (J6).
7. Download the code to the board.
8. Remove the debug adapter connection.
9. Measure the power of the device.
Figure 5. SiM3L1xx MCU Card Power Measurement Configuration—Fixed VBAT
USB Debug
Adapter 1
2
3
6
9 V Power
Adapter
4
5