Silicon Laboratories SiM3L1xx User manual

Rev 1.1 11/14 Copyright © 2013 by Silicon Laboratories SiM3L1xx
SiM3L1xx
High-Performance, Low-Power, 32-Bit Precision32™
MCU Family with up to 256 kB of Flash
32-bit ARM Cortex-M3 CPU
-50 MHz maximum frequency
-Single-cycle multiplication, hardware division support
-Nested vectored interrupt control (NVIC) with 8 priority levels
Memory
-32–256 kB flash, in-system programmable
-8–32 kB SRAM with configurable low power retention
Clock Sources
-Internal oscillator with PLL: 23–50 MHz
-Low power internal oscillator: 20 MHz
-Low frequency internal oscillator (LFO): 16.4 kHz
-External real-time clock (RTC) crystal oscillator
-External oscillator: Crystal, RC, C, CMOS clock
Power Management
-Three adjustable low drop-out (LDO) regulators
-Power-on reset circuit and brownout detectors
-DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
-Multiple power modes supported for low power optimization
Low Power Features
-75 nA typical current in Power Mode 8
-Low-current RTC (180 nA from LFO, 300 nA from crystal)
-4 μs wakeup, register state retention and no reset required from
lowest power mode
-175 μA/MHz at 3.6 V executing from flash
-140 μA/MHz at 3.6 V executing from SRAM
-Specialized on-chip charge pump reduces power consumption
-Process/Voltage/Temperature (PVT) Monitor
5 V Tolerant Flexible I/O
-Up to 62 contiguous 5 V tolerant GPIO with one priority cross-
bar providing flexibility in pin assignments
Temperature Range: –40 to +85 °C
Supply Voltage: 1.8 to 3.8 V
Analog Peripherals
-12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode
or 1
Msps 10-bit mode
-10-Bit Current-mode Digital-to-Analog Converter
-2 x Low-current comparators
Digital and Communication Peripherals
-1 x USART with IrDA and ISO7816 Smartcard support
-1 x UART that operates in low power mode
-2 x SPIs, 1 x I2C, 16/32-bit CRC
-128/192/256-bit Hardware AES Encryption
-Encoder/Decoder: Manchester and Three-out-of-Six
-Integrated LCD Controller: up to 160 segments (40x4), auto-
contrast and low power operation
Timers/Counters
-3 x 32-bit or 6 x 16-bit timers with capture/compare
-16-bit, 6-channel counter with capture/compare/PWM and
dead-time controller with differential outputs
-16-bit low power timer/advanced capture counter operational in
the lowest power mode
-32-bit real time clock (RTC) with multiple alarms
-Watchdog timer
-Low power mode advanced capture counter (ACCTR)
Data Transfer Peripherals
-10-Channel DMA Controller
-3 Channel Data Transfer Manager manages complex DMA
transfers without core intervention
On-Chip Debugging
-Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG
(no boundary scan) allow debug and programming
-Cortex-M3 embedded trace macrocell (ETM)
Package Options
-QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
-TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)

2 Rev 1.1

SiM3L1xx
Rev 1.1 3
Table of Contents
1. Related Documents and Conventions...............................................................................5
1.1. Related Documents........................................................................................................5
1.1.1. SiM3L1xx Reference Manual.................................................................................5
1.1.2. Hardware Access Layer (HAL) API Description ....................................................5
1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5
1.2. Conventions ...................................................................................................................5
2. Typical Connection Diagrams ............................................................................................6
2.1. Power .............................................................................................................................6
3. Electrical Specifications......................................................................................................8
3.1. Electrical Characteristics ................................................................................................8
3.2. Thermal Conditions ......................................................................................................30
3.3. Absolute Maximum Ratings..........................................................................................31
4. Precision32™ SiM3L1xx System Overview.....................................................................32
4.1. Power ...........................................................................................................................34
4.1.1. DC-DC Buck Converter (DCDC0)........................................................................34
4.1.2. Three Low Dropout LDO Regulators (LDO0) ......................................................35
4.1.3. Voltage Supply Monitor (VMON0) .......................................................................35
4.1.4. Power Management Unit (PMU)..........................................................................35
4.1.5. Device Power Modes...........................................................................................35
4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0).......................38
4.2. I/O.................................................................................................................................39
4.2.1. General Features.................................................................................................39
4.2.2. Crossbar ..............................................................................................................39
4.3. Clocking........................................................................................................................40
4.3.1. PLL (PLL0)...........................................................................................................41
4.3.2. Low Power Oscillator (LPOSC0) .........................................................................41
4.3.3. Low Frequency Oscillator (LFOSC0)...................................................................41
4.3.4. External Oscillators (EXTOSC0)..........................................................................41
4.4. Integrated LCD Controller (LCD0)................................................................................42
4.5. Data Peripherals...........................................................................................................43
4.5.1. 10-Channel DMA Controller.................................................................................43
4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2) .................................................43
4.5.3. 128/192/256-bit Hardware AES Encryption (AES0) ............................................43
4.5.4. 16/32-bit Enhanced CRC (ECRC0) .....................................................................44
4.5.5. Encoder / Decoder (ENCDEC0) ..........................................................................44
4.6. Counters/Timers...........................................................................................................45
4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2)...........................................................45
4.6.2. Enhanced Programmable Counter Array (EPCA0) .............................................45
4.6.3. Real-Time Clock (RTC0) .....................................................................................46
4.6.4. Low Power Timer (LPTIMER0)............................................................................46
4.6.5. Watchdog Timer (WDTIMER0)............................................................................46
4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0)...................................47
4.7. Communications Peripherals .......................................................................................48
4.7.1. USART (USART0) ...............................................................................................48

SiM3L1xx
4 Rev 1.1
4.7.2. UART (UART0)....................................................................................................48
4.7.3. SPI (SPI0, SPI1) ..................................................................................................49
4.7.4. I2C (I2C0) ............................................................................................................49
4.8. Analog ..........................................................................................................................50
4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)...................................................50
4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) .........................................................50
4.8.3. Low Current Comparators (CMP0, CMP1) ..........................................................50
4.9. Reset Sources..............................................................................................................51
4.10.Security ........................................................................................................................52
4.11.On-Chip Debugging .....................................................................................................52
5. Ordering Information.........................................................................................................53
6. Pin Definitions....................................................................................................................55
6.1. SiM3L1x7 Pin Definitions .............................................................................................55
6.2. SiM3L1x6 Pin Definitions .............................................................................................62
6.3. SiM3L1x4 Pin Definitions .............................................................................................69
6.4. TQFP-80 Package Specifications ................................................................................74
6.4.1. TQFP-80 Solder Mask Design.............................................................................77
6.4.2. TQFP-80 Stencil Design ......................................................................................77
6.4.3. TQFP-80 Card Assembly.....................................................................................77
6.5. QFN-64 Package Specifications ..................................................................................78
6.5.1. QFN-64 Solder Mask Design...............................................................................80
6.5.2. QFN-64 Stencil Design ........................................................................................80
6.5.3. QFN-64 Card Assembly.......................................................................................80
6.6. TQFP-64 Package Specifications ................................................................................81
6.6.1. TQFP-64 Solder Mask Design.............................................................................84
6.6.2. TQFP-64 Stencil Design ......................................................................................84
6.6.3. TQFP-64 Card Assembly.....................................................................................84
6.7. QFN-40 Package Specifications ..................................................................................85
6.7.1. QFN-40 Solder Mask Design...............................................................................87
6.7.2. QFN-40 Stencil Design ........................................................................................87
6.7.3. QFN-40 Card Assembly.......................................................................................87
7. Revision Specific Behavior...............................................................................................88
7.1. Revision Identification ..................................................................................................88
Document Change List...........................................................................................................90
Contact Information................................................................................................................91

SiM3L1xx
Rev 1.1 5
1. Related Documents and Conventions
1.1. Related Documents
This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices.
1.1.1. SiM3L1xx Reference Manual
The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral on the
SiM3L1xx devices.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Figure 1.1. Block Diagram Conventions

SiM3L1xx
6 Rev 1.1
2. Typical Connection Diagrams
This section provides typical connection diagrams for SiM3L1xx devices.
2.1. Power
Figure 2.1 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck
converter is not used.
Figure 2.1. Connection Diagram with DC-DC Converter Unused
Figure 2.2 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the internal dc-dc
buck converter is in use and I/O are powered directly from the battery.
Figure 2.2. Connection Diagram with DC-DC Converter Used and I/O Powered from Battery
Figure 2.3 shows a typical connection diagram for the power pins of the SiM3L1xx devices when used with an
external radio device like the Silicon Labs EZRadio®or EZRadioPRO®devices.

SiM3L1xx
Rev 1.1 7
Figure 2.3. Connection Diagram with External Radio Device
Figure 2.4 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck
converter is used and the I/O are powered separately.
Figure 2.4. Connection Diagram with DC-DC Converter Used and I/O Powered Separately

SiM3L1xx
8 Rev 1.1
3. Electrical Specifications
3.1. Electrical Characteristics
Table 3.1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating Supply Voltage on
VBAT/VBATDC
VBAT 1.8 — 3.8 V
Operating Supply Voltage on VDC VDC 1.25 — 3.8 V
Operating Supply Voltage on VDRV VDRV 1.25 — 3.8 V
Operating Supply Voltage on VIO VIO 1.8 — VBAT V
Operation Supply Voltage on VIORF VIORF 1.8 — VBAT V
Operation Supply Voltage on VLCD VLCD 1.8 — 3.8 V
System Clock Frequency (AHB) fAHB 0 — 50 MHz
Peripheral Clock Frequency (APB) fAPB 0 — 50 MHz
Operating Ambient Temperature TA–40 — +85 °C
Operating Junction Temperature TJ–40 — 105 °C
Note: All voltages with respect to VSS.
All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise.

SiM3L1xx
Rev 1.1 9
Table 3.2. Power Consumption
Parameter Symbol Test Condition Min Typ Max Unit
Digital Core Supply Current
Normal Mode1,2,3,4—Full speed
with code executing from flash,
peripheral clocks ON
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 17.5 18.9 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 6.7 7.2 mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 1.15 1.4 mA
Normal Mode1,2,3,4—Full speed
with code executing from flash,
peripheral clocks OFF
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 13.3 14.5 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 5.4 5.9 mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 980 1.2 μA
Normal Mode1,2,3,4—Full speed
with code executing from flash,
LDOs powered by dc-dc at 1.9 V,
peripheral clocks OFF
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
VBAT = 3.3 V
— 9.7 — mA
FAHB = 49 MHz,
FAPB = 24.5 MHz
VBAT = 3.8 V
— 8.65 — mA
FAHB = 20 MHz,
FAPB = 10 MHz
VBAT = 3.3 V
— 4.15 — mA
FAHB = 20 MHz,
FAPB = 10 MHz
VBAT = 3.8 V
— 3.9 — mA
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

SiM3L1xx
10 Rev 1.1
Power Mode 11,2,3,4—Full speed
with code executing from RAM,
peripheral clocks ON
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 13.4 16.6 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 4.7 — mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 810 — μA
Power Mode 11,2,3,4—Full speed
with code executing from RAM,
peripheral clocks OFF
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 9.4 12.5 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 3.3 — mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 630 — μA
Power Mode 11,2,3,4—Full speed
with code executing from RAM,
LDOs powered by dc-dc at 1.9 V,
peripheral clocks OFF
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
VBAT = 3.3 V
— 7.05 — mA
FAHB = 49 MHz,
FAPB = 24.5 MHz
VBAT = 3.8 V
— 6.3 — mA
FAHB = 20 MHz,
FAPB = 10 MHz
VBAT = 3.3 V
— 2.75 — mA
FAHB = 20 MHz,
FAPB = 10 MHz
VBAT = 3.8 V
— 2.6 — mA
Power Mode 21,2,3,4,5—Core halted
with peripheral clocks ON
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 7.6 11.3 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 2.75 — mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 575 — μA
Table 3.2. Power Consumption (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

SiM3L1xx
Rev 1.1 11
Power Mode 21,2,3,4,5—Core halted
with only Port I/O clocks on (wake
from pin).
IBAT FAHB = 49 MHz,
FAPB = 24.5 MHz
— 4 7.2 mA
FAHB = 20 MHz,
FAPB = 10 MHz
— 1.47 — mA
FAHB = 2.5 MHz,
FAPB = 1.25 MHz
— 430 — μA
Power Mode 31,2,6—Fast-Wake
Mode (PM3CLKEN = 1)
IBAT VBAT = 3.8 V — 320 530 μA
VBAT = 1.8 V — 225 — μA
Power Mode 41,2,4,6—Slower clock
speed with code executing from
flash, peripheral clocks ON
IBAT FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
— 385 640 μA
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
— 330 — μA
Power Mode 51,2,4,6—Slower clock
speed with code executing from
RAM, peripheral clocks ON
IBAT FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
— 320 490 μA
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
— 275 — μA
Power Mode 61,2,4,6—Core halted
with peripheral clocks ON
IBAT FAHB = FAPB = 16 kHz,
VBAT = 3.8 V
— 315 490 μA
FAHB = FAPB = 16 kHz,
VBAT = 1.8 V
— 270 — μA
Power Mode 81,2—Low Power
Sleep, powered through VBAT,
VIO, and VIORF at 2.4 V, 32kB of
retention RAM
IBAT RTC Disabled,
TA= 25 °C
— 75 400 nA
RTC w/ 16.4 kHz LFO,
TA= 25 °C
— 360 — nA
RTC w/ 32.768 kHz Crystal,
TA= 25 °C
— 670 — nA
Table 3.2. Power Consumption (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

SiM3L1xx
12 Rev 1.1
Power Mode 81,2—Low Power
Sleep, powered by the low power
mode charge pump, 32kB of reten-
tion RAM
IBAT RTC w/ 16.4 kHz LFO,
VBAT = 2.4 V, TA= 25 °C
— 180 — nA
RTC w/ 32.768 kHz Crystal,
VBAT = 2.4 V, TA= 25 °C
— 300 — nA
RTC w/ 16.4 kHz LFO,
VBAT = 3.8 V, TA= 25 °C
— 245 — nA
RTC w/ 32.768 kHz Crystal,
VBAT = 3.8 V, TA= 25 °C
— 390 — nA
Unloaded VIO and VIORF Current10 IVIO — 2 — nA
Power Mode 8 Peripheral Currents
UART0 IUART0 VBAT = 3.8 V, TA= 25 °C — 195 600 nA
VBAT = 2.4 V, TA= 25 °C — 120 — nA
LCD07, No segments active ILCD0 VBAT = 3.8 V, TA= 25 °C — 495 660 nA
VBAT = 2.4 V, TA= 25 °C — 395 — nA
LCD07, All (4 x 40) segments active ILCD0 VBAT = 3.8 V, TA= 25 °C — 800 — nA
VBAT = 2.4 V, TA= 25 °C — 580 — nA
Advanced Capture Counter
(ACCTR0), LC Single-Ended
Mode, Relative to Sampling Fre-
quency9
IACCTR VBAT = 2.4 V, TA= 25 °C,
CPMD = 01
— 1.11 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 01
— 1.44 — nA/Hz
VBAT = 2.4 V, TA= 25 °C,
CPMD = 10
— 1.45 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 10
— 1.82 — nA/Hz
VBAT = 2.4 V, TA= 25 °C,
CPMD = 11
— 2.15 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 11
— 2.54 — nA/Hz
Table 3.2. Power Consumption (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

SiM3L1xx
Rev 1.1 13
Advanced Capture Counter
(ACCTR0), LC Dual or Quadrature
Mode, Relative to Sampling Fre-
quency9
IACCTR VBAT = 2.4 V, TA= 25 °C,
CPMD = 01
— 1.39 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 01
— 1.89 — nA/Hz
VBAT = 2.4 V, TA= 25 °C,
CPMD = 10
— 2.08 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 10
— 2.59 — nA/Hz
VBAT = 2.4 V, TA= 25 °C,
CPMD = 11
— 3.47 — nA/Hz
VBAT = 3.8 V, TA= 25 °C,
CPMD = 11
— 4.03 — nA/Hz
Analog Peripheral Supply Currents
PLL0 Oscillator (PLL0OSC) IPLLOSC Operating at 49 MHz — 1.4 1.6 mA
Low-Power Oscillator (LPOSC0) ILPOSC Operating at 20 MHz — 25 — μA
Operating at 2.5 MHz — 25 — μA
Low-Frequency Oscillator
(LFOSC0)
ILFOSC Operating at 16.4 kHz — 190 310 nA
External Oscillator (EXTOSC0) IEXTOSC FREQCN = 111 — 3.8 4.5 mA
FREQCN = 110 — 840 960 μA
FREQCN = 101 — 185 230 μA
FREQCN = 100 — 65 80 μA
FREQCN = 011 — 25 30 μA
FREQCN = 010 — 10 13 μA
FREQCN = 001 — 5 7 μA
FREQCN = 000 — 3 5 μA
Table 3.2. Power Consumption (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

SiM3L1xx
14 Rev 1.1
SARADC0 ISARADC Sampling at 1 Msps, Internal
VREF used
— 1.2 1.6 mA
Sampling at 250 ksps, lowest
power mode settings.
— 390 540 μA
Temperature Sensor ITSENSE — 75 110 μA
Internal SAR Reference IREFFS Normal Power Mode — 680 — μA
Normal Power Mode — 160 — μA
VREF0 IREFP — 80 — μA
Comparator 0 (CMP0),
Comparator 1 (CMP1)
ICMP CMPMD = 11 — 0.5 2 μA
CMPMD = 10 — 3 8 μA
CMPMD = 01 — 10 16 μA
CMPMD = 00 — 25 42 μA
IDAC08IIDAC — 70 100 μA
Voltage Supply Monitor (VMON0) IVMON — 10 22 μA
Flash Current on VBAT
Write Operation IFLASH-W — — 8 mA
Erase Operation IFLASH-E — — 15 mA
Table 3.2. Power Consumption (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes all peripherals that cannot have clocks gated in the Clock Control module.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8
production test measurements.

Table 3.3. Power Mode Wake Up Times
Parameter Symbol Test Condition Min Typ Max Unit
Power Mode 2 or 6 Wake Time tPM2 4 — 5 clocks
Power Mode 3 Fast Wake Time
(using LFO as clock source)
tPM3FW — 425 — μs
Power Mode 8 Wake Time tPM8 — 3.8 — μs
Notes:
1. Wake times are specified as the time from the wake source to the execution phase of the first instruction following WFI.
This includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0).
Table 3.4. Reset and Supply Monitor
Parameter Symbol Test Condition Min Typ Max Unit
VBAT High Supply Monitor Threshold
(VBATHITHEN = 1)
VVBATMH Early Warning — 2.20 — V
Reset 1.95 2.05 2.1 V
VBAT Low Supply Monitor Threshold
(VBATHITHEN = 0)
VVBATML Early Warning — 1.85 — V
Reset 1.70 1.75 1.77 V
Power-On Reset (POR) Threshold VPOR Rising Voltage on
VBAT
— 1.4 — V
Falling Voltage on
VBAT
0.8 1 1.3 V
VBAT Ramp Time tRMP Time to VBAT > 1.8 V 10 — 3000 μs
Reset Delay from POR tPOR Relative to VBAT >
VPOR
3 — 100 ms
Reset Delay from non-POR source tRST Time between release
of reset source and
code execution
— 10 — μs
RESET Low Time to Generate Reset tRSTL 50 — — ns
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD FAHB > 1 MHz — 0.5 1.5 ms
Missing Clock Detector Trigger
Frequency
FMCD — 2.5 10 kHz
VBAT Supply Monitor Turn-On Time tMON — 2 — μs
SiM3L1xx
Rev 1.1 15

SiM3L1xx
16 Rev 1.1
Table 3.5. On-Chip Regulators
Parameter Symbol Test Condition Min Typ Max Unit
DC-DC Buck Converter
Input Voltage Range VDCIN 1.8 — 3.8 V
Input Supply to Output Voltage Differ-
ential (for regulation)
VDCREG 0.45 — — V
Output Voltage Range VDCOUT 1.25 — 3.8 V
Output Voltage Accuracy VDCACC — ±25 — mV
Output Current IDCOUT — — 90 mA
Inductor Value1LDC 0.47 0.56 0.68 μH
Inductor Current Rating ILDC Iload < 50 mA 450 — — mA
Iload > 50 mA 550 — — mA
Output Capacitor Value CDCOUT 1 2.2 10 μF
Input Capacitor Value2CDCIN — 4.7 — μF
Load Regulation Rload — 0.03 — mV/mA
Maximum DC Load Current During
Startup
IDCMAX — — 5 mA
Switching Clock Frequency FDCCLK 1.9 2.9 3.8 MHz
Local Oscillator Frequency FDCOSC 2.4 2.9 3.4 MHz
LDO Regulators
Input Voltage Range3VLDOIN Sourced from VBAT 1.8 — 3.8 V
Sourced from VDC 1.9 — 3.8 V
Output Voltage Range4VLDO 0.8 — 1.9 V
LDO Output Voltage Accuracy VLDOACC — ±25 — mV
Output Settings in PM8 (All LDOs) VLDO 1.8 V < VBAT < 2.9 V 1.5 V
1.95 V < VBAT < 3.5 V 1.8 V
2.0 V < VBAT < 3.8 V 1.9 V
Notes:
1. See reference manual for recommended inductors.
2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10
m(@ frequency > 1 MHz).
3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure
that the LDO output voltage will remain at a valid level as long as VLDOIN is at or above the specified minimum.
4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both
LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO.
When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO.
5. Output range represents the programmable output range, and does not reflect the minimum voltage under all
conditions. Dropout when the input supply is close to the output setting is normal, and accounted for.
6. Analog peripheral specifications assume a 1.8 V output on the analog LDO.

SiM3L1xx
Rev 1.1 17
Memory LDO Output Setting5VLDOMEM During Programming 1.8 — 1.9 V
During Normal
Operation
1.5 — 1.9 V
Digital LDO Output Setting VLDODIG FAHB < 20 MHz 1.0 — 1.9 V
FAHB > 20 MHz 1.2 — 1.9 V
Analog LDO Output Setting During
Normal Operation6
VLDOANA 1.8 V
Table 3.5. On-Chip Regulators (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. See reference manual for recommended inductors.
2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10
m(@ frequency > 1 MHz).
3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure
that the LDO output voltage will remain at a valid level as long as VLDOIN is at or above the specified minimum.
4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both
LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO.
When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO.
5. Output range represents the programmable output range, and does not reflect the minimum voltage under all
conditions. Dropout when the input supply is close to the output setting is normal, and accounted for.
6. Analog peripheral specifications assume a 1.8 V output on the analog LDO.

Table 3.6. Flash Memory
Parameter Symbol Test Condition Min Typ Max Unit
Write Time1tWRITE One 16-bit Half Word 20 21 22 μs
Erase Time1tERASE One Page 20 21 22 ms
tERALL Full Device 20 21 22 ms
Endurance (Write/Erase Cycles) NWE 20k 100k — Cycles
Retention2tRET TA= 25 °C, 1k Cycles 10 100 — Years
Notes:
1. Does not include sequencing time before and after the write/erase operation, which may take up to 35 μs. During
sequential write operations, this extra time is only taken prior to the first write and after the last write.
2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report.
SiM3L1xx
18 Rev 1.1

SiM3L1xx
Rev 1.1 19
Table 3.7. Internal Oscillators
Parameter Symbol Test Condition Min Typ Max Unit
Phase-Locked Loop (PLL0OSC)
Calibrated Output Frequency
(Free-running output mode,
RANGE = 2)
fPLL0OSC Full Temperature and
Supply Range
48.3 49 49.7 MHz
Power Supply Sensitivity
(Free-running output mode,
RANGE = 2)
PSSPLL0OSC TA = 25 °C,
Fout = 49 MHz
— 300 — ppm/V
Temperature Sensitivity
(Free-running output mode,
RANGE = 2)
TSPLL0OSC VBAT = 3.3 V,
Fout = 49 MHz
— 50 — ppm/°C
Adjustable Output Frequency
Range
fPLL0OSC 23 — 50 MHz
Lock Time tPLL0LOCK fREF = 20 MHz,
fPLL0OSC = 50 MHz
M=39, N=99,
LOCKTH = 0
— 2.75 — μs
fREF = 2.5 MHz,
fPLL0OSC = 50 MHz
M=19, N=399,
LOCKTH = 0
— 9.45 — μs
fREF = 32.768 kHz,
fPLL0OSC = 50 MHz
M=0, N=1524,
LOCKTH = 0
— 92 — μs
Low Power Oscillator (LPOSC0)
Oscillator Frequency fLPOSC Full Temperature and
Supply Range
19 20 21 MHz
Divided Oscillator Frequency fLPOSCD Full Temperature and
Supply Range
2.375 2.5 2.625 MHz
Power Supply Sensitivity PSSLPOSC TA = 25 °C — 0.5 — %/V
Temperature Sensitivity TSLPOSC VBAT = 3.3 V — 55 — ppm/°C
Low Frequency Oscillator (LFOSC0)
Oscillator Frequency fLFOSC Full Temperature and
Supply Range
13.4 16.4 19.7 kHz
TA = 25 °C,
VBAT = 3.3 V
15.8 16.4 17.3 kHz
Power Supply Sensitivity PSSLFOSC TA = 25 °C — 2.4 — %/V
Temperature Sensitivity TSLFOSC VBAT = 3.3 V — 0.2 — %/°C

SiM3L1xx
20 Rev 1.1
RTC0 Oscillator (RTC0OSC)
Missing Clock Detector Trigger
Frequency
fRTCMCD — 8 15 kHz
RTC External Input CMOS Clock
Frequency
fRTCEXTCLK 0 — 40 kHz
RTC Robust Duty Cycle Range DCRTC 25 — 55 %
Table 3.8. External Oscillator
Parameter Symbol Test Condition Min Typ Max Unit
External Input CMOS Clock
Frequency
fCMOS 0* — 50 MHz
External Crystal Frequency fXTAL 0.01 — 25 MHz
External Input CMOS Clock High Time tCMOSH 9 — — ns
External Input CMOS Clock Low Time tCMOSL 9 — — ns
Low Power Mode Charge Pump
Supply Range (input from VBAT)
VBAT 2.4 — 3.8 V
*Note: Minimum of 10 kHz when debugging.
Table 3.7. Internal Oscillators (Continued)
Parameter Symbol Test Condition Min Typ Max Unit