Silicon Laboratories Giant Gecko EFM32GG User manual

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EFM32GG Reference Manual
Giant Gecko Series
• 32-bit ARM Cortex-M3 processor running at up to 48 MHz
• Up to 1024 kB Flash and 128 kB RAM memory
• Energy efficient and autonomous peripherals
• Ultra low power Energy Modes with sub-µA operation
• Fast wake-up time of only 2 µs
The EFM32GG microcontroller series revolutionizes the 8- to 32-bit market with a
combination of unmatched performance and ultra low power consumption in both
active- and sleep modes. EFM32GG devices consume as little as 219 µA/MHz in run
mode.
EFM32GG's low energy consumption outperforms any other available 8-, 16-,
and 32-bit solution. The EFM32GG includes autonomous and energy efficient
peripherals, high overall chip- and analog integration, and the performance of the
industry standard 32-bit ARM Cortex-M3 processor.

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1 Energy Friendly Microcontrollers
1.1 Typical Applications
The EFM32GG microcontroller is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive
applications. These devices are developed to minimize the energy consumption by lowering both the
powerandtheactivetime,overallphasesofMCUoperation.Thisuniquecombinationofultralowenergy
consumption and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out
of the available energy in a variety of applications.
Ultra low energy EFM32GG microcontrollers are perfect for:
• Gas metering
• Energy metering
• Water metering
• Smart metering
• Alarm and security systems
• Health and fitness applications
• Industrial and home automation
01 2 3 4
1.2 EFM32GG Development
BecauseEFM32GGusetheCortex-M3CPU,embeddeddesignersbenefitfromthelargestdevelopment
ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design
process and includes powerful debug tools, and some of the world’s top brand compilers. Libraries with
documentation and user examples shorten time from idea to market.
The range of EFM32GG devices ensure easy migration and feature upgrade possibilities.

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2 About This Document
This document contains reference material for the EFM32GG series of microcontrollers. All modules
and peripherals in the EFM32GG series devices are described in general terms. Not all modules are
present in all devices, and the feature set for each device might vary. Such differences, including pin-
out, are covered in the device-specific datasheets.
2.1 Conventions
Register Names
Register names are given as a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the numeric instance for modules that might have more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register,
where xdenotes the port instance (A,B,...).
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with
(x:y), where xis the start bit and yis the end bit.
Address
The address for each register can be found by adding the base address of the module (found in the
Memory Map), and the offset address for the register (found in module Register Map).
Access Type
The register access types used in the register descriptions are explained in Table 2.1 (p. 3) .
Table 2.1. Register Access Types
Access Type Description
R Read only. Writes are ignored.
RW Readable and writable.
RW1 Readable and writable. Only writes to 1 have effect.
RW1H Readable, writable and updated by hardware. Only writes to
1 have effect.
W1 Read value undefined. Only writes to 1 have effect.
W Write only. Read value undefined.
RWH Readable, writable and updated by hardware.
Number format
0x prefix is used for hexadecimal numbers.
0b prefix is used for binary numbers.
Numbers without prefix are in decimal representation.

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Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0
unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices.
Reset Value
The reset value denotes the value after reset.
Registers denoted with X have an unknown reset value and need to be initialized before use. Note
that, before these registers are initialized, read-modify-write operations might result in undefined register
values.
Pin Connections
Pin connections are given as a module prefix followed by a short pin name:
USn_TX (USARTn TX pin)
The pin locations referenced in this document are given in the device-specific datasheet.
2.2 Related Documentation
Further documentation on the EFM32GG family and the ARM Cortex-M3 can be found at the Silicon
Laboratories and ARM web pages:
www.silabs.com
www.arm.com

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3 System Overview
3.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for
any battery operated application, as well as other systems requiring high performance and low-energy
consumption, see Figure 3.1 (p. 5) .
3.2 Block Diagram
Figure 3.1 (p. 5) shows the block diagram of EFM32GG. The color indicates peripheral availability
in the different energy modes, described in Section 3.4 (p. 7) .
Figure 3.1. Block Diagram of EFM32GG
Clock Management Energy Management
Serial Interfaces
I/ O Ports
Core and Memory
Timers and Triggers Analog Interfaces Security
32- bit bus
Peripheral Reflex System
ARM Cortex™- M3 processor
Flash
Program
Memory
LESENSE
High Freq.
RC
Oscillator
High Freq.
Crystal
Oscillator
Timer/
Counter
Low Energy
Timer
Pulse
Counter
Real Time
Counter
Low Freq.
Crystal
Oscillator
Low Freq.
RC
Oscillator
Watchdog
Timer
RAM
Memory
Ext. Bus
Interface
General
Purpose
I/ O
Memory
Protection
Unit
DMA
Controller
Debug
Interface
w/ ETM
External
Interrupts
Pin
Reset
Hardware
AES
Giant Gecko
LCD
Controller
ADC
DAC Operational
Amplifier
USB
USART
Low
Energy
UART
I
2
C
UART
Power- on
Reset
Voltage
Regulator
Back- up
Power
Domain
Voltage
Comparator
Brown- out
Detector
TFT
Driver
Back- up
RTC
Pin
Wakeup
Ultra Low Freq.
RC
Oscillator
Analog
Comparator
Aux High Freq.
RC
Oscillator
Figure 3.2. Energy Mode Indicator
01 2 3 4

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Note In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.
3.3 Features
3.3.1 MCU Features
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.8 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32768 Hz oscillator, Power-on Reset,
Brown-out Detector, RAM and CPU retention
• 80 µA/MHz @ 3 V Sleep Mode
• 219 µA/MHz @ 3 V Run Mode, with code executed from flash
•1024/512 KB Flash
• Read-while-write support
•128 KB RAM
•Up to 90 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•12 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
•12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
•External Bus Interface (EBI)
• Up to 4x256 MB of external memory mapped space
• TFT Controller supporting Direct Drive
•Universal Serial Bus (USB)
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
•Integrated LCD Controller for up to 8×36 Segments
• Voltage boost, adjustable contrast adjustment and autonomous animation feature
•Hardware AES with 128/256-bit Keys in 54/75 cycles
•Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA (USART0)/I2S (USART1+USART2)
• Triple buffered full/half-duplex operation
• 4-16 data bits
• 2× Universal Asynchronous Receiver/Transmitter
• Triple buffered full/half-duplex operation
• 8-9 data bits
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode

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•Timers/Counters
• 4× 16-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit and 1× 32-bit Real-Time Counter
• 3× 8/16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
• Single ended or differential operation
• Conversion tailgating for predictable latency
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• Up to 3 Operational Amplifiers
• Supports rail-to-rail inputs and outputs
• Programmable gain
• 2× Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Supply Voltage Comparator
•Ultra low power sensor interface
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
3.3.2 System Features
•Ultra efficient Power-on Reset and Brown-Out Detector
•Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
•Temperature range -40 - 85°C
•Single power supply 1.98 - 3.8 V
•Packages
• QFN64
• TQFP64
• LQFP100
• LFBGA112
• VFBGA120
• Full wafer
3.4 Energy Modes
There are five different Energy Modes (EM0-EM4) in the EFM32GG, see Table 3.1 (p. 8). The
EFM32GG is designed to achieve a high degree of autonomous operation in low energy modes. The
intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short

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wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy
consumption.
Tip
Throughout this document, the first figure in every module description contains an Energy Mode
Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ).
Table 3.1. Energy Mode Description
Energy Mode Name Description
01 2 3 4 EM0 – Energy Mode 0
(Run mode)
In EM0, the CPU is running and consuming as little as 219 µA/MHz, when
running code from flash. All peripherals can be active.
01 2 3 4 EM1 – Energy Mode 1
(Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 80 µA/MHz. All peripherals, including DMA, PRS and memory system, are still available.
01 2 3 4 EM2 – Energy Mode 2
(Deep Sleep Mode)
In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz
oscillator running, selected low energy peripherals (LCD, RTC, LETIMER,
PCNT, LEUART, I2C, LESENSE, OPAMP, USB, WDOG and ACMP) are still
available. This gives a high degree of autonomous operation with a current
consumption as low as 1.1 µA with RTC enabled. Power-on Reset, Brown-out
Detection and full RAM and CPU retention is also included.
01 2 3 4 EM3 - Energy Mode 3
(Stop Mode)
In EM3, the low-frequency oscillator is disabled, but there is still full CPU
and RAM retention, as well as Power-on Reset, Pin reset, EM4 wake-up
and Brown-out Detection, with a consumption of only 0.8 µA. The low-power
ACMP, asynchronous external interrupt, PCNT, and I2C can wake-up the
device. Even in this mode, the wake-up time is a few microseconds.
01 2 3 4 EM4 – Energy Mode 4
(Shutoff Mode)
In EM4, the current is down to 20 nA and all chip functionality is turned off
except the pin reset, GPIO pin wake-up, GPIO pin retention, Backup RTC
(including retention RAM) and the Power-On Reset. All pins are put into their
reset state.
3.5 Product Overview
Table 3.2 (p. 8) shows a device overview of the EFM32GG Microcontroller Series, including
peripheral functionality. For more information, the reader is referred to the device specific datasheets.
Table 3.2. EFM32GG Microcontroller Series
EFM32GG Part # Flash RAM GPIO(pins) USB LCD USART+UART LEUART I2C Timer(PWM) LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI LESENSE Op-Amps Package
230F512 512 128 56 - - 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y - Y 3 QFN64

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EFM32GG Part # Flash RAM GPIO(pins) USB LCD USART+UART LEUART I2C Timer(PWM) LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI LESENSE Op-Amps Package
230F1024 1024 128 56 - - 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y - Y 3 QFN64
232F512 512 128 53 - - 3 2 2 4
(11) 1 1311 (8) 2 (2) 2 (16) Y - Y 3 TQFP64
232F1024 1024 128 53 - - 3 2 2 4
(11) 1 1311 (8) 2 (2) 2 (16) Y - Y 3 TQFP64
280F512 512 128 86 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 LQFP100
280F1024 1024 128 86 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 LQFP100
290F512 512 128 90 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 LFBGA112
290F1024 1024 128 90 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 LFBGA112
295F512 512 128 93 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 VFBGA120
295F1024 1024 128 93 - - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 VFBGA120
330F512 512 128 53 Y - 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y - Y 3 QFN64
330F1024 1024 128 53 Y - 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y - Y 3 QFN64
332F512 512 128 50 Y - 3 2 2 4
(11) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 TQFP64
332F1024 1024 128 50 Y - 3 2 2 4
(11) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 TQFP64
380F512 512 128 83 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y Y 3 LQFP100
380F1024 1024 128 83 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y Y 3 LQFP100
390F512 512 128 87 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y Y 3 LFBGA112
390F1024 1024 128 87 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y Y 3 LFBGA112
395F512 512 128 93 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 VFBGA120
395F1024 1024 128 93 Y - 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y Y 3 VFBGA120
840F512 512 128 56 - 8x20 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (8) Y - Y 3 QFN64
840F1024 1024 128 56 - 8x20 3 2 2 4
(12) 1 1311 (8) 2 (2) 2 (8) Y - Y 3 QFN64
842F512 512 128 53 - 8x18 3 2 2 4
(11) 1 1311 (8) 2 (2) 2 (8) Y - Y 3 TQFP64
842F1024 1024 128 53 - 8x18 3 2 2 4
(11) 1 1311 (8) 2 (2) 2 (8) Y - Y 3 TQFP64
880F512 512 128 86 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 LQFP100
880F1024 1024 128 86 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 LQFP100
890F512 512 128 90 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 LFBGA112

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EFM32GG Part # Flash RAM GPIO(pins) USB LCD USART+UART LEUART I2C Timer(PWM) LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI LESENSE Op-Amps Package
890F1024 1024 128 90 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 LFBGA112
895F512 512 128 93 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 VFBGA120
895F1024 1024 128 93 - 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 VFBGA120
900F512 512 128 93 Y 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 Wafer
900F1024 1024 128 93 Y 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 Wafer
940F512 512 128 53 Y 8x18 3 2 2 4
(12) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 QFN64
940F1024 1024 128 53 Y 8x18 3 2 2 4
(12) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 QFN64
942F512 512 128 50 Y 8x16 3 2 2 4
(11) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 TQFP64
942F1024 1024 128 50 Y 8x16 3 2 2 4
(11) 1 1311 (8) 2 (2) 1 (4) Y - Y 3 TQFP64
980F512 512 128 83 Y 8x34 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y1Y 3 LQFP100
980F1024 1024 128 83 Y 8x34 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y1Y 3 LQFP100
990F512 512 128 87 Y 8x34 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y1Y 3 LFBGA112
990F1024 1024 128 87 Y 8x34 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (12) Y Y1Y 3 LFBGA112
995F512 512 128 93 Y 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 VFBGA120
995F1024 1024 128 93 Y 8x36 3+2 2 2 4
(12) 1 1311 (8) 2 (2) 2 (16) Y Y1Y 3 VFBGA120
1EBI and LCD overlaps in the part. Only a reduced pin count LCD driver can be used simultaneously with the EBI.
3.6 Device Revision
The device revision number is read from the ROM Table. The major revision number and the chip family
number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and
PID3 registers, as illustrated in Figure 3.3 (p. 10). The Fam[5:2] and Fam[1:0] must be combined
to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to
form the complete revision number.
Figure 3.3. Revision Number Extraction
PID1 (0xE00FFFE4)
31:4 3:0
PID0 (0xE00FFFE0)
31:8 7:6 5:0
Major Rev[5:0]
PID3 (0xE00FFFEC)
31:8 7:4 3:0
Minor Rev[3:0]
Fam[1:0] Fam[5:2]
PID2 (0xE00FFFE8)
31:8 7:4 3:0
Minor Rev[7:4]