Sony MZ-E80 User manual

MICROFILM
SERVICE MANUAL
PORTABLE MINIDISC PLAYER
E Model
Tourist Model
Model Name Using Similar Mechanism MZ-E55
Mechanism Type MT-MZE55-150
Optical Pick-Up Name ODX-1B
SPECIFICATIONS
MZ-E80
US and foreign patents licensed from Dolby
Laboratories Licensing Corporation.
Photo: Silver
Ver 1.1 2000. 05
With SUPPLEMENT-1
(9-927-132-82)

– 2 –
TABLE OF CONTENTS
1. SERVICING NOTES ............................................... 2
2. GENERAL ................................................................... 3
3. DISASSEMBLY ......................................................... 4
4. TEST MODE.............................................................. 6
5. ELECTRICAL ADJUSTMENTS......................... 10
6. DIAGRAMS
6-1. Block Diagram ................................................................ 11
6-2. Printed Wiring Boards .................................................... 16
6-3. Schematic Diagram ......................................................... 19
6-4. IC Pin Function Description ........................................... 28
7. EXPLODED VIEWS................................................ 35
8. ELECTRICAL PARTS LIST ............................... 37
Flexible Circuit Board Repairing
• Keep the temperature of the soldering iron around 270 ˚C dur-
ing repairing.
• Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
• Be careful not to apply force on the conductor when soldering
or unsoldering.
Notes on chip component replacement
• Never reuse a disconnected chip component.
• Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK !OR DOTTED
LINE WITH MARK !ON THE SCHEMATIC DIAGRAMS
AND IN THE PARTS LIST ARE CRITICAL TO SAFE
OPERATION. REPLACE THESE COMPONENTS WITH
SONY PARTS WHOSE PART NUMBERS APPEAR AS
SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUB-
LISHED BY SONY.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous ra-
diation exposure.
SECTION 1
SERVICING NOTES
This MiniDisc player is classified as a CLASS 1
LASER product.
The CLASS 1 LASER PRODUCT label is located
on the bottom exterior.
• Removing the mechanism deck causes this set to be disabled
during a repair with the power supplied to the set. Therefore,
lock convex portion of open/close detect switch (S801) during
a repair.
• Replacement of CXD2663GA (IC601) used in this set requires
a special tool. Therefore, it cannot be replaced.
Mechanism deck section
Open/close detect
switch (S801)

– 3 –
SECTION 2
GENERAL
1OPERATE indicator
2HOLD switch
3DIGITAL MEGABASS switch
4AVLS switch
5Battery cover
6VOLUME +/– buttons
7MD operate buttons
+/”( FF • PLAY )
=(REW )
p(STOP)
8External battery terminal (+/–)
9OPEN switch
!º 2REMOTE jack
1Headphone
2MD operate switch
”/+(PLAY • FF)
=(REW)
3VOL +/– buttons
4Display window
5DISPLAY button
6PLAYMODE button
7P(PAUSE) button
8HOLD cswitch
9p(STOP) button
8
7
6
5
4
3
21
0
9
8
7
6
5
4
321
9
• LOCATION OF CONTROLS
– Main Unit –
– Remote commander with headphone –

– 4 –
UPPER LID ASSY
MECHANISM DECK SECTION (MT-MZE55-150)
Note: Follow the disassembly procedure in the numerical order given.
SECTION 3
DISASSEMBLY
Set Upper lid assy Mechanism deck
section
(MT-MZE55-150)
SW boardMain Board, Audio board
Optical pick-up section
• This set can be disassembled in the order shown below.
5 two screws
(M1.4
× 1.6)
6 fulcrum plate (L)
assy
main section
7 upper lid assy
1 knob (open)
2
4
screw (M1.4 × 1.3)
3 lid
(battery case)
1 screw
(B1.4
× 3)
1 two screws
(B1.4
× 2.3)
2 Open slider assy
main board
main section
5 mechanism deck section
4 flexible board
(CN501)
3 flexible board
(CN551)

– 5 –
MAIN BOARD, AUDIO BOARD
OPTICAL PICK-UP SECTION
8 main board
5 bracket
4 screw
(B1.4
× 2.5)
4 screw
(B1.4
× 2.3)
9 audio board * 1
1 claw
2 lid (battery case)
3
battery case
6 screw
(1.4
× 3)
7 fulcrum plate
(R) assy
bottom panel ass
y
6 screw
(1.4
× 2)
3 SW board
2 flexible board
1 caution label * 2
battery case
main board
* 1 Note: In removing the Audio board, raise the
connector section uprightly.
* 2 Note: If the SW board or flexible board is removed,
the caution label (4-213-092-01) on the flex-
ible board will be defaced or deformed, and
replace it with a new label.
2 flexible board
4 optical pick-up
section
3 screw
(M1.4
× 2.5)
chassis assy
1 flexible board
adhesive sheet
SW BOARD

– 6 –
100 V1. 000
ROM version display
SHUF
LCD on remote commander
SECTION 4
TEST MODE
Outline
• In this set, overall adjustment mode is made available by enter-
ing test mode to perform automatic adjustment of CD and MO.
In the overall adjustment mode, the disc is determined whether
it is CD or MO and adjustments are performed in sequence. If a
fault is found, the location of the fault is displayed. Also, in
servo mode, each adjustment can be automatically made.
• Operation in the test mode is performed with the remote com-
mander. A key having no particular description in the text, indi-
cates a remote commander key.
Setting theTest Mode
To enter the test mode, two methods are available :
1. Entering method with key input.
Turn on the HOLD switch on the set. While pressing the p
key on the set, press the following remote commander keys in
the following order :
”/+n”/+n=n=n”/+n=n
”/+n=nPnP
2. Entering method by shorting the test point
Solder bridge the test point TAP805 (TEST) on the MAIN
board (connect IC801 pin #£ to GND), and turn on the power.
– MAIN BOARD (Conductor side) –
Releasing theTest Mode
A test mode releasing method varies depending on the test mode
setting method.
1. When test mode was entered with key input, turn off the power.
2. When test mode was entered by shorting the test point, turn
off the power and open the solder bridge of TAP805 (TEST
MODE) on the MAIN board.
Operation of Setting onTest Mode
When the test mode is set, the LCD displays the following :
• The cycle - the above ROM version display nAll lit nAll
off - is repeated.
• When the PLAYMODE key is pressed and hold down, the dis-
play at that time is held so that display can be checked.
Test mode
Short:Test mode
Open: Normal mode
()
” / + key
” / + key
p key
p key
p key
p key
VOL
+ key
VOL
– key
(044 Start?)
Overall
adjustment
mode (044 Auto?)
Adjustment
mode
(044 Manu?) Servo mode
0 0 0
Audio mode
1 0 0
Power mode
3 0 0
VOL +/– keys
VOL
+/– keys
Display when test mode
is set
VOL
+/– keys
Displays of the LCD on the remote commander
are shown in parenthesis.
Configuration ofTest Mode
The test mode has the configuration given below.
Servo Mode
• Set the test mode, press the VOL – key and use the ”/+key
to set the servo mode.
• When the servo mode is set, use the +/”key and the =
key on the set to move the optical pick-up to the outer circum-
ference and to the inner circumference respectively.
• When entering another mode, refer to the configuration of test
mode.
1. Structure of Servo Mode
Servo mode
0 0 0
Offset adjustment
0 1 0
Laser power
adjustment
0 2 0
011 to 014
* 1
021 to 024
* 1
23
1
p
key
p key
p key
p key
” / + key
” / + key
” / + key
” / + key
” / + key
VOL
+/– keys
VOL
+/– keys
(See page 7.)
* 1 Repeatedly press ” / + key
to change the mode.
(Refer to the following list
for a description of each
mode.)

– 7 –
(See page 6.)
p key
p key
p key
p key
MO adjustment
0 3 0
031
to 039
03a to 03f 
*
1
p key
p key
CD adjustment
0 5 0
051
to 059
05a to 05f
* 1
p key
p key
Sled movement
0 6 0
061
, 062
*
1
” / + key
041 to 048
*
1
” / + key
Low reflection
CD adjustment
0 4 0
p key
p key
p key
p key
VOL
+/– keys VOL
+/– keys VOL
+/– keys VOL
+/– keys VOL
+/– keys VOL
+/– keys
NV relation
0 9 0
091
to 093
*
1
” / + key
” / + key
” / + key
” / + key
” / + key
” / + key
” / + key
071 to 074
*
1
” / + key
Automatic
adjustment
0 7 0
23
1
Retern the Offset
adjustment (
0 1 0 )
* 1 : Repeatedly press ” / + key
to change the mode.
(Refer to the following list
for a description of each
mode.)
2. Description of Each Mode
010 Offset adjustment
Mode Description
011 VC offset, FE offset, ABCD offset
012 Not used
013 Not used
014 Not used
020 Laser power adjustment
Mode Description
021 MO power (GRV)
022 MO power (LPIT)
023 CD power (HPIT)
024 Not used
030 MO adjustment
Mode Description
031 MO EF balance
032 MO tracking offset
033 MO ABCD gain
034 MO focus gain
035 MO tracking gain
036 MO focus bias
037
038
039
(03a)
(03b)
(03c)
(03d) Not used
(03e) Not used
(03f) Not used
040 Lower reflection CD adjustment
Mode Description
041 Lower reflection CD EF balance
042 Lower reflection CD tracking offset
043 Lower reflection CDABCD gain
044 Lower reflection CD focus gain
045 Lower reflection CD tracking gain
046 Lower reflection CD focus bias
047
048 Not used

– 8 –
050 CD adjustment
Mode Description
051 CD EF balance
052 CD tracking offset
053 CD ABCD gain
054 CD focus gain
055 CD tracking gain
056 CD focus bias
057
058
059
(05a)
(05b)
(05c)
(05d) Not used
(05e) Not used
(05f) Nor used
060 Sled movement
Mode Description
061 Sled in
062 Sled out
070 Automatic adjustment
Mode Description
071 Focus search
072 Access 32
073 Not used
074 Not used
090 NV relation
Mode Description
091 NV clear
092 Power OFF
093 Function code change
Note: The parenthesizal mode numbers in table are not displayed on the
LCD of remote commander.
Audio Mode
• Enter the test mode and press the VOL – key. Then, press the
”/+key and theVOL + key in this turn to enter audio mode.
• When entering another mode, refer to the configuration of test
mode.
1. Structure of Audio Mode
Audio mode
1 0 0
Audio playback test
1 1 0
3 kHz Beep sound
1 1 1
p key
p key
” / + key
” / + key
” / + key

– 9 –
Power mode
3 0 0
UNREG check
31 0
Power OFF
3 1 1
p key
p key
” / + key
” / + key
” / + key
044 Auto?
Start ?
CD automatic
adjustment
MO automatic
adjustment
OK
NG
OK
NG
Overall
adjustment
mode
Auto?
Adjustment
mode
Manu ?
p key
p key
p key
p key
” / + key (to discriminate between CD and MO)
” / + key
Power Mode
• Enter the test mode and press theVOL – key. Then, press the ”/
+key and the VOL – key in this turn to enter power mode.
• When entering another mode, refer to the configuration of test
mode.
1. Structure of Power Mode
Overall Adjustment Mode
• Enter the test mode and press the VOL + key to enter overall
adjustment mode.
• When entering another mode, refer to the configuration of test
mode.
• When the overall adjustment mode is entered, the LCD on the
remote commander display the following :
1. Structure of Overall Adjustment Mode

– 10 –
SECTION 5
ELECTRICAL ADJUSTMENTS
Notes for Adjustment
• In this set, automatic adjustment of CD and MO can be per-
formed by entering the test mode. (See page 6)
• Adjustments are performed in the overall adjustment mode. If
an item is determined as NG, the item is readjusted in servo
mode.
Adjustment Method in Overall Adjustment Mode
1. Enter the test mode and press the VOL + key to enter overall
adjustment mode.
2. Insert the CD test disc TDYS-1 (Parts No. 4-963-646-01) or
SONY MO disc (recorded) commercially available.
3. Press the ”/+key. The disc is determined whether it is CD
or MO and each adjustment mode is set. Automatic adjust-
ments are performed in the order of the items listed below.
• In CD Automatic adjustment Mode
No. Mode Description
1061 Sled in
2062 Sled out
3071 Focus search
4051 CD EF balance
5053 CD ABCD gain
6051 CD EF balance
7052 CD tracking offset
8054 CD focus gain
9055 CD tracking gain
10 056 CD focus bias
• In MO Automatic adjustment Mode
No. Mode Description
1061 Sled in
2062 Sled out
3071 Focus search
4031 MO EF balance
5033 MO ABCD gain
6031 MO EF balance
7032 MO tracking offset
8034 MO focus gain
9035 MO tracking gain
10 036 MO focus bias
* Remote commander display during automatic adjustment
4. If result of automatic adjustment is OK, the following display
appears.
5. If result of automatic adjustment is NG, the following display
appears.
* If NG, enter servo mode to perform automatic adjustment of the
item determined as NG.
Adjustment in Servo Mode Method
1. When each adjustment mode is set according to the structure
of servo mode, the lower two digits of the mode No. and the
adjustment value written in EEPROM are displayed and lit on
the LCD on the remote commander. (See page 6)
2. When the Pkey is pressed, the following display appears and
the automatic adjustment is performed.
Note: Although theVOL +/– keys can be used to change the adjust-
ment value to any value, they should not be used whenever
possible.
3. When the automatic adjustment is completed, the flashing ad-
justment value is lit.
055  
Adjustment value (flashing)
Mode No. under adjustment
056  End-OK 
052  NG 
Error code
NG mode No.
052  
Adjustment value (lit)
Mode No.
052  
Adjustment value (flashing)
052  
Ad
j
ustment value
(
lit
)

MZ-E80
BRUSHLESS
MOTOR
CONTROL
F
C B
D A
E
I J
J
I
B
A
C
D
E
F
DETECTOR
1
2J
I
4
5
6
7
A
B
C
D
8
9
E
F
LDPD
LASER DIODE
ILCC
PD
OPTICAL PICK-UP
(ODX-1B)
AUTOMATIC
POWER
CONTROL
Q502
LASER ON
SWITCH
Q501, 503
11
10
APC
PD
LD/PD
AMP
APCREF
I-V
AMP
I-V
AMP
AT
AMP B.P.F. 29 30
WBL
ADFM ADIN
32
ADFG
ABCD
AMP
FOCUS
ERROR AMP
TRACKING
ERROR AMP
35
34
26
28
ABCD
FE
TE
SE
V-I
CONVERTER
20
F0CNT WBL
3T EQ
SERIAL/
PARALLEL
CONVERTER,
DECODER
COMMAND
1716 18
SWDT
SCLK
XLAT
RF AMP
B.P.F.
46
RFO 40 RF AGC
& EQ
AGCI
EQ
38
RF
RF AMP,
FOCUS/TRACKING ERROR AMP
IC501
TEMP
48 47
MORFO
MORFI
3T
PEAK &
BOTTOM
WBL
33
AUX
37
PEAK
36
BOTM
PLL
FILTER
81
80
83
82
FILI
PCO
CLTV
FILO
74
75
78
ASYO
ASYI
RFI
ADIP
DEMODULATOR/
DECODER
99 ADFG
SUBCODE
PROCESSOR
D/A
CONVERTER
LOW-PASS
FILTER
DIGITAL
AUDIO
INTERFACE
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO SIGNAL PROCESSOR,
EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER,
D/A CONVERTER, /16M BIT D-RAM
IC601
INTERNAL BUS
D-RAM
CPU
INTERFACE
MONITOR
CONTROL
13
SQSY
16
XINT
11 10 6 7 8
SENS SRDT SWDT SCLK XLAT
2345
MNT0 MNT1 MNT2 MNT3
64 - 6747 – 52, 55 – 59, 70
D0 – D3A00 – A11
71
72
60
63
XOE
XWE
XRAS
XCAS
12
•SIGNAL PATH
: PLAYBACK
COMPA-
RATOR
EFM/ACIRC
ENCODER/DECODER
SHOCK PROOF
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
SLED MOTOR
CONTROL
Q551,552
UNREG B+
30 P02
28 P01
DC/DC
DRIVE
DC/DC
DRIVE 33
32
P12
P11
24205240
VM4
VM2
VD
VD2
TRACKING
COIL
DRIVE
43
45
60
59
F13
R13
FOCUS
COIL
DRIVE
49
47
57
58
F11
R11
SLED
MOTOR
DRIVE1
53
51
55
56
F12
R12
SLED
MOTOR
DRIVE2
39
41
62
61
F14
R14
2-AXIS
DEVICE
(TRACKING)
(FOCUS)
TRK–
FCS+
FCS–
SPINDLE
MOTOR
DRIVE
21
23
25
36
35
HIU
HIV
34
HIW
SLEEP UP/DOWN
/POWER SW
DECODER
71
63
72
1NOTE
18 17 16
OE
PWM
D1
HOW
HOV
HOU
R04
F04
R02
F02
R01
F01
R03
F03
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC551
88
84
85
86
87
96
95
ANALOG
MUX
A/D CONVERTER
103
104
105
102
117
118
106
110
109
111
112
114
115
142
141
124
133
134
135
140
AUTO
SEQUENCOR
SPINDLE
SERVO
PWM GENERATOR
127
128
129
130
131
132
138
139
DIGITAL SERVO
SIGNAL PROCESS
113
45
46
47
38
39
42
24
37
1
BGR
19
TRACKING
VOLTAGE
MONITOR
IC502
27 28 52 65 66 64 67 56 57 58 69
EEPROM
IC802
9 76 75 74 73
7 1 2 3 4
PE CS BK DI DO
20
19
OSCILLATOR
CELL
27
24
34
38
45
43
46
42
33 31 23 51 29 30 17 16 8
S804-808
44
69
6
68
34
63
7
71
70
60
21
22
15 BEEP 24
23
2
4
17 18 13
HEADPHONE AMP
IC301
INB
INA
BEEP IN
OUTB
OUTA
BEEP OUTA
BEEP OUTB
MT SW PW SW VREF IN
REFERENCE
VOLTAGE
SWITCHING
Q301
B+
GND
KEY
DATA
VDD
J301
2REMOTE
12
B+ SWITCH
Q902
VG B+ B+ SWITCH
Q901
DC/DC
CONVERTER
IC902
D903
Q903
+2V
REGULATOR
IC504
+2.2V
REGULATOR
IC503
B+
(+2.2V)
B+
(+2V)
10
8
33
28
30
34
35
31
13
17
14
16
18
4
RESET
SYSTEM
CONTROL
XWK3
CLK
SLEEP
XWK2
XWK1
FFCLR
CHARGE
PUMP
VG B+
COMPARATOR
23
OSC1
STEP-UP
DC/DC
CONVERTER
25
26
PWM1
MODE
SELECT 21
22
XRST
XRST
S801
(OPEN/CLOSE)
M
M502
(SLED)
SLED
VOLTAGE
MONITOR
IC552(1/2)
SLED
VOLTAGE
MONITOR
IC552(2/2)
W
UV
D901
INM
VG
C1H
C1L
C2H
C2L
VC
SW
VBH
VB1
D1
DRY BATTERY
SIZE " AA "
(IEC DESIGNATION R6)
1PCS. 1.5V
–+
DC IN 1.5V
(BATTERY CASE)
RECHAGEBLE
BATTERY
(NICKEL-METAL)
NH-14WN 1.2V
UNREG B+
PWM1
POWER SUPPLY
IC901
X801
16.9344MHz
S301
DIGITAL MEGABASS
0 1 2
S803
AVLS
NORM LIMIT
S802
HOLD
OFF HOLD
D801
OPERATE
TAP805
TEST
OPEN : NORMAL MODE
SHORT : TEST MODE
BEEP
HP MUTE
HP STBY
REC KEY
RMC DTCK
RMC VCON
SLEEP
OPEN CLS SW
XWK CLR
V28 CON
SET KEY XOUT XIN DBB1 DBB0 AVLS SW HOLD SW OPR LED ADJUST
THOLD
LD ON
XRFSW
CLV VCON
CLV W MON
CLV V MON
CLV U MON
SLD 2 MON
SLD 1 MON
U0
V0
W0
U0
V0
W0
SQSY
XINT
SENSE
SRDT
SWDT
SCLK
XLAT
MNT0 MNT1 MNT2 MNT3
XRESET
NV CSI
NV CLK
NV DO
NV DI
X601
22.5792MHz
AOUTR
AOUTL
DOUT
DATAI
DADT
XRCK
LRCK
FS256
OSCI
OSCO
SYSTEM CONTROLLER
IC801
FS4
SLCU
SLCV
SPCU
SPCV
SPCW
AUX1
PEAK
BOTM
ABCD
FE
TE
SE
XLRF
CKRF
DTRF
F0CNT
SPRD
SPFD
APCREF
TFDR
TRDR
FEDR
FRDR
SRDR
SFDR
BYPS
SLVS
SPVS
SLDU
SLDV
SLDW
SLCW
SPDU
SPDV
SPDW
05
M501
(SPINDLE)
TRK+
W0 V0
U0
XSTBY
SYSTEM CONTROLLER
(IC801) B+
(FOR A/D CONVERTER)
SPDW
SPDV
SPDU
SLCW
SLDW
SLDU
FFDR
TRDR
TFDR
FRDR
SLDV
SWDT
SCLK
XLAT
REMOTE
COMMANDER
B+
IC601
HP MUTE
HP STBY
– 11 – – 12 – – 13 – – 14 –
6-1. BLOCK DIAGRAM
SECTION 6
DIAGRAMS

MZ-E80
– 19 – – 20 – – 21 – – 22 –
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
• % : indicates tolerance.
•¢: internal component.
•C: panel designation.
•A: B+ Line.
• Powervoltage isdc1.5 Vand fed withregulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark : PLAYBACK
• Voltagesaretaken with aVOM(Input impedance 10MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
E: PLAYBACK
Note: The components identified by mark !or dotted line
with mark !are critical for safety.
Replace only with part number specified.
*IC601 is not replaceable
• The voltage and waveform of CSP (chip size package) can-
not be measured, because its lead layout is different form that
of conventional IC.
6-3. SCHEMATIC DIAGRAM • See page 23 for Waveforms. •See page 24 for IC Block Diagrams.
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.

– 23 – – 24 – – 25 – – 26 –
2IC501 @§ (TE)
10 mV/DIV, 1 µs/DIV
3IC501 #¢ (FE)
100 mV/DIV, 1 µs/DIV
4IC501 #• (RF), IC601 &• (RF1)
500 mV/DIV, 10 µs/DIV
6IC551 !§, !¶, !• (U0, V0, W0)
IC601 `⁄‹‚, `⁄‹⁄, `⁄‹¤ (SPCU, SPCV, SPCW)
1 V/DIV, 10 ms/DIV
8IC551 &¡ (PWM), IC901 @™ (PWM1)
2 V/DIV, 2 µs/DIV
9IC601 @£ (OSCO)
1 V/DIV, 20 ns/DIV
!¡ IC801 !§ (XOUT)
500 mV/DIV, 20 ns/DIV
Approx.
340 mVp-p
Approx.
12 mVp-p
Approx.
10 mVp-p
Approx.
1.2 Vp-p
2.4 Vp-p
2.2 ms
2.3 Vp-p
26 ms
4.2 Vp-p
5.7 µ s
1.9 Vp-p
16.9344 MHz
2.7 Vp-p
5.7 µ s
260 mVp-p
5.7 µ s
3 Vp-p
10 µ s
7IC551 #¢, #∞, #§ (HIW, HIV, HIU)
IC601 `⁄¤‡, `⁄¤°, `⁄¤· (SPDU, SPDV, SPDW)
IC801 $•, $ª, %º
(CLV U CON, CLVV CON, CLVW CON)
1 V/DIV, 10 ms/DIV
0IC601 `⁄⁄‹ (FS4), IC901 @• (CLK)
1 V/DIV, 2 µs/DIV
2.9 Vp-p
22.5792 MHz
Approx.
320 mVp-p
2.6 Vp-p
5.7 µ s
1IC501 1, 2(I,J)
100 mV/DIV, 5 µs/DIV
5IC501 $™, $§ (AGCI, RFO)
100 mV/DIV, 5 µs/DIV
!™ IC901 !£, !¢, !§, !¶
(C2L, C1L, C1H, C2H)
1 V/DIV, 2 µs/DIV
!£ IC901 !∞ (VB)
100 mV/DIV, 2 µs/DIV
!¢ IC902 5(LX)
1 V/DIV, 2 µs/DIV
• Waveforms
– MAIN Board –
• IC Block Diagrams
– MAIN Board –
IC501 CXA2523ATQ-T4
–1
–2
+
–
IVR BB
+
–
IVR AA
+
–
IVR CC
+
–
IVR DD
+
–
IVR +
–
EE EE'
EFB TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12APCREF
11APC
10PD
9F
8E
7D
6C
5B
4A
3VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+–
–
+
AUXSW
COMMAND
+
–
IVR
GSW
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
–
–
–
–
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+ –
RFA1
–
–
–
–
1
2
–
–
–
1
2
GRVA
OFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC EQ
EQ
DET
P-P
WBL
3T WBL TEMP
PBH
–
+
USROP
+
–USRC
3T
BPF3T
PEAK3T
1I
2J
RFA3
PBSW
AUX
SW
IV
ESW
EBAL
IC551 MPC17A55FTA
21
22
23
24
25
26
27
28
29
30
235
4678910
111 12 13 14 15 16 17 18
19
20
31
32
33
34
35
36
3738394051525354
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
41424344454647484950
71
72
PRE DRIVER PRE DRIVER PRE DRIVER PREDRIVER
HI–BRIDGE
CONTROL
HI–BRIDGE
CONTROL
HI–BRIDGE
CONTROL
HI–BRIDGE
CONTROL
BIAS
CONTROL
SLEEP UP/DOWN
/POWER SW
DECODER
POWER SW
PRE DRIVER
STEP UP/DOWN
PRE DRIVER
STEP–UP
PRE DRIVER
PRE DRIVER
3 PHASE CONTROL
PRE
DRIVER
PWM
DRIVER
PRE
DRIVER
PWM
DRIVER
VC VC VG VC VC VG VC VC VG VC VC VG
VC VC VG
VC VC VG
VC VC VG
VC
VG
VGVG
VG
VG
VC
VC
VC
VC
REN
ROE
1ntSTB
1ntSTB
1ntOE
DO or DI
F12
R12
F11
R11
R13
F13
R14
F14
OE
VREG
VREG
CONT
CLPF
RGND
VC
GND
VG
PWM
DI
DO
VB1 VB1
VB VB
VB2
LI LI
UO
VO
WO
V0 V0
L2H
L2L
GND
DCC2
GND
DCC1
GND
DCC1
HIU
HIV
HIW
P11
P12
VPS2
PO2
GND
PS
PO1
VPS1
GND
3P2
HOW
VD2
HOV
GND
3PI
HOU
VD
IN
GND H2 FO2 VM2 RO2 GND H12 FO1 VM1 RO1 GND H13 RO3 VM3 FO3 GND H34 RO4 GND H4 VC VM4 FO4
IC601 CXD2663GA
1
2
3
4
5
MONITOR
CONTROL
6
7
8
9
10
CPU I/F
11
12
EACH
BLOCK
EACH
BLOCK
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SUBCODE
PROCESSOR
DAC
OSC CELL
LPF
DIGITAL
AUDIO I/F
S
ATRAC
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
16M
DRAM
SHOCK RESISTANT
MEMORY CONTROLLER
EFM/ACIRC
DECODER
COMP
PLL
ANALOG
MUX
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
103
102
104
105
107
106
108
109
110
111
112
113
114
115
117
116
118
119
120
121
122
123
124
125
126
A/D
CONVERTER
ADIP
DECODER
AUTO
SEQUENCER
PWM
GENERATOR
SERVO DSP
SPINDLE
SERVO
BRUSHLESS MOTOR CONTROL
127128129130131132133134135136137138139140141142143144145146147
XBCK SPFD SPRD SFDR SRDR
168 - 148 VSIO3
VDIO3
SPVS
MTFLGR
TEST3
TEST2
TEST1
FGIN
SPFD
SPRD
VSC4
SFDR
SRDR
FS4
FRDR
FFDR
TFDR
TRDR
VDC4
LDDR
APCREF
DTRF
CKRF
XLRF
FOCNT
VSIO2
VDIO2
ADFG
APC
DCHG
TE
SE
ADRB
AVS2
AVD2
ADRT
ADID
VC
AUX1
FE
ABCD
BOTM
PEAK
CLTV
FILO
FILI
PCO
AVS1
RFI
BIAS
AVD1
ASYI
ASYO
MVCI
XWE
XOE
A11
VSC3
VDC3
D3 D0 D2 D1
XCAS
IXWE
IXOE
XRAS
A09 A08 A10 A07 A00
VSIO1
VDIO1
A06 A01 A05 A02 A04 A03
FS256
XBCK
VSC2
LRCK
DADT
TST7
TST6
TST5
DATAI
VDC2
VDC1
DT72
DOUT
TST4
TST3
XSTL
VSC1
DAVSSR
VREFR
AOUTR
DAVDDR
DAVDDL
AOUTL
VREFL
DAVSSL
VSIOSC
OSCO
OSCI
VDIOSC
TST2
XINT
TST1
MTFLGL
SQSY
XRST
SENS
SRDT
VSCO
XLAT
SCLK
SWDT
MNT3
MNT2
MNT1
MNT0
VDCO
SPDU SPDV SPDW SPCU SPCV SPCW SLDU SLDV SLDW VDC5 VSC5 SLCU SLCV SLCW SLVS BYSP DVSS0 DVDD0 DVSS1 DVDD1 TST8 NC
IC802 AK93C55AV-L
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
INSTRUCTION
REGISTER
ADD
BUFFERS
DATA
REGISTER
R/W AMPS
AND
AUTO ERASE
DECODER
VPP
SW
VREF VPP
GENERATOR
EEPROM
2048bit
128 X 16
2
3
5
4
6
7
8
1VCC
PE
NC
GND
CS
SK
DI
DO

– 27 –
IC901 MPC1830ADTB IC902 XC6383C281MR
21
22
23
24
25
26
27
28
29
30
2
3
5
4
6
7
8
9
10
1
11
12
13
14
15
16
17
18
19
20
31
32
33
34
35
36
GND
VRMC
VREF
INM
RF
DTC
CRST
XRST
VBMON
VC
SPCKI
SPCKO
C2L
C1L
VB
C1H
C2H
VG
BAND GAP
REFERENCE
RESET
VB SELECT
SPCK
BUFF
CHARGE
PUMP
VSTB
VBH
SYSTEM
CONTROL
OSC1
STEP-UP
DC / DC
CONVERTER
PWM1
MODE
SELECT
SAW
OSC2
XWK1
XWK2
XWK3
XWK4
FFCLR
SLEEP
VBSEL
CLK
VB2
VB1
PGND
SW
PWMI
DO
DI
VCON
1
2
3
CHIP
ENABLE
+
–
+
–
VREF
2STEP PFM CONTROL
OSC 100/180kHz
VLX LIMITER 5
4
VDD
CE
VOUT
NC VSS
LX
BUFFER
– AUDIO Board –
IC301 TA2131FL (EL)
V REF
MT
SW
BST
SW
BEEP
19
20
21
22
23
24
18 17 16 15 14 13
PW
SW 12
11
10
8
7
BST1
9
BST2
654321
BST
AGC
PW
B
PW
A
ADD
MT TC
VCC1
INB
INA
BEEP
OUTB
BEEP
OUTA
VCC2
OUTA
PWR
GND
OUTB
DET
A
GC IN
BST OUT
BST NF2
LPF2
BST NF1
LPF1
VREF
VREF IN GND BEEP IN BST SW MT SW PW SW

– 28 –
6-4. IC PIN FUNCTION DESCRIPTION
•MAIN BOARD IC501 CXA2523ATQ-T4 (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No. Pin Name I/O Description
1II
I-V converted RF signal I input from the optical pick-up block detector
2JI
I-V converted RF signal J input from the optical pick-up block detector
3VCO
Middle point voltage (+1.2V) generation output terminal
4 to 9 A to F I Signal input from the optical pick-up detector (A to F)
10 PD I Light amount monitor input from the optical pick-up block laser diode
11 APC O Laser amplifier output terminal to the automatic power control circuit
12 APCREF I Reference voltage input terminal for setting laser power
13 GND — Ground terminal
14 TEMPI I Connected to the temperature sensor Not used (open)
15 TEMPR O Output terminal for a temperature sensor reference voltage Not used (open)
16 SWDT I Writing data input from the CXD2663GA (IC601)
17 SCLK I Serial clock signal input from the CXD2663GA (IC601)
18 XLAT I Serial latch signal input from the CXD2663GA (IC601)
19 XSTBY I Standby control signal input from the system controller (IC801) “L”: standby
20 F0CNT I Center frequency control signal input terminal of internal circuit (BPF22, BPF3T, EQ) input from
the CXD2663GA (IC601)
21 VREF O Reference voltage output terminal Not used (open)
22 EQADJ I Center frequency setting terminal for the internal circuit (EQ)
23 3TADJ I Center frequency setting terminal for the internal circuit (BPF3T)
24 VCC — Power supply terminal (+2.4V)
25 WBLADJ I Center frequency setting terminal for the internal circuit (BPF22)
26 TE O Tracking error signal output to the CXD2663GA (IC601)
27 CSLED I Connected to the capacitor for low-pass filter of the sled error signal
28 SE O Sled error signal output to the CXD2663GA (IC601)
29 ADFM O FM signal output terminal of the ADIP
30 ADIN I Receives a ADIP FM signal in AC coupling
31 ADAGC I Connected to the external capacitor for ADIP AGC
32 ADFG O ADIP duplex FM signal (22.05 kHz ±1 kHz) output to the CXD2663GA (IC601)
33 AUX O Auxiliary signal (I3signal/temperature signal) output to the CXD2663GA (IC601)
34 FE O Focus error signal output to the CXD2663GA (IC601)
35 ABCD O Light amount signal output to the CXD2663GA (IC601)
36 BOTM O Light amount signal (RF/ABCD) bottom hold output to the CXD2663GA (IC601)
37 PEAK O Light amount signal (RF/ABCD) peak hold output to the CXD2663GA (IC601)
38 RF O Playback EFM RF signal output to the CXD2663GA (IC601)
39 RFAGC I Connected to the external capacitor for RF auto gain control circuit
40 AGCI I Receives a RF signal in AC coupling
41 COMPO O User comparator output terminal Not used (open)
42 COMPP I User comparator input terminal Not used (fixed at “L”)
43 ADDC I Connected to the external capacitor for cutting the low band of the ADIP amplifier
44 OPO O User operational amplifier output terminal Not used (open)
45 OPN I User operational amplifier inversion input terminal Not used (fixed at “L”)
46 RFO O RF signal output terminal
47 MORFI I Receives a MO RF signal in AC coupling
48 MORFO O MO RF signal output terminal

– 29 –
•MAIN BOARD IC601 CXD2663GA
Pin No. Pin Name I/O Description
1 VDCO — Power supply terminal (+2V) (for internal logic)
2 MNT0 O Signal indicating the speed follow-up spinning mode output to the system controller (IC801)
“H”: speed follow-up spinning mode
3 MNT1 O Sled motor operation monitor signal output to the system controller (IC801) “H”: monitor drive
4 MNT2 O Speed limiter signal output to the system controller (IC801) “L”: limiter on
5 MNT3 O Window signal to detect an inverse trigger edge output to the system controller (IC801)
“H”: edge detectable
6 SWDT I Writing data input from the system controller (IC801)
7 SCLK I Serial clock signal input from the system controller (IC801)
8 XLAT I Serial data latch pulse input from the system controller (IC801)
9 VSCO — Ground terminal (for internal logic)
10 SRDT O Reading data output to the system controller (IC801)
11 SENS O Internal status (SENSE) output to the system controller (IC801)
12 XRST I System reset signal input from the MPC1830ADTB (IC901) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13 SQSY O Subcode Q sync (SCOR) output the system controller (IC801)
“L”: is output every 13.3 msec Almost all, “H” is output
14 MTFLGL O Muting applied to analog signal input in non-signal status causes the signal to be “H”
automatically Not used
15 TST1 I Input terminal for the test (fixed at “L”)
16 XINT O Interrupt status output to the system controller (IC801)
17 TST2 I Input terminal for the test (fixed at “L”)
18 VDIOSC — Power supply terminal (+2.4V) (for oscillator cell)
19 OSCI I System clock (512Fs=22.5792 MHz) input terminal
20 OSCO O System clock (512Fs=22.5792 MHz) output terminal
21 VSIOSC — Ground terminal (for oscillator cell)
22 DAVSSL — Ground terminal (for internal D/A converter L-ch)
23 VREFL O Reference voltage output terminal (for internal D/A converter L-ch)
24 AOUTL O Playback analog signal (L) output to the headphone amplifier (IC301)
25 DAVDDL — Power supply terminal (+2.4V) (for internal D/A converter L-ch)
26 DAVDDR — Power supply terminal (+2.4V) (for internal D/A converter R-ch)
27 AOUTR O Playback analog signal (R) output to the headphone amplifier (IC301)
28 VREFR O Reference voltage output terminal (for internal D/A converter R-ch)
29 DAVSSR — Ground terminal (for internal D/A converter R-ch)
30 VSC1 — Ground terminal (for internal logic)
31 XTSL I Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
32, 33 TST3, TST4 I Input terminal for the test (normally : fixed at “L”)
34 DOUT O Digital audio signal output terminal when playback mode Not used (open)
35 DT72 O Not used (open)
36, 37 VDC1, VDC2 — Power supply terminal (+2V) (for internal logic)
38 DATAI I Input terminal of external audio data to the internal D/A converter Not used (open)
39 to 41 TST5 to TST7 I Input terminal for the test (normally : fixed at “L”)
42 DADT O Playback data signal output to the external D/A converter Not used (open)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, D/A CONVERTER, 16M BIT D-RAM)

– 30 –
Pin No. Pin Name I/O Description
43 LRCK O L/R sampling clock signal (44.1 kHz) output to the external D/A converter Not used (open)
44 VSC2 — Ground terminal (for internal logic)
45 XBCK O Bit clock signal (2.8224 MHz) output to the external D/A converter Not used (open)
46 FS256 O Clock signal (11.2896 MHz) output to the external D/A converter Not used (open)
47 to 52 A03, A04, A02,
A05, A01, A06 O Address signal output to the external D-RAM Not used (open)
53 VDIO1 — Power supply terminal (+2.2V) (for I/O cell)
54 VSIO1 — Ground terminal (for I/O cell)
55 to 59 A00, A07, A10,
A08, A09 O Address signal output to the external D-RAM Not used (open)
60 XRAS O Row address strobe signal output to the external D-RAM “L” active Not used (open)
61 IXOE O Output enable signal output terminal “L” active Not used (open)
62 IXWE O Data write enable signal output terminal “L” active Not used (open)
63 XCAS O Column address strobe signal output to the external D-RAM “L” active Not used (open)
64 to 67 D1, D2, D0, D3 I/O Two-way data bus with the external D-RAM Not used (open)
68 VDC3 — Power supply terminal (+2V) (for internal logic)
69 VSC3 — Ground terminal (for internal logic)
70 A11 O Address signal output to the external D-RAM Not used (open)
71 XOE O Output enable signal output to the external D-RAM “L” active Not used (open)
72 XWE O Data write enable signal output to the external D-RAM “L” active Not used (open)
73 MVCI I Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
74 ASYO O Playback EFM full-swing output terminal
75 ASYI I Playback EFM asymmetry comparator voltage input terminal
76 AVD1 — Power supply terminal (+2.4V) (analog system)
77 BIAS I Playback EFM asymmetry circuit constant current input terminal
78 RFI I Playback EFM RF signal input from the CXA2523ATQ (IC501)
79 AVS1 — Ground terminal (analog system)
80 PCO O Phase comparison output for master clock of the recording/playback FEM master PLL
81 FILI I Filter input for master clock of the recording/playback EFM master PLL
82 FILO O Filter output for master clock of the recording/playback EFM master PLL
83 CLTV I Internal VCO control voltage input of the recording/playback EFM master PLL
84 PEAK I Light amount signal (RF/ABCD) peak hold input from the CXA2523ATQ (IC501)
85 BOTM I Light amount signal (RF/ABCD) bottom hold input from the CXA2523ATQ (IC501)
86 ABCD I Light amount signal input from the CXA2523ATQ (IC501)
87 FE I Focus error signal input from the CXA2523ATQ (IC501)
88 AUX1 I Auxiliary signal (I3signal/temperature signal) input from the CXA2523ATQ (IC501)
89 VC I Middle point voltage (+1.2V) input terminal
90 ADIO O Monitor output of the A/D converter input signal Not used (open)
91 ADRT I A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
92 AVD2 — Power supply terminal (+2.4V) (analog system)
93 AVS2 — Ground terminal (analog system)
94 ADRB I A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
95 SE I Sled error signal input from the CXA2523ATQ (IC501)
96 TE I Tracking error signal input from the CXA2523ATQ (IC501)
97 DCHG I Connected to the +2.4V power supply
98 APC I Error signal input for the laser automatic power control Not used (fixed at “H”)

– 31 –
Pin No. Pin Name I/O Description
99 ADFG I ADIP duplex FM signal (22.05 kHz ±1 kHz) input from the CXA2523ATQ (IC501)
100 VDIO2 — Power supply terminal (+2.2V) (for I/O cell)
101 VSIO2 — Ground terminal (for I/O cell)
102 F0CNT O Center frequency control signal output terminal of internal circuit (BPF22, BPF3T, EQ) output to
the CXA2523ATQ (IC501)
103 XLRF O Serial latch signal output to the CXA2523ATQ (IC501)
104 CKRF O Serial clock signal output to the CXA2523ATQ (IC501)
105 DTRF O Writing data output to the CXA2523ATQ (IC501)
106 APCREF O Control signal output to the reference voltage generator circuit for the laser automatic power
control
107 LDDR O PWM signal output for the laser automatic power control Not used (open)
108 VDC4 — Power supply terminal (+2V) (for internal logic)
109 TRDR O Tracking servo drive PWM signal (–) output to the MPC17A55VF (IC551)
110 TFDR O Tracking servo drive PWM signal (+) output to the MPC17A55VF (IC551)
111 FFDR O Focus servo drive PWM signal (+) output to the MPC17A55VF (IC551)
112 FRDR O Focus servo drive PWM signal (–) output to the MPC17A55VF (IC551)
113 FS4 O Clock signal (176.4 kHz) output to the MPC1830ADTB (IC901) (X' tal system)
114 SRDR O Sled servo drive PWM signal (–) output terminal Not used (open)
115 SFDR O Sled servo drive PWM signal (+) output terminal Not used (open)
116 VSC4 — Ground terminal (for internal logic)
117 SPRD O Spindle servo drive PWM signal (–) output terminal Not used (open)
118 SPFD O Spindle servo drive PWM signal (+) output terminal Not used (open)
119 FGIN I FG signal input terminal for spindle servo
120 to 122 TEST1 to TEST3 I Input terminal for the test (normally : fixed at “L”)
123 MTFLGR O Muting applied to analog signal input in non-signal status causes the signal to be “H”
automatically Not used
124 SPVS O Spindle servo drive voltage control signal output to the MPC17A55VF (IC551)
125 VDI03 — Power supply terminal (+2.2V) (for I/O cell)
126 VSI03 — Ground terminal (for I/O cell)
127 SPDU O Spindle servo (U) drive signal output to the MPC17A55VF (IC551)
128 SPDV O Spindle servo (V) drive signal output to the MPC17A55VF (IC551)
129 SPDW O Spindle servo (W) drive signal output to the MPC17A55VF (IC551)
130 SPCU I Spindle servo (U) timing signal input from the MPC17A55VF (IC551)
131 SPCV I Spindle servo (V) timing signal input from the MPC17A55VF (IC551)
132 SPCW I Spindle servo (W) timing signal input from the MPC17A55VF (IC551)
133 SLDU O Sled servo (U) drive signal output to the MPC17A55VF (IC551)
134 SLDV O Sled servo (V) drive signal output to the MPC17A55VF (IC551)
135 SLDW O Sled servo (W) drive signal output to the MPC17A55VF (IC551)
136 VDC5 — Power supply terminal (+2V) (for internal logic)
137 VSC5 — Ground terminal (for internal logic)
138 SLCU I Sled servo (U) timing signal input from the MPC17A55VF (IC551)
139 SLCV I Sled servo (V) timing signal input from the MPC17A55VF (IC551)
140 SLCW I Sled servo (W) timing signal input from the MPC17A55VF (IC551)
141 SLVS O Sled servo voltage control signal output to the MPC17A55VF (IC551)
142 BYPS O By-pass transistor control signal output terminal for the sled drive power supply
143 DVSS0 — Ground terminal (for internal 16M bit D-RAM)

– 32 –
Pin No. Pin Name I/O Description
144 DVDD0 — Power supply terminal (+2.4V) (for internal 16M bit D-RAM)
145 DVSS1 — Ground terminal (for internal 16M bit D-RAM)
146 DVDD1 — Power supply terminal (+2.4V) (for internal 16M bit D-RAM)
147 TST8 I Input terminal for the test Not used (open)
148 to168 NC — Not used (open)