ST STM32F0 Series Installation and operating instructions

February 2013 Doc ID 023035 Rev 2 1/29
AN4080
Application note
Getting started with STM32F0xxx hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the STM32F0xxx product family and describes the minimum hardware
resources required to develop an STM32F0xxx application.
The STM32F0xxx family comprises a sub-group, the STM32F06xxx, which can be
distinguished from the main devices (STM32F05xxx). This sub-family bypasses the internal
voltage regulator to target applications that already have one onboard.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
Table 1. Applicable products
Type Part number
Microcontrollers STM32F05xxx family
STM32F06xxx family
www.st.com

Contents AN4080
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Contents
1 Power supplies of the STM32F05xxx family . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 Independent analog converter supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.1 Power-on reset (POR) / power-down reset (PDR) . . . . . . . . . . . . . . . . . . 7
1.2.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.3 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Power supplies of the STM32F06xxx family . . . . . . . . . . . . . . . . . . . . . 11
2.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Independent analog converter supply . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 External power-on reset and power-down reset (NPOR) . . . . . . . . . . . 13
2.2.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 High speed external clock signal (HSE) OSC clock . . . . . . . . . . . . . . . . . 15
3.2 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 SWD port (serial wire debug) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Serial wire debug (SWD) pin assignment . . . . . . . . . . . . . . . . . . . . . . . 19

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5.3.2 SWD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.3 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . 20
5.3.4 SWD port connection with standard SWD connector . . . . . . . . . . . . . . 20
6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Ground and power supply (VSS, VDD, VDDA) . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.3 STM32F06xxx power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.4 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.5 SWD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.7 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Hardware migration from STM32F1 to STM32F0 . . . . . . . . . . . . . . . . . 27
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power supplies of the STM32F05xxx family AN4080
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1 Power supplies of the STM32F05xxx family
1.1 Power supply schemes
There are a variety of power supply schemes:
●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●VDDA = 2.0 to 3.6 V: external analog power supply for ADC/DAC, Reset blocks, HSI,
HSI14, LSI and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC
and DAC are used).
The VDDA voltage level must always be greater than or equal to the VDD voltage level
and must be provided first.
●VBAT = 1.65 to 3.6 V: power supply for RTC, LSE 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
Figure 1. Power supply scheme
MS19875V2

Analo g:
RCs, PLL,
...
Power switch
VBAT
GP I/O s
OUT
IN Kernel logic
(CPU,
Digital
& Memories)
Backup circuitry
(LSE,RTC,
Backup registers)
2 × 100 nF
+ 1 × 4.7 μF
1.65 -3.6V
Regulator
VDDA
VSSA
ADC/
DAC
Level shifter
IO
Logic
VDD
10 nF
+ 1 μF
VDDA
VREF+
VREF-
VDD
VSS
2 ×
2 ×

AN4080 Power supplies of the STM32F05xxx family
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1.1.1 Independent analog converter supply
To improve conversion accuracy and to extend the supply flexibility, the analog domain has
an independent power supply which can be separately filtered and shielded from noise on
the PCB.
●The ADC and DAC voltage supply input is available on a separate VDDA pin.
●An isolated supply ground connection is provided on pin VSSA.
The VDDA supply can be equal to or higher than VDD. This allows VDD to stay low while still
providing the full performance for the analog blocks.
When a single supply is used, VDDA must be externally connected to VDD,. It is
recommended to use an external filtering circuit in order to ensure a noise free VDDA.
When VDDA is different from VDD, VDDA must be always higher or equal to VDD. To keep safe
potential difference between VDDA and VDD during power-up/power-down, an external
Schottky diode may be used between VDD and VDDA. Refer to the datasheet for the
maximum allowed difference.
Figure 2. Schottky diode connection
1.1.2 Battery backup
To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be
connected to an optional standby voltage supplied by a battery or another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off.
The switch to the VBAT supply is controlled by the power down reset (PDR) circuitry
embedded in the Reset block.
If no external battery is used in the application, it is recommended to connect VBAT
externally to VDD.
1.1.3 Voltage regulator
The voltage regulator is always enabled after reset.
MS30272V1
VDD VDDA
VDD VDDA
Schottky diode

Power supplies of the STM32F05xxx family AN4080
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It works in three different modes depending on the application modes:
●Run mode: the regulator supplies full power to the 1.8 V domain (core, memories and
digital peripherals)
●Stop mode: the regulator supplies low power to the 1.8 V domain, preserving the
contents of the registers and SRAM
●Standby mode: the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup domain. This includes the
following features which can be selected by programming individual control bits:
– Independent watchdog (IWDG): the IWDG is started by writing to its Key register
or by a hardware option. Once started it cannot be stopped except by a reset.
– Real-time clock (RTC): configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR).
– Internal low speed oscillator (LSI): configured by the LSION bit in the
Control/status register (RCC_CSR).
– External 32.768 kHz oscillator (LSE): configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).

AN4080 Power supplies of the STM32F05xxx family
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1.2 Reset and power supply supervisor
1.2.1 Power-on reset (POR) / power-down reset (PDR)
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits
which are always active and ensure proper operation above a threshold of 2 V.
The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, VPOR/PDR, without the need for an external reset circuit.
●The POR monitors only the VDD supply voltage. During the startup phase VDDA must
arrive first and be greater than or equal to VDD.
●The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power
supply supervisor can be disabled (by programming a dedicated option bit
VDDA_MONITOR) to reduce the power consumption if the application design ensures that
VDDA is higher than or equal to VDD.
For more details on the power on / power down reset threshold, refer to the electrical
characteristics section in the datasheet.
Figure 3. Power on reset/power down reset waveform
VDD/VDDA
Reset
40 mV
hysteresis
Temporization
tRSTTEMPO
VPOR
VPDR

Power supplies of the STM32F05xxx family AN4080
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1.2.2 System reset
A system reset sets all registers to their reset values, except the reset flags in the clock
controller CSR register and the registers in the Backup domain. A system reset is generated
when one of the following events occurs:
1. A low level on the NRST pin (external reset).
2. System window watchdog event (WWDG reset).
3. Independent watchdog event (IWDG reset).
4. A software reset (SW reset).
5. Low-power management reset.
6. Option byte loader reset.
7. Power reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In the case of an external reset, the reset is generated while the NRST pin is
asserted low.
Figure 4. Simplified diagram of the reset circuit
Software reset
The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M0 technical
reference manual for more details.
NRST
RPU
V
DD
WWDG reset
IWDG reset
Pulse
generator Power reset
External
reset
(min 20 μs)
System reset
Filter
Software reset
Low-power management reset
Option byte loader reset
MS19841V1

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Low-power management reset
There are two ways to generate a low-power management reset:
1. Entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in
User Option Bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
2. Entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User
Option Bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
Option byte loader reset
The option byte loader reset is generated when OBL_LAUNCH (bit 13) is set in the
FLASH_CR register. This bit launches the option byte loading by software.
Power reset
A power reset sets all registers to their reset values, except the Backup domain. It is
generated when one of the following events occurs.
1. Power-on/power-down reset (POR/PDR reset).
2. Exiting Standby mode.
Backup domain reset
A backup domain reset only affects the backup domain. It is generated when one of the
following events occurs.
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. VDD power up if VBAT has been disconnected when it was low.
3. RTC tamper detection event.
4. Change of the read out protection from level 1 to level 0.

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1.2.3 Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
When enabled, the typical current consumption of this feature is 0.15 µA.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if VDD
is higher or lower than the PVD threshold.
●This event is internally connected to the EXTI line16 and can generate an interrupt if
enabled through the EXTI registers.
●The PVD output interrupt can be generated when VDD drops below the PVD threshold
and/or when VDD rises above the PVD threshold depending on EXTI line16
rising/falling edge configuration. As an example the service routine could perform
emergency shutdown tasks.
Figure 5. PVD thresholds
V
DD
PVD output
100 mV
hysteresis
VPVD threshold