ST STM32F100 Series Installation and operating instructions

October 2010 Doc ID 16896 Rev 2 1/36
AN3127
Application note
CEC networking
using STM32F100xx value line microcontrollers
Introduction
STM32F100xx value line microcontrollers feature a high-definition multimedia interface
consumer electronics control (HDMI™-CEC) controller peripheral that supports the HDMI-
CEC v1.3a protocol. The HDMI-CEC controller provides a hardware support of this protocol,
and it supports the whole set of features offered with CEC devices.
This application note describes the CEC protocol software and hardware implementation
based on the HDMI-CEC controller. A real application example is also provided to illustrate
the software implementation.
www.st.com

Contents AN3127
2/36 Doc ID 16896 Rev 2
Contents
1 High-definition multimedia interface, consumer
electronics control (HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Frame description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Device connectivity and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.1 CEC communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.2 Enhanced DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.3 Hot plug detect (HPD) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.4 Physical address discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.5 Discovery algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.6 Logical addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.7 Logical address allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 STM32F100xx’s HDMI-CEC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.2 HDMI-CEC advanced features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Hardware environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 HDMI connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Package directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Firmware architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Value line evaluation board CEC demonstration . . . . . . . . . . . . . . . . . 27
4.1 CEC demonstration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Device type selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Physical address discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4 Logical address allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Checking the connected devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6 Displaying CEC send/receive information on the LCD . . . . . . . . . . . . . . . 30

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4.6.1 Receive information subscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6.2 Send information subscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

List of tables AN3127
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List of tables
Table 1. Logical addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. HDMI connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. STM32F100xx and HDMI-CEC connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. High-level functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AN3127 List of figures
Doc ID 16896 Rev 2 5/36
List of figures
Figure 1. CEC frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Follower acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. CEC and DDC line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Addresses within a HDMI cluster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Physical address discovery algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. System exits Stop mode when data reception starts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. HDMI cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Electrical schematic proposal for STM32100B-EVAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Electrical schematic proposal for STM32100E-EVAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Example of a hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Package directory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Firmware architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. CEC demonstration flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Device type selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. Physical and logical addresses display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. CEC menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21. Receive flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22. Receive information subscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. Send flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. Select CEC command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Glossary of terms
Broadcast message: a message sent to logical address 15 that all devices are expected to
receive.
Destination: the target device for a CEC message.
Follower: a device that has just received a CEC message and is required to respond to it.
Initiator: the device that is sending, or has just sent, a CEC message and, if appropriate, is
waiting for a follower to respond.
Logical address: a unique address assigned to each device.
Menu-providing device: a non-display device that may render a menu on TV.
Playback device: a device that has the ability to play media, like a DVD player.
Recording device: a device that has the ability to record a source such as an internal tuner
or an external connection.
Source device: a device that is currently providing an AV stream via HDMI.
Tuner device: a device that contains a tuner, e.g. an STB (set-top box) or a recording
device.
TV: a device with a HDMI input that has the ability to display the input HDMI signal.
Generally it has no HDMI output.
CEC: consumer electronics control.
DDC: display data channel.
E-DDC: enhanced display data channel.
EDID: extended display identification data.
E-EDID: enhanced extended display identification data.
HDMI: high-definition multimedia Interface.
(HDMI) source: a device with a HDMI output.
(HDMI) sink: a device with a HDMI input.

AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
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1 High-definition multimedia interface, consumer
electronics control (HDMI-CEC)
1.1 Introduction
Consumer electronics control (CEC) is the appendix supplement 1 to the HDMI (high-
definition multimedia interface) standard.
It is a protocol that provides high-level control functions between all of the various
audiovisual products in a given environment. It is specified to operate at low speeds with
minimum processing and memory overhead.
For more details, refer to the high-definition multimedia interface specification available from
www.hdmi.org.
1.2 Frame description
The CEC bus is a single-wire protocol that can connect up to 10 audiovisual devices through
standard HDMI cabling.
All transactions on the CEC line consist of an initiator and one or more followers. The
initiator is responsible for sending the message structure and the data. The follower is the
recipient of any data and is responsible for setting any acknowledgement bits.
A message is conveyed in a single frame that consists of a start bit followed by a header
block and, optionally, an opcode and a variable number of operand blocks. Figure 1 shows a
CEC frame format.
Figure 1. CEC frame format
Figure 2. Message structure
Start bit
01101101 0-
EOM ACKInitiator Destination
Header block
Header block Databock 1 Datablock n
10 bits10 bits10 bits
Initiator address = 0x6
Destination address = 0xD
Example of Header block:
11100101 0 -
EOM ACK Data
Data block
Data= 0xE5
Example of Datablock:
ai15931
3TART
HIGH (EADER /PCODE /PERAND /PERAND
TOOPERANDS
HIGH
IMPEDANCE BIT IMPEDANCE
AI

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Figure 3. Blocks
All these blocks are made of an 8-bit payload (most significant bit transmitted first) followed
by an end-of-message (EOM) bit and an acknowledge (ACK) bit.
The EOM bit is set in the last block of a message and kept cleared in all others. If a message
contains additional blocks after the EOM, these blocks should be ignored. The EOM bit may
be set in the header block to “ping” other devices and make sure that they are active.
The acknowledge bit is always brought to high impedance by the initiator. It can therefore be
driven low by either the follower that has read its own address in the header, or the follower
that needs to reject a broadcast message.
The header consists of the source logical address field, and the destination logical address
field. Note that the address 0xF is specially used for broadcast messages.
1.3 Bit timing
The format of the start bit is unique and identifies the start of a message. It should be
validated by its low duration and its total duration.
All remaining data bits in the message, after the start bit, have a consistent timing. The high-
to-low transition at the end of the data bit is the start of the next data bit except for the final
bit where the CEC line remains high.
Figure 4 shows the timings of the start bit and the different data bits.
Figure 4. Bit timings
%/- !#+

$%34).!4)/.;=).)4)!4/2;=
(EADERBLOCK
%/- !#+

$!4!;=
/PCODE/PERANDBLOCK
AI
3TARTBIT
HIGHIMPEDANCE
LOWIMPEDANCE
MSMS
MSMS
$ATABIT
HIGHIMPEDANCE
LOWIMPEDANCE
MSMS
MSMS
).)4)!4/2LOGICAL
$ATABIT
HIGHIMPEDANCE
LOWIMPEDANCE
MSMS
MSMS
).)4)!4/2LOGICAL
AI

AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
Doc ID 16896 Rev 2 9/36
CEC Figure 5 shows an example bit with both initiator and follower where the follower may
assert the bit to logical 0 to acknowledge a data block. The initiator outputs a logical 1, thus
allowing the follower to change the CEC state by pulling the control line low for the duration
of the safe sample period.
Figure 5. Follower acknowledge (ACK)
1.4 Device connectivity and addressing
1.4.1 CEC communication
By definition the HDMI system architecture consists of sources and sinks. A given device
may have one or more HDMI input(s) and output(s). Each HDMI input on the device should
follow all the rules for a HDMI sink and each HDMI output should follow all the rules for a
HDMI source.
The DDC is used for configuration and status exchange between a single source and a
single sink. The optional CEC protocol provides high-level control functions between all of
the various audiovisual products in a user’s environment.
Figure 6. CEC and DDC line connections
HIGHIMPEDANCE
LOWIMPEDANCE
HIGHIMPEDANCE
LOWIMPEDANCE
AI
MS
MS
MS
MSMAX
$ATABITINITIATORLOGICAL
$ATABITFOLLOWERLOGICAL

High-definition multimedia interface, consumer electronics control (HDMI-CEC) AN3127
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Figure 7. Addresses within a HDMI cluster
1.4.2 Enhanced DDC
The enhanced DDC described in this section is defined in VESA “ENHANCED DISPLAY
DATA CHANNEL STANDARD Version 1 (September 2, 1999)”. All sinks are required to
support these enhanced DDC features. If the E-EDID structure of a sink is longer than 256
bytes, it should support the segment pointer.
Timing
Data is synchronized with the SCL signal and timing should comply with the Standard Mode
of the I2C specification (100 kHz maximum clock rate).
The I2C bus is a standard two-wire (clock and data) serial databus protocol. Refer to the I2C
specification for details.
Note that a HDMI sink may hold off the DDC transaction by stretching the SCL line during
the SCL-low period following the Acknowledge bit as permitted by the I2C specification. All
HDMI sources should delay the DDC transaction while the SCL line is being held low.
Data transfer protocols
The source should use I2C commands to read information from a sink’s E-EDID with a slave
address.
In Enhanced DDC, a segment pointer is used to address the E-EDID outside the 256 bytes
normally addressable by the 0xA0/0xA1 addresses. The Enhanced DDC protocol sets the
segment pointer before the remainder of the DDC command.

AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
Doc ID 16896 Rev 2 11/36
Segment pointer
Enhanced DDC allows access to up to 32 Kbytes of data. This is accomplished using a
combination of the 0xA0/0xA1 address pair and a segment pointer. For each value of the
segment pointer, 256 bytes of data are available at the 0xA0/0xA1 address pair. An
unspecified segment pointer references the same data as when the segment pointer is zero.
Each successive value of the segment pointer allows access to the next two blocks of E-
EDID (128 bytes each). The value of the segment pointer register cannot be read since it is
reset at the completion of each command.
Enhanced DDC sink
The sink should be Enhanced DDC read compliant.
The sink should be capable of responding with EDID 1.3 data and up to 255 extension
blocks, each 128 bytes long (up to 32 Kbytes of E-EDID memory) whenever the hot plug
detect (HPD) signal is asserted.
The sink should be capable of providing E-EDID information over the Enhanced DDC
channel whenever the +5 V power signal is provided. The information should be available
within 20 ms after the +5 V power signal is provided.
Enhanced DDC source
The source should use Enhanced DDC protocols.
It should be capable of reading EDID 1.3 data at DDC address 0xA0.
The source reads Enhanced EDID extension data at DDC address 0xA0 using segment
pointer 0x60.
1.4.3 Hot plug detect (HPD) signal
A HDMI sink should not assert high voltage levels on its HPD pin when the E-EDID is not
available for reading. This requirement should be fulfilled at all times, even if the sink is
powered off or in standby. The HPD pin may be asserted only when the +5 V power line
from the source is detected. This ensures that the HPD pin is not asserted before the third
make of the connector.
A source may use a high voltage level HPD signal to initiate the reading of E-EDID data. It
does not indicate whether the sink is powered, or whether the HDMI input on the sink is
selected or active.
A HDMI sink should indicate any change to the contents of the E-EDID by driving a low
voltage level pulse on the HPD pin. This pulse should last at least 100 ms.
1.4.4 Physical address discovery
In order to allow CEC to address specific physical devices, all have a physical address. The
bus connectivity is worked out whenever the hot plug detect (HPD) signal is de-asserted by
the physical address discovery process. That process uses only the DDC/EDID (display
data channel/extended display identification data) mechanism. Starting from the CEC root
device which takes address 0b0000 (normally the TV), all sinks and repeaters, whether
CEC-capable or not, determine the address their source device should take, and make it
available in the source address field of the EDID vendor-specific data block

High-definition multimedia interface, consumer electronics control (HDMI-CEC) AN3127
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(EDID_EXT_VSDB_B0-1). Thereby, except for the root device, all devices have the physical
address stored in the EDID of their connected sink.
The physical address of each node is determined through the physical address discovery
process. This process is dynamic in that it automatically adjusts physical addresses as
required as devices are physically or electrically added or removed from the device tree.
All sinks and repeaters should perform the steps of physical address discovery and
propagation even if those devices are not CEC-capable. Sources are not required to
determine their own physical address unless they are CEC-capable.
All addresses are 4 digits long allowing for a 5-device-deep hierarchy. All are identified in the
form of n.n.n.n in the following description.
A sink or repeater that is acting as the CEC root device generates its own physical address:
0.0.0.0. The source or repeater reads its physical address from the EDID of the connected
sink. The CEC line may be connected to only one HDMI output so a device with multiple
HDMI outputs will read its physical address from the EDID on the CEC-connected output.
Each sink and repeater is responsible for generating the physical address of all source
devices connected to that device by appending a port number onto its own physical address
and placing that value in the EDID for that port.
1.4.5 Discovery algorithm
The following algorithm is used to allocate the physical address of each device whenever
HPD is de-asserted, or upon power-up:
Figure 8. Physical address discovery algorithm
$ISABLEASSERTIONOF (0$TOALLSOURCEDEVICES
)F)AM#%#ROOT
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4HEDEVICESHALL RETAINTHISPHYSICALADDRESSUNTIL
(0$ISREMOVEDORT HEDEVICEISPOWEREDOFF
%NDIF
)FDEVICEHASCONNECT IONSFORSOURCEDEVICESTHEN
,ABELALLPOSSIBLE CONNECTIONSTOSOURCEDEVICES
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AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
Doc ID 16896 Rev 2 13/36
Whenever a new physical address (other than F.F.F.F) is discovered, a CEC device should:
●allocate the logical address (see Section 1.4.7: Logical address allocation)
●report the association between its logical and physical addresses by broadcasting
<Report Physical Address>
This process allows any node to create a map of physical connections to logical addresses.
1.4.6 Logical addressing
Apart from the physical address, each device appearing on the control signal line has a
unique logical address. This address defines a device type as well as being a unique
identifier. This address is 0 for a TV set with physical address 0b0000 and 14 or even 15
otherwise. It is defined in the CEC_OAR register and in the upper nibble of the first byte of
the transmitted message. All CEC devices therefore have both a physical and a logical
address, whereas non-CEC devices only have a physical address.
1.4.7 Logical address allocation
Note that a logical address should only be allocated when a device has a valid physical
address (i.e. not F.F.F.F), at all other times a device should take the ‘Unregistered’ logical
address (15).
Only the device at physical address 0.0.0.0 may take logical address TV (0). A TV at any
other physical address will take the ‘free use’ (14) address. If address 14 is already
allocated it will take the ‘unregistered’ address (15).
Table 1. Logical addresses
Address Device
0TV
1 Recording device 1
2 Recording device 2
3 Tuner 1
4 Playback device 1
5 Audio system
6 Tuner 2
7 Tuner 3
8 Playback device 2
9 Recording device 3
10 Tuner 4
11 Playback device 3
12 Reserved
13 Reserved
14 Free use
15 Unregistered (as initiator address) broadcast (as destination
address)

High-definition multimedia interface, consumer electronics control (HDMI-CEC) AN3127
14/36 Doc ID 16896 Rev 2
Reserved addresses should not be used at present and are reserved for future extensions
to this specification.
Where more than one possible logical address is available for the given device type (e.g.
Tuner 1, Tuner 2, etc.), an address allocation procedure should be carried out by a newly
connected device. The device takes the first allocated address for that device type and
sends a <Polling Message> to the same address (e.g. Tuner 1 -->Tuner 1). If the <Polling
Message> is not acknowledged, then the device stops the procedure and retains that
address.
If the first address is acknowledged, then the device takes the next address for that device
type and repeats the process (e.g. Tuner 2 .. Tuner 2). Again, if the message is not
acknowledged, the device keeps that address.
This procedure continues until all possible ‘type-specific’ addresses have been checked; if
no ‘type-specific’ addresses are available the device should take the unregistered address
(15). Note that several physical devices might be sharing this address.
A device may lose its logical address when it is disconnected or switched off. However, it
may remember its previous logical address, so that the next time it is connected or switched
on, it can begin the polling process at its previous logical address and try each other
allowable logical address in sequence before taking the unregistered address. For example
if an STB that was previously allocated address Tuner 2 is reconnected, it would poll Tuner
2, Tuner 3, Tuner 4 and Tuner 1 before taking the unregistered address.
If a device loses its physical address at any time (e.g. it is unplugged) then its logical
address should be set to unregistered (15).
1.5 STM32F100xx’s HDMI-CEC controller
The STM32F100xx’s HDMI-CEC controller provides a hardware support of the CEC
protocol.

AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
Doc ID 16896 Rev 2 15/36
1.5.1 Main features
●Supports HDMI-CEC v1.3a
●Supports the whole set of features offered with CEC (devices may use all or only some
of these features, depending on functionality):
– One touch play - a device may be played and become the active source by
pressing a single button.
– System standby - enables devices to be set on standby by pressing a single
button.
– Preset transfer - the presets of a device can be autoconfigured to match those of
the TV.
– One touch record - used to make recordings by pressing a single button.
– Timer programming - any device can program a timer to start/stop audio/video
recording.
– System information - allows devices to autoconfigure their language and country
settings.
– Deck control - allows a device to control and interrogate a playback device.
– Tuner control - allows a device to control the tuner of another device.
– Vendor-specific commands - allow vendor-defined commands to be used.
– OSD display - allows a device to display text using the on-screen display of the TV.
– Device menu control - allows a device to control the menu of another device.
– Routing control - enables control of CEC switches for the streaming of a new
source device.

High-definition multimedia interface, consumer electronics control (HDMI-CEC) AN3127
16/36 Doc ID 16896 Rev 2
1.5.2 HDMI-CEC advanced features
The STM32 HDMI-CEC controller provides an easy platform to build CEC firmware
applications:
●dedicated address register containing up to 15 CEC device addresses
●Programmable high-resolution prescaler (14 bit) to obtain a 50 µs time base (HDMI
specification resolution)
●advanced arbitration mechanism using SFT (signal free time) and header arbitration
●dedicated transmission and reception flags (TBTRF and RBTF) with interrupt capability
●error handling in a single dedicated register: bit timing errors, bit period errors,
message errors and error bit generation
– Tx block transfer finished error (TBTFE)
– Line error (LINE)
– Block acknowledge error (ACKE)
– Start bit error (SBE)
– Rx block transfer finished error (RTBFE)
– Bit period error (BPE)
– Bit timing error (BTE)
●error-free mode to allow safe communication with non-tolerant CEC devices. This
mode can be selected using a dedicated configuration bit.
●Rx digital filtering
●CEC controller built around a flexible state machine to ensure safe communication,
switching between the Tx and Rx modes, and easy error handling. There are 6 states:
Disabled, Idle, RX, TX, RX_ERROR and TX_ERROR. Please refer to the reference
manual (RM0041) available from www.st.com for more details.
●Wakeup-from-Stop source, with no data loss: the CEC line can be used as a wakeup
event from the Stop mode. The STM32 Wakeup system is fast enough to ensure that
there is no CEC data loss. CEC data received when the system is in the Stop mode
cause the system to wake up from the low power mode, and in so doing, allow the CEC
peripheral to easily retrieve them.

AN3127 High-definition multimedia interface, consumer electronics control (HDMI-CEC)
Doc ID 16896 Rev 2 17/36
Figure 9. System exits Stop mode when data reception starts
As the tolerance margin on the start bit is 200 µs, the software has to reconfigure the system
clock within this time frame (see Figure 9). The system clock reconfiguration is necessary as
after waking up from the Stop mode the CPU starts running on the high-speed internal
oscillator (HSI 8 MHz).
To ensure that there is no data loss while the system is in the wakeup phase from the Stop
mode, the following procedures can be selected:
●The software can choose to use the system PLL as the system main clock. The PLL
source should be the HSI and not the HSE.
●For applications which do not need the full CPU performance, the software can choose
to receive the first message just after waking up from Stop mode at the HSI frequency.
In this case, there is no need to reconfigure the system clock after the CPU exits the
Stop mode. However, just before entering the Stop mode the CEC prescaler should be
reprogrammed to be in line with the HSI frequency by:
– disabling the CEC peripheral. To do so, write PE=0 and wait until PE goes low
– writing the CEC prescaler register (CEC_PRER = 399)
– enabling the CEC peripheral. This is done by writing PE=1.
– requesting Stop mode entry
Note: 1 The HSE cannot be used after wakeup from Stop mode as it takes some time to start up,
and CEC data would be lost.
2 Any data sent on the CEC bus cause the device to wake up even if the destination address
is not matched.
3 After the first message is received, the software can restore the initial clock configuration to
continue in Run mode or re-enter the Stop mode.
Refer to the STM32F100xx reference manual (RM0041) for further details.
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Hardware environment AN3127
18/36 Doc ID 16896 Rev 2
2 Hardware environment
To be fully compliant with the stringent HDMI 1.3a specification, specially when the CEC
device is in the power-off state, a fully integrated ESD protection should be added externally
to the STM32F100xx device. For that purpose, the HDMI2C1-5DIJ ensures level-shifting
and serves as the signal booster for control links of HDMI 1.3 transmitters. The HDMI2C1-
5DIJ is a bidirectional isolation buffer, integrating hysteresis and signal boosters for
maximum system robustness and signal integrity.
In addition to this circuit, the 27 kΩpull-up resistor on the CEC line should be externally
connected to the STM32F100xx.
With these few hardware additions, the STM32F100xx CEC solution (CEC peripheral plus
ESD protection circuit) is fully compliant with the HDMI 1.3 standard.
The solution is already implemented on Value line evaluation boards. Two HDMI connectors
are available for each Value line evaluation board (CN15, CN16 for STM32100B-EVAL and
CN2, CN3 for STM32100E-EVAL). The CEC, SCL, SDA and HPD signals are supported
and connected to STM32F100xx through HDMI2C1-5DIJ.
The external hardware component is only needed when the CEC power-off state is needed
in the application. If the power-off state is not needed, you can directly connect the
STM32F100xx CEC line to the CEC bus.
2.1 HDMI connector
Only a vendor-approved, HDMI connector should be used. The list of approved HDMI
connectors is available from the HDMI site (www.hdmi.org).
The differential impedance of this connector should be equal to 100 Ω±15%. This can be
checked by using time domain reflectometry (TDR) equipment.
Figure 10. HDMI cable

AN3127 Hardware environment
Doc ID 16896 Rev 2 19/36
2.1.1 I2C bus
The display data channel (DDC) I/Os and wires (SDA, SCL, DDC/CEC Ground), should
meet the requirements specified in the I²C bus specification, version 2.1 (Section 15 for
“Standard-Mode” devices).
Discussions about high-capacitance environments found in the I²C Specification section
(17.2 “Switched pull-up circuit for Fast-mode I²C-bus devices”) also apply to the HDMI
environment.
This section covers the electrical specifications for the I²C (defined by the CTS and by the
I²C bus specification). Timing specifications are not dealt with here. The HDMI standard
specifies that the maximum clock rate is 100 kHz.
The I²C bus is a standard two-wire (SCL for clock and SDA for data) serial databus protocol.
The electrical specifications for I²C bus device I/Os are power-supply-dependent. An I²C bus
device with fixed input levels of 1.5 V and 3 V can have its own supply voltage. A pull-up
resistor has to be connected to a 5 V ±10% supply.
When devices with fixed input levels are mixed with devices with input levels dependent on
VCC, the latter have to be connected to a common 5 V ±10% supply line with pull-up
resistors connected to their SDA and SCL pins.
The ST reference board implemented in this application note has 3.3 V-tolerant I/Os and a
HDMI-compatible I²C bus dependent on a +5 V VCC supply. For the implementation, it is
recommended to use the setup shown in Figure 11, with the HDMI2C1-5DIJ chip.
Table 2. HDMI connector pinout
Pin number Signal name Pin number Signal name
1 TMDS Data 2+ 11 TMDS Clock Shield
2 TMDS Data 2 Shield 12 TMDS Clock-
3 TMDS Data 2- 13 CEC
4 TMDS Data 1+ 14 No Connect
5 TMDS Data 1 Shield 15 DDC Clock
6 TMDS Data 1- 16 DDC Data
7 TMDS Data 0+ 17 Ground
8 TMDS Data 0 Shield 18 +5 V power
9 TMDS Data 0- 19 Hot Plug Detect
10 TMDS Clock+ - -

Hardware environment AN3127
20/36 Doc ID 16896 Rev 2
Figure 11. Application schematic