Toshiba TLCS-900/H1 Series User manual

TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CF30FG
Semiconductor Company

Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Notes and Restrictions”.

TMP92CF30
2009-06-12
92CF30-1
CMOS 32-Bit Microcontroller
TMP92CF30FG
1. Outline and Features
The TMP92CF30 is a high-speed advanced 32-bit microcontroller developed for controlling
equipment which processes mass data.
The TMP92CF30FG is housed in a 176-pin QFP package.
(1) CPU: 32-bit CPU (High-speed 900/H1 CPU)
•Compatible with TLCS-900/L1 instruction code
•16 Mbytes of linear address space
•General-purpose register and register banks
•Micro DMA: 8channels (62.5 ns/4 bytes at fSYS = 80 MHz, best case)
(2) Minimum instruction execution time : 12.5 ns (at fSYS = 80 MHz)
(3) Internal RAM: 144 Kbytes (can be used for program and data)
Internal ROM: None
(4) External memory expansion
•Expandable up to 2.1 Gbytes (shared program/data area)
•Can simultaneously support 8-, 16- and 32-bit width external data buses
…… Dynamic data bus sizing
•Separate bus system
(5) Memory controller
•Chip select output: 4 channels
•One channel in 4 channels is enabled detailed AC enable setting
(6) 8-bit timers: 8 channels
(7) 16-bit timer/event counter: 2 channels
(8) General-purpose serial interface: 2 channels
•UART/synchronous mode: 2 channels
•IrDA ver.1.0 (115.2 kbps) selectable
(9) Serial bus interface: 1 channel
•I2C standard mode only
(10) USB (universal serial bus) controller: 1 channel
•Full-speed (12 Mbps) (Low-speed is not supported.)
•Endpoint 0: Control 64 bytes ×1 FIFO
Endpoint 1: BULK (output) 64 bytes ×2 FIFOs
Endpoint 2: BULK (input) 64 bytes ×2 FIFOs
Endpoint 3: Interrupt (input) 8 bytes ×1 FIFO
•Descriptor RAM: 384 bytes

TMP92CF30
2009-06-12
92CF30-2
(11) I2S (Inter-IC Sound) interface: 1 channel
•I2S bus mode selectable (Master, transmission only)
•Data Format is supported Left/Right Justify
•128-byte FIFO buffer (64 bytes ×2)
(12) SDRAM controller:1 channel
•Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate)
SDRAM
•Possible to execute instruction on SDRAM
(13) Timer for real-time clock (RTC)
•Based on TC8521A
(14) Key-on wakeup (Interrupt key input)
(15) 10-bit A/D converter (Built in Sample Hold circuit): 6 channels
(16) Touch screen interface
•Built-in Switch of Low-resistor, and available to reduce external components for shift
change row/column
(17) Watchdog timer
(18) Melody/alarm generator
•Melody: Output of a clock 4 to 5461-Hz clock
•Alarm: Output of 8 kinds of alarm pattern
•5 kinds of interval interrupt
(19) MMU
•Expandable up to 2.1 Gbytes (3 local area/8 bank method)
•Independent bank for each program, read data, write data, source and destination of
DMAC (Odd channel/Even channel)
(20) Interrupts: 58 interrupts
•9 CPU interrupts: Software interrupt instruction and illegal instruction
•39 internal interrupts: Seven selectable priority levels
•10 external interrupts: Seven selectable priority levels (include key and NMI interrupt)
(8-edge selectable)
(21) DMAC function: 6 channels
•High-speed data transfer enable by controlling which convert micro DMA function and
this function
(22) Input/Output ports: 98 pins (Except Data bus (16bit), Address bus (24bit) and RD pin)
(23) NAND Flash interface: 2 channels
•Direct NAND flash connection capability
•Supports SLC type and MLC type
•Supports Data Bus 8/16 bit, Page Size 512/2048 bytes
•Built-in Reed Solomon calculation circuits which enabled correct 4-address, and detect
error more than 5-address

TMP92CF30
2009-06-12
92CF30-3
(24) SPI controller: 1 channel
•Supports SPI mode of SD card and MMC card
•Built-in FIFO buffer of 32 bytes to each Input/Output
(25) Product/Sum calculation: 1 channel
•Supports calculation 32 ×32 + 64 =64 bits, 64 −32 ×32 =64 bits and 32 ×32 −64 =64 bits
•I/O method
•Supports Signed calculations
(26) Standby function
•Three Halt modes: IDLE2 (programmable), IDLE1, STOP
•Each pin status programmable for standby mode
(27) Clock controller
•Two blocks of clock doubler (PLL) supplies 48 MHz for USB and 80 MHz for CPU from 10
MHz
•Clock gear function: Selectable high-frequency clock fc to fc/16
•Clock for Timer (fs =32.768 kHz)
(28) Operating voltage:
•2 power supplies (Internal power supply (1.4 to 1.6 V), External power supply (3.0 to 3.6 V)
(29) Package
•176-pin LQFP: LQFP176-P-2020-0.40F

TMP92CF30
2009-06-12
92CF30-4
Figure 1.1 Block Diagram of TMP92CF30
(PY)P97
IX
IY
IZ
SP
LH
ED
CB
AW
XSP
XIZ
XIY
XIX
XHL
XDE
XBC
XWA
900/H1 CPU
FSR
32bit
P C
144KB RAM
SERIAL I/O
SIO0
(RXD1,RXD0) P91
(TXD1,TXD0) P90
RESET
AM [1:0]
10-bit 6ch
AD
Converter
VREFH, VREFL
AVCC, AVSS
(AN3, MY, ADTRG)PG3
(AN2, MX)PG2
(AN0 to AN1)PG0 to PG1
8BIT TIMER
(TIMERA0)
8BIT TIMER
(TIMERA1)
(TA1OUT, MLDALM)
8BIT TIMER
(TIMERA2)
8BIT TIMER
(TIMERA3)
16BIT TIMER
(TIMERB0)
WATCH-DOG TIMER
X1
H-OSC X2
Clock gear
Interrupt
Controller
MMU
(TB0OUT0) PP6
XT1
L-OSC XT2
(PX, INT4)P96 Touch screen
I/F
(TSI)
(SDA) PV6
(SCL) PV7
SDRAM
Controller
(SDCLK)PF7
(SDRAS ,SRLLB )PJ0
(SDCAS , SRLUB )PJ1
(SDWE ,SRWR )PJ2
(SDLLDQM)PJ3
(SDLUDQM)PJ4
(SDCKE)PJ7
PORT8
PORT1
PORT6
P10 to P17 (D8 to D15)
PORT7
P70 (RD )
P73 (EA24)
P74 (EA25)
P75(R/ W, NDR/B)
P76 ( WAIT )
RTC
MELODY/
ALARM-OUT
KEY-BOARD
I/F
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
PM2 ( ALARM ,MLDALM )
PLL
NAND-FLASH
I/F (2ch)
SBI (I2Cbus)
SPI
Controller
(SPDO) PR1
(SPDI) PR0
(SPCLK) PR3
(SPCS ) PR2
I2S
(I2S0)
(I2S0DO) PF1
(I2S0CKO) PF0
(I2S0WS) PF2
(TA0IN, INT1) PC1
D+
D - USB
Controller
(
X1D4, X1USB
)
PX5
PC0 (INT0)
PC2 (INT2)
P71 ( WRLL ,NDRE )
P72 ( WRLU ,NDWE )
P86 (CSZD ,CE0ND )
P87 (CSXB, CE1ND )
PJ5 (NDALE, SRULB )
PJ6 (NDCLE, SRUUB )
PORTM PM7
DVCC3A [8]
DVCC1C [1]
DVSS1C [1]
MAC
DMAC PORT5
PORT4
P60 to P67 (A16 to A23)
P50 to P57 (A8 to A15)
P40 to P47 (A0 to A7)
PL0 to PL7 (D16 to D23)
PT0 to PT7 (D24 to D31)
PORTL
PORTT
NMI
PORTC PC4 (EA26, SPDI)
PC5 (EA27, SPDO)
PC6 (EA28, SPCLK)
16BIT TIMER
(TIMERB1)
8BIT TIMER
(TIMERA4)
8BIT TIMER
(TIMERA5)
8BIT TIMER
(TIMERA6)
8BIT TIMER
(TIMERA7)
(TA2IN, INT3) PC3
PP5
P80 ( 0CS )
P81 ( 1CS ,SDCS )
P82 ( 2CS ,CSZA ,SDCS )
P83 ( 3CS ,CSXA )
(
AN4, AN5
)
PG4 to PG5
PORTK PK0 to PK7
DVCC1A [4]
DVCC1B [1]
DVSSCOM [8]
D0 to D7
(TA7OUT, INT5, TXD1, TXD0) PP3
(TB0IN0, INT6, RXD1, RXD0) PP4

TMP92CF30
2009-06-12
92CF30-5
TMP92CF30FG
QFP176
Top View
PX5, X1USB, X1D4
AM1
PX4, CLKOUT
DVCC1C
X2
DVSS1C
X1
DVCC1A2
PP6, TB0OUT0
PP5, INT7, TB1IN0, SCLK1/0, CTS1/0
PP4, INT6, TB0IN0, RXD1, RXD0
PP3, INT5, TA7OUT, TXD1, TXD0
DVCC3A3
DVSSCOM3
PT7, D31 PT6, D30 PT5, D29 PT4, D28 PT3, D27 PT2, D26 PT1, D25 PT0, D24
PL7, D23 PL6, D22 PL5, D21 PL4, D20 PL3, D19 PL2, D18 PL1, D17 PL0, D16
DVCC3A4
DVSSCOM4
P17, D15 P16, D14 P15, D13 P14, D12 P13, D11 P12, D10
P11, D9 P10, D8
D7 D6 D5 D4
PG5, AN5 PG4, AN4 PG3, AN3, MY, ADTRG PG2, AN2, MX PG1,AN1 PG0,AN0 DVSSCOM8 DVCC3A8
P92, SCLK1,SCLK0,CTS1,CTS0 P91, RXD1, RXD0 P90, TXD1, TXD0 PM2, ALARM, MLDALM PM1, TA1OUT, MLDALM PV7, SCL PV6, SD
A
PF2, I2S0WS PF1, I2S0DO PF0, I2S0CKO DVCC1A4 PF7, SDCLK NMI PJ7, SDCKE PJ6, NDCLE, SRUUB PJ5, NDALE, SRULB PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR PJ1, SDCAS, SRLUB PJ0, SDRAS, SRLLB DVSSCOM7 D- D+ DVCC3A7 P87, CSXB, ND1CE P86, CSZD, ND0CE P83, CS3, CSXA P82, CS2, CSZ
A
, SDCS
P81, CS1, SDCS P80, CS0 P76, WAIT P75, R/W, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE
45
50
55
60
65
70
75
80
85
130
125
120
115
110
105
100
95
90
175 170 165 160 155 150 145 140 135
1 5 10 15 20 25 30 35
40
2. Pin Assignment and Pin Functions
The assignment of input/output pins for TMP92CF30, their names and functions are as follows;
2.1 Pin Assignment Diagram (Top View)
Figure 2.1.1 shows the pin assignment of the TMP92CF30.
Figure 2.1.1 Pin assignment diagram (P-FBGA228)
P71, WRLL , NDRE
P70, RD
PC6, EA28, SPCLK
PC5, EA27, SPDO
PC4, EA26, SPDI
PC3, INT3, TA2IN
PC2, INT2
PC1, INT1, TA0IN
PC0, INT0
DVSSCOM6
XT1
XT2
DVCC3A6
P67, A23
P66, A22
P65, A21
P64, A20
P63, A19
P62, A18
P61, A17
P60, A16
P57, A15
P56, A14
P55, A13
P54, A12
P53, A11
P52, A10
P51, A9
P50, A8
P47, A7
P46, A6
P45, A5
DVCC1A3
DVSSCOM5
DVCC3A5
P44, A4
P43, A3
P42, A2
P41, A1
P40, A0
D0
D1
D2
D3
VREFH
VREFL
AVCC
AVSS
P97, PY
P96, PX, INT4
PR0, SPDI
PR1, SPDO
PR2, SPCS
PR3, SPCLK
DVCC3A1
DVSSCOM1
DVCC1B
PM7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
DVCC1A1
PC7, KO8
PN7, KO7
PN6, KO6
PN5, KO5
PN4, KO4
PN3, KO3
PN2, KO2
PN1, KO1
PN0, KO0
PA0, KI0
PA1, KI1
PA2, KI2
PA3, KI3
PA4, KI4
PA5, KI5
PA6, KI6
PA7, KI7
DVCC3A2
DVSSCOM2
AM0
RESET

TMP92CF30
2009-06-12
92CF30-6
2.2 Pin names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions (1/6)
Pin name Number
of Pins I/O Functions
D0 to D7 8 I/O Data: Data bus D0 to D7
P10 to P17
D8 to D15 8 I/O I/O Port 1: I/O port input or output specifiable in units of bits Data: Data bus D8 to D15
P40 to P47
A0 to A7 8 Output Output Port 4: Output port Address: Address bus A0 to A7
P50 to P57
A8 to A15 8 Output Output Port 5: Output port Address: Address bus A8 to A15
P60 to P67
A16 to A23 8 I/O Output Port 6: I/O port input or output specifiable in units of bits Address: Address bus A16 to A23
P70
RD 1 Output
Output Port 70: Output port Read: Outputs strobe signal to read external memory
P71
WRLL
NDRE
1 I/O
Output
Output
Port 71: Output port
Write: Outputs strobe signal for writing data on pins D0 to D7
NAND Flash read: Outputs strobe signal to read external NAND-Flash
P72
WRLU
NDWE
1 I/O
Output
Output
Port 72: I/O port
Write: Outputs strobe signal for writing data on pins D8 to D15
NAND Flash write: Write enable for NAND Flash
P73
EA24 1 I/O Output Port 73: I/O port Expanded address 24
P74
EA25 1 I/O Output Port 74: I/O port Expanded address 25
P75
R/ W
NDR/B
1 I/O
Output
Input
Port 75: I/O port
Read/Write: “High” represents read or dummy cycle; “Low” represents write cycle
NAND Flash Ready(1) / Busy(0) input
P76
WAIT 1 I/O
Input Port 76: I/O port Wait: Signal used to request CPU bus wait
P80
0CS 1 Output
Output Port 80: Output port Chip select 0: Outputs “Low” when address is within specified address area
P81
1CS
SDCS
1 Output
Output
Output
Port 81: Output port
Chip select 1: Outputs “Low” when address is within specified address area
Chip select for SDRAM: Outputs “Low” when the address is within SDRAM address area
P82
2CS
CSZA
SDCS
1 Output
Output
Output
Output
Port 82: Output port
Chip select 2: Outputs “Low” when address is within specified address area
Expanded address ZA: Outputs “Low” when address is within specified address area
Chip select for SDRAM: Outputs “Low” when the address is within SDRAM address area
P83
3CS
CSXA
1 Output
Output
Output
Port 83: Output port
Chip select 3: Outputs “Low” when address is within specified address area
Expanded address XA: Outputs “Low” when address is within specified address area

TMP92CF30
2009-06-12
92CF30-7
Table 2.2.1 Pin names and functions (2/6)
Pin name Number
of Pins I/O Functions
P86
CSZD
CE0ND 1 Output
Output
Output
Port 86: Output port
Expanded address ZD: Outputs “Low” when address is within specified address area
Chip select for NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable
P87
CSXB
CE1ND 1 Output
Output
Output
Port 87: Output port
Expanded address XB: Outputs “Low” when address is within specified address area
Chip select for NAND Flash 1: Outputs “Low” when NAND Flash 1 is enable
P90
TXD0
TXD1 1 I/O
Output
Output
Port 90: I/O port
Transmit data for serial 0: programmable Open-drain output
Transmit data for serial 1: programmable Open-drain output
P91
RXD0
RXD1 1 I/O
Input
Input
Port 91: I/O port (Schmitt-input)
Receive data for serial 0
Receive data for serial 1
P92
SCLK0
0CTS
SCLK0
0CTS
1
I/O
I/O
Input
I/O
Input
Port 92: I/O port (Schmitt-input)
Clock I/O for serial 0
Enable to send data for serial 0 (Clear to send)
Clock I/O for serial 1
Enable to send data for serial 1 (Clear to send)
P96
INT4
PX
1 Input
Input
Output
Port 96: Input port (schmitt-input, with pull-up resistor)
Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge
X-Plus: Pin connected to X+pin for Touch Screen I/F
P97
PY 1 Input Output Port 97: Input port (schmitt input) Y-Plus: Pin connected to Y+pin for Touch Screen I/F
PA0 to PA7
KI0 to KI7 8 Input Input Port A0 to A7: Input port Key input 0 to 7: Pin used for key on wake-up 0 to 7 (Schmitt-input, with pull-up resistor)
PC0
INT0 1 I/O Input Port C0: I/O port (Schmitt-input) Interrupt request pin 0: Interrupt request pin with programmable rising/falling edge
PC1
INT1
TA0IN 1 I/O
Input
Input
Port C1: I/O port (Schmitt-input)
Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge
Timer A0 input: Input pin for 8 bit timer 0
PC2
INT2 1 I/O Input Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge
PC3
INT3
TA2IN 1 I/O
Input
Input
Port C3: I/O port (Schmitt-input)
Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge
Timer A2 input: Input pin for 8 bit timer 2
PC4
EA26
SPDI 1 I/O
Output
Input
Port C4: I/O port
Expanded address 26
Data input pin for SD card
PC5
EA27
SPDO 1 I/O
Output
Output
Port C5: I/O port
Expanded address 27
Data output pin for SD card
PC6
EA28
SPCLK 1 I/O
Output
Output
Port C6: I/O port
Expanded address 28
Clock output pin for SD card
PC7
KO8 1 I/O Output Port C7: I/O port Key output 8: Key scan strobe pin (programmable Open-drain output)

TMP92CF30
2009-06-12
92CF30-8
Table 2.2.1 Pin names and functions (3/6)
Pin name Number
of Pins I/O Functions
PF0
I2S0CKO 1 I/O Output Port F0: I/O port Outputs clock for I2S0
PF1
I2S0DO 1 I/O Output Port F1: I/O port Outputs data for I2S0
PF2
I2S0WS 1 I/O Output Port F2: I/O port Outputs word select signal for I2S0
PF7
SDCLK 1 Output Output Port F7: Output port Clock for SDRAM
PG0 to PG1
AN0 to AN1 2 Input Input Port G0 to G1: Input port Analog input pin 0 to 1: Input pin for AD converter
PG2
AN2
MX 1 Input
Input
Output
Port G2: Input port
Analog input pin 2: Input pin for AD converter
X-Minus: Pin connected to X- pin for Touch Screen I/F
PG3
AN3
MY
ADTRG
1
Input
Input
Output
Input
Port G3: Input port
Analog input pin 3: Input pin for A/D converter
Y-Minus: Pin connected to Y- pin for Touch Screen I/F
A/D Trigger: Request signal for A/D start
PG4 to PG5
AN4 to AN5 2 Input Input Port G4 to G5: Input port Analog input pin 4 to 5: Input pin for A/D converter
PJ0
SDRAS
SRLLB 1 Output
Output
Output
Port J0: Output port
Outputs strobe signal for SDRAM row address
Data enable signal for D0 to D7 for SRAM
PJ1
SDCAS
SRLUB 1 Output
Output
Output
Port J1: Output port
Outputs strobe signal for SDRAM column address
Data enable signal for D8 to D15 for SRAM
PJ2
SDWE
SRWR 1 Output
Output
Output
Port J2: Output port
Outputs write enable signal for SDRAM
Write enable for SRAM: Outputs strobe signal to write data
PJ3
SDLLDQM 1 Output Output Port J3: Output port Data enable signal for D0 to D7 for SDRAM
PJ4
SDLUDQM 1 Output Output Port J4: Output port Data enable signal for D8 to D15 for SDRAM
PJ5
NDALE
SDULB 1 I/O
Output
Output
Port J5: I/O port
Address latch enable signal for NAND Flash
Data enable signal for D16 to D23 for SDRAM
PJ6
NDCLE
SDUUB 1 I/O
Output
Output
Port J6: I/O port
Command latch enable signal for NAND Flash
Data enable signal for D24 to D31 for SDRAM
PJ7
SDCKE 1 Output Output Port J7: Output port Clock enable signal for SDRAM

TMP92CF30
2009-06-12
92CF30-9
Table 2.2.1 Pin names and functions (4/6)
Pin name Number
of Pins I/O Functions
PK0 to PK7 8 Output Port K0 to PK7: Output port
PL0 to PL7
D16 to D23 8 I/O Output Port L0 to L7: I/O port Data bus D16 to D23
PM1
TA1OUT
MLDALM 1 Output
Output
Output
Port M1: Output port
Timer A1 output: Output pin for 8 bit timer 1
Melody / Alarm output pin
PM2
ALARM
MLDALM 1 Output
Output
Output
Port M2: Output port
Alarm output from RTC
Melody / Alarm output pin (inverted)
PM7 1 Output Port M7: Output port
PN0 to PN7
KO0 to KO7 8 I/O Output Port N: I/O port Key output 0 to 7: Key scan strobe pin (programmable Open-drain output)
PP3
INT5
TA7OUT
TXD0
TXD1
1
I/O
Input
Output
Output
Output
Port P3: I/O port (Schmitt-input)
Interrupt request pin 5: Interrupt request pin with programmable rising/falling edge
Timer A7 output: Output pin for 8 bit timer 7
Transmit data for serial 0: programmable Open-drain output
Transmit data for serial 1: programmable Open-drain output
PP4
INT6
TB0IN0
RXD0
RXD1
1
I/O
Input
Input
Input
Input
Port P4: I/O port (Schmitt-input)
Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge
Timer B0 input: Input pin for 16 bit timer 0
Receive data for serial 0
Receive data for serial 1
PP5
INT7
TB1IN0
SCLK0
0CTS
SCLK1
1CTS
1
I/O
Input
Input
I/O
Input
I/O
Input
Port P5: I/O port (Schmitt-input)
Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge
Timer B1 input: Input pin for 16 bit timer 1
Clock I/O for serial 0
Enable to send data for serial 0 (Clear to send)
Clock I/O for serial 1
Enable to send data for serial 1 (Clear to send)
PP6
TB0OUT0 1 Output Output Port P6: I/O port Timer B0 output: Output pin for 16 bit timer 0

TMP92CF30
2009-06-12
92CF30-10
Table 2.2.1 Pin names and functions (5/6)
Pin name Number
of Pins I/O Functions
PR0
SPDI 1 I/O Input Port R0: I/O port Data input pin for SD card
PR1
SPDO 1 I/O Output Port R1: I/O port Data output pin for SD card
PR2
SPCS 1 I/O
Output Port R2: I/O port Chip select signal for SD card
PR3
SPCLK 1 I/O Output Port R3: I/O port Clock output pin for SD card
PT0 to PT7
D24 to D31 8 I/O I/O Port T0 to T7: I/O port Data: Data bus D24 to D31
PV6
SDA 1 I/O I/O Port V6: I/O port Send/receive data at I2C mode
PV7
SCL 1 I/O I/O Port V7: I/O port Input/output clock at I2C mode
PX4
CLKOUT 1 Output Output Port X4: Output port Internal clock output pin
PX5
X1USB
X1D4 1 I/O
Input
Output
Port X5: I/O port
Clock input pin for USB
Direct clock output pin

TMP92CF30
2009-06-12
92CF30-11
Table 2.2.1 Pin names and functions (6/6)
Pin name Number
of Pins I/O Functions
D+, D−2 I/O
USB-data connecting pin
Connect pull-up(DVCC3A) or pull-down resistor to both pins to avoid through current when
USB is not in use.
NMI 1 Input Non-maskable interrupt pin.
AM1, AM0 2 Input
Operation mode;
Fix to AM1 =“0”,AM0 =“1” for 16 bit external bus starting
Fix to AM1 =“1”,AM0 =“0” for 32 bit external bus starting
Fix to AM1 =“1”,AM0 =“1” is prohibited to set
Fix to AM1 =“0”,AM0 =“0” is prohibited to set
X1/X2 2 I/O High-frequency oscillator circuit connection pin
XT1/XT2 2 I/O Low-frequency oscillator circuit connection pin
RESET 1 Input Reset: Initialize TMP92CF30 (Schmitt-input , with pull-up resistor)
VREFH 1 Input Pin for reference voltage input to AD converter(H)
VREFL 1 Input Pin for reference voltage input to AD converter(L)
AVCC 1
−Power supply pin for AD converter
AVSS 1
−GND pin for AD converter (0V)
DVCC3A 8
−Power supply pin for peripheral I/O-A (All DVCC3A pins should be connected to the power
supply pin )
DVCC1A 4
−Power supply pin for internal logic-A (All DVCC1A pins should be connected to the power
supply pin )
DVCC1B 1
−Power supply pin for internal logic-B (Keep the voltage DVCC1A level )
DVSSCOM 8 −GND pin (0V) (All DVSS pins should be connected to GND(0V))
DVCC1C 1
−Power supply pin for High speed oscillator (Keep the voltage DVCC1A level )
DVSS1C 1
−GND pin (0V) (DVSS1C pin should be connected to GND(0V))
Table 2.2.2 shows the range of operational voltage for power supply pins.
Table 2.2.2 the range of operational voltage for power supply pins
Power supply pin Range of operational
voltage
DVCC1A
DVCC1B
DVCC1C
1.4V~1.6V
DVCC3A
AVCC 3.0V~3.6V

TMP92CF30
2009-06-12
92CF30-12
3. Operation
This section describes the basic components, functions and operation of the TMP92CF30.
3.1 CPU
The TMP92CF30 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU)
3.1.1 CPU Outline
The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the
TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to
process Instructions more quickly.
The following is an outline of the CPU:
Table 3.1.1Outline of TMP92CF30
Parameter TMP92CF30
Width of CPU Address Bus 24-bit
Width of CPU Data Bus 32-bit
Internal Operating Frequency Max 80 MHz
Minimum Bus Cycle 1-clock access (12.5ns at 80 MHz)
Internal RAM 32-bit 2-1-1-1 clock access
8-bit,
2-clock access INTC,SDRAMC,
MEMC,TSI,PORT
16-bit,
2-clock access MMU,USB, NDFC,SPIC,DMAC
32-bit,
2-clock access I2S
32-bit,
1-clock access MAC
Internal I/O
8-bit,
5 to 6-clock access TMRA,TMRB, SIO,RTC,
MLD/ALM, SBI
CGEAR,ADC,WDT
External memory
(SRAM, MASKROM etc.) 8/16-bit 2-clock access (waits can be inserted)
External memory
(SDRAM) 16-bit 1-clock access
External memory
(NAND FLASH) 8/16-bit 2-clock access (waits can be inserted)
Minimum Instruction
Execution Cycle 1-clock (12.5ns at 80 MHz)
Conditional Jump 2-clock (25.0ns at 80 MHz)
Instruction Queue Buffer 12-byte
Instruction Set Compatible with TLCS-900/L1
(LDX instruction is deleted)
Micro DMA 8-channel
Hardware DMA 6-channel

TMP92CF30
2009-06-12
92CF30-13
3.1.2 Reset Operation
When resetting the TMP92CF30 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at
X1=10MHz).
At reset, since the clock doublers (PLL0) is bypassed and the clock-gear is set to 1/16, the
system clock operates at 625 kHz(X1=10MHz).
When the Reset has been accepted, the CPU performs the following. CPU internal
registers do not change when the Reset is released.
•Sets the Stack Pointer (XSP) to 00000000H.
•Sets bits <IFF2:0> of the Status Register (SR) to “111” (thereby setting the Interrupt Level
Mask Register to level 7).
•Clears bits <RFP1:0> of the Status Register to “00” (thereby selecting Register Bank 0).
When the Reset is released, the CPU starts executing instructions according to the
Program Counter settings.
•Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored at
address FFFF00H~FFFF02H:
PC<7:0> ←data in location FFFF00H
PC<15:8> ←data in location FFFF01H
PC<23:16> ←data in location FFFF02H
When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•Initializes the internal I/O registers as table of “Special Function Register” in Section 5.
Figure 3.1.1 shows reset timing chart. Figure 3.1.2 shows the example of order of
supplying power and the timing of releasing reset.
Note: This LSI builds in RAM internally. However, the data in internal RAM may not be held by Reset operation. After
reset, initialize the data in internal RAM.

TMP92CF30
2009-06-12
92CF30-14
Figure 3.1.1 TMP92CF30 Reset timing chart
Read Write
fSYS
A23∼A0
DATA-IN
D0∼D31
D0∼D31
Sampling
(After reset is released, it is started from 1 wait read cycle)
: High-Z
Sampling
RESET
RD
WRxx SRWR
0FFFF00H
DATA-IN
DATA-OUT
CS0,1, 3
CS2
SRxxB
SRxxB
fSYS×(15.5∼16.5) Clock
Note: This is a timing chart of the 32 bit external bus start mode

TMP92CF30
2009-06-12
92CF30-15
This LSI has the restriction for the order of supplying power. Be sure to supply external
3.3V power with 1.5V power is supplied.
Note1: Although it is possible to turn on or off the 1.5-V and 3.3-V power supply rails simultaneously, it may cause
external pins to temporarily become unstable. Therefore, if there is any possibility that this would affect
peripheral devices connected with the TMP92CF30, external power supplies should be turned on or off while
the internal power supplies are stable, as indicated by the heavy lines in the diagram above.
Note2: In the power-on sequence, the 3.3-V power supply rails must not be turned on before the ones of 1.5-V . In the
power -off sequence, the 3.3-V power supply rails must not be turned off after the ones of 1.5-V.
Figure 3.1.2 Power on Reset Timing Example
1.5V
Power
DVCC1A
DVCC1B
DVCC1C
RESET
AVCC
DVCC3A
Power should rise and
stabilizes within 100 ms. 3.3-V rails should be
turned off first, followed by
the 1.5-V rails.
1.5-V rails should be
turned on first,
followed by the 3.3-V
rails.
Power should fall and
stabilizes within 100 ms.
High-frequency Oscillation Stabilizing Time
＋20 system clock cycles
3.3V
Power
When Powering on When Powering off

TMP92CF30
2009-06-12
92CF30-16
3.1.3 Setting of AM0 and AM1
Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage.
Table 3.1.2 Operation Mode Setup Table
Mode Setup input pin
RESET AM1 AM0 Operation Mode
0 1 16-bit external bus starting
1 0 32-bit external bus starting
1 1 Test mode (Prohibit to set)
0 0 Test mode (Prohibit to set)

TMP92CF30
2009-06-12
92CF30-17
Provisional Emulator Control Area
(64Kbyte)
3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP92CF30.
Figure 3.2.1 Memory Map
Note1: If using an emulator, an optional 64 Kbytes of the 16M bytes area is used for emulator control. Therefore, if
using an emulator, this area cannot be used.
Note2: Do not use the 144K byte area (022000H to 045FFFH) and the last 16-byte area (FFFFF0H to FFFFFFH).
This area is reserved as internal area.
000000H
002000H
16Mbyte area
(R)
(
−R)
(R+)
(R
+R8/16)
(R
+d8/16)
(nnn)
Direct area(n)
64Kbyte area
(nn)
Internal I/O
(8 Kbyte)
04A000H
010000H
( =Internal area)
FFFF00H
FFFFFFH Vector table
(
256 B
y
te
)
000100H
External memory
F00000H
F10000H
(Note2)
046000H (Internal Back Up RAM 16Kbyte)
001FF0H
021FFFH Don’t access area (Note2)
External memory
Internal RAM
(128 Kbyte)
(Note1)

TMP92CF30
2009-06-12
92CF30-18
3.3 Differences between the TMP92CZ26A/CF26A and the TMP92CF30
The TMP92CF30 is a lower pin-count version of the TMP92CF26A with fewer functions
(there are some added functions).
Sections 3.3.1 through 3.3.13 describe the functions that are deleted or newly added to the
TMP29CF30. There are no major differences in AC/DC characteristics. For details, refer to the
chapter “Electrical Characteristics”.
3.3.1 DSU Circuit Deleted
The TMP92CF30 does not support the DSU function, which is available in the
TMP92CZ26A/CF26A.
The development environment is offered with the TMP92CF26AXBG. (The DSU function
is used and a pin conversion is required.) Therefore, functions that are modified or newly
added to the TMP92CF30 cannot be debugged with development tools. (Please use the
actual device or a ROM emulator to debug the TMP92CF30.)
3.3.2 Internal I/O Functions Deleted and Modified
[Deleted function]
The TMP92CF30 has only one I2S channel (Channel 0), whereas the
TMP92CZ26A/CF26A has Channels 0 and 1. When using the TMP92CF30, therefore,
do not access the addresses where special-function registers for this deleted function
have been mapped. For details, see the Table of Special Function Registers (SFRs).
[Modified function 1]
The SIO channel (SIO1) is newly added to the TMP92CF30 with its control registers.
For details, see Table 3.3.1.
[Modified function 2]
There are some modifications to the port control method (multiplexed pin settings)
and associated registers. If an ICE using the TMP92CF26A is used for development
and debugging modified and added registers cannot be debugged. For details, see Table
3.3.1.