Sys Tec Electronic ECUcore-1021 User manual

SYS TEC electronic GmbH
L-1589e-04 Hardware Manual ECUcore-1021
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ECUcore-1021
Hardware Manual
Document Revision: L-1589e-04
Disclaimer:
All data, information and technical specifications contained in this document has been subjected to a
thorough examination. The information in the document is current at the time of publication as long as
nothing else is explicitly stated. However no liability is given for the correctness, completeness and
topicality of the contents.

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Revision History
Version
Date
Changes
01
17.09.2014
Created (Module revision 4377.0)
02
17.03.2015
Changes to module revision 4377.1 added:
- Pin connector: Signal IFC_AD15 and FTM2_EXTCLK can be supported
now (optional order number) (sec. 2.4.2)
- USB3.0: AC coupling capacitors are supported on-board (sec. 3.5)
- SDC: Feature set of SDC corrected. (sec. 3.12)
- DSM: This feature is prepared for future use, but not supported in the latest
version. (sec. 3.13)
03
11.03.2016
- Block diagram changed
- Freescale changed to NXP
- sec. 4 (Application Carrier Board) added
04
23.01.2017
Alternate pin names of IFC interface are added to Table 5 and Table 6.

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List of Abbreviations
ADC Analog digital converter
AI Analog Input
AO Analog Output
BSP Board Support Package
CAN Controller Area Network (according to ISO 11898-1:2003 and ISO 11898-2:2003)
CPU Central Processing Unit
DSM Deep Sleep Mode
EEPROM Electrically Erasable Programmable Read-Only Memory
eMMC embedded Multimedia card
EN European Norm
ETH Ethernet
FB Function Block
GB Giga Byte (1024 x 1MB)
Gb Giga bit
GbE Gigabit Ethernet
GND Ground Reference potential
GPIO General Purpose Input Output
HW Hardware
IEC International Electro technical Commission
I/O Input/Output
I2C Inter-integrated circuit
I2S Integrated Interchip Sound
kB Kilo Byte (1024 byte)
MAC Media Access Controller (e.g. Ethernet controller)
MB Mega Byte (1024 x 1kB)
MDI Media Dependent Interface
nc not connected
OS Operating System
PCB Printed Circuit Board
PDO Process Data Object
PMIC Power Management Integrated Circuit
PLC Programmable Logical Controller
PWM Pulse Width Modulation
RAM Random-Access Memory
RGMII Reduced Gigabit Media-Independent Interface
ROM Read-Only Memory
RTC Real Time Clock
RX Receive
SAI Synchronous Audio Interface
SD Secure Digital
SDC System Diagnostics Controller
sec Seconds
SGMII Serial Gigabit Media-Independent Interface
SIO Serial Input Output
SIL Safety integrity level
SPI Serial Peripheral Interface
SW Software
tbd to be defined
TX Transmit
UART Universal Asynchronous Receiver Transmitter

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Contents
List of Abbreviations............................................................................................................................. 3
List of Tables ......................................................................................................................................... 4
List of Figures........................................................................................................................................ 5
Reference documents........................................................................................................................... 6
1Introduction .................................................................................................................................... 7
2Product Description....................................................................................................................... 8
2.1 Orderable parts ........................................................................................................................ 8
2.2 Technical Data ......................................................................................................................... 9
2.3 Block Diagram........................................................................................................................ 12
2.4 Module connector and pin assignment.................................................................................. 14
2.4.1 Connector type for the Carrier board................................................................................ 14
2.4.2 Pin assignment row A and row B...................................................................................... 14
2.5 Mechanical Dimensions and Heat spreader.......................................................................... 21
3Design-in Considerations............................................................................................................ 23
3.1 Power Supply Design considerations .................................................................................... 23
3.2 Power-on RESET and RESET Configurations ...................................................................... 23
3.3 Manual RESET (/MR) ............................................................................................................ 23
3.4 System Booting...................................................................................................................... 23
3.5 General interface design consideration ................................................................................. 23
3.6 PCI Express ........................................................................................................................... 25
3.7 SGMII..................................................................................................................................... 25
3.8 SGMII/SATA........................................................................................................................... 25
3.9 ETHERNET Interface considerations .................................................................................... 25
3.10 I2C Interface considerations .................................................................................................. 25
3.11 Temperature sensor............................................................................................................... 26
3.12 System Diagnostics Controller (SDC, optional)..................................................................... 26
3.12.1 Window-Watchdog timer................................................................................................... 26
3.12.2 Real Time Clock (RTC)..................................................................................................... 26
3.13 Deep sleep mode considerations........................................................................................... 26
3.14 Thermal Design considerations ............................................................................................. 27
4Application Carrier Board (optional).......................................................................................... 28
5Release and Comments............................................................................................................... 30
List of Tables
Table 1: Orderable parts............................................................................................................................... 8
Table 2: Technical data .............................................................................................................................. 11
Table 3: Overview to primary and alternative signal functions of LS1021A signal groups ........................ 13
Table 4: Carrier board plug-in connector.................................................................................................... 14
Table 5: Connector pin assignment (row A)............................................................................................... 17
Table 6: Connector pin assignment (row B)............................................................................................... 20
Table 7: Mechanical mounting material...................................................................................................... 22
Table 8: Overview of configured on-board power rails............................................................................... 23
Table 9: High-speed interface trace lengths............................................................................................... 24
Table 10: I2C line pull-up resistors............................................................................................................. 26
Table 11: I2C device addresses and bit rates............................................................................................ 26

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List of Figures
Figure 1: Block diagram ECUcore-1021..................................................................................................... 12
Figure 2: Module dimension and location of Module connector on Carrier Board..................................... 21
Figure 3: Carrier board plug-in connector physical dimension................................................................... 22
Figure 4: Mounting example of Module, Carrier Board and heat spreader................................................ 22
Figure 5: Heat spreader with mounted heat sink (dimension and details)................................................. 27
Figure 6: Heat spreader with mounted heat sink (example) ...................................................................... 27
Figure 7: Block diagram ECUcore-1021 with Application Carrier Board.................................................... 28

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Reference documents
/1/ NXP: LS1021A Reference Manual
/2/ NXP: LS1021A Data Sheet
/3/ PCIMG: COMExpress Carrier Design Guide Rev.2.0

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1 Introduction
The ECUcore-1021 is a System On Module (SOM) based on NXP QorIQTM LS1021A. The LS1021A
offers a high density of communication and I/O interfaces combined on a single chip. This enables the
customer to configure the chip and define the arrangement of the interfaces on the connector
independently. This flexibility enables to use the ECUcore-1021 in a wide variety of application scenarios;
from simple HMI to a complex network device.
Compared to similar CPUs, the used processor provides high performance at comparatively lower power
dissipation. It can usually be used at higher temperatures in industrial environment without active cooling.
This not only reduces the needed board space and makes the module very compact, but also is cost-
effective.
The error-correcting code can be integrated as placement-option in series production, so the automatic
error detection and correction is done by hardware.
To further increase the reliability of the module, there is the following diagnosis functions integrated:
RTC (real-time clock)
Temperature Monitoring
Firmware Protection (optional)
1x ADC (optional)
Independent Window Watchdog (optional)

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2 Product Description
2.1 Orderable parts
Part number
Product name
Feature
Notes
4001046
ECUcore-1021 (1GB)
LS1021A, 1GB DDR3L, 128MB Flash, -
40/+85°C
GPCM8/GASIC8
Support only
tbd
ECUcore-1021 (1GB)
LS1021A, 1GB DDR3L, 128MB Flash, -
40/+85°C with support for GPCM with 16bit
multiplexed address/data bus Interface
SPI1 controller
is not available.
Table 1: Orderable parts
Options: Additional ECC-RAM and/or support for Profibus baud rate of 12MBaud on request.

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2.2 Technical Data
CPU core
Processor
NXP QorIQ LS1021A
- Dual-core Cortex-A7 (ARM® Cortex®-A7 MPCore
compliant with ARMv7-A™ architecture)
Each core includes:
–32 Kbyte L1 Instruction Cache (ECC protection)
–32 Kbyte L1 Data Cache (ECC protection)
–NEON co-processor
–Floating Point (FPU)
–QorIQ Trust Architecture and ARM TrustZone®
For both cores:
–512 Kbyte unified I/D L2 Cache (ECC protection)
CPU Clock
1GHz each Core
Main memory
DDR3L-1600MT, 32bit + ECC (optional)
1GB (Optional 2GB)
Boot memory
Quad-SPI NOR-Flash
2x64MB
Mass storage
SATA
1x SATA3.0 controller
SD-Card
1x interface for SDHC/MMC/eMMC
Connectivity
Ethernet
Up to 3x GbE Ethernet (1x on-board GbE-Phy, up to
2x SGMII, 1x RGMII)
On-board Phy Feature:
- 10/100BASE-TX, 1000BASE-T
- Auto-MDI/MDI-X
- Auto-Negotiation
- Digital Loopback and Analog Remote Loopback
mode
- LinkMD Cable diagnostics
PCI Express
2x PCI Express Gen2 controllers
USB-Host
1x USB3.0 controller with integrated Phy

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UART
Up to 2x DUART, up to 6x LPUART
CAN
Up to 4x FlexCAN modules
I2C
Up to 2x I2C controllers
SPI
Up to 2x SPI interfaces, 1 QSPI interface
Display
24-bit RGB, 12bit DDR pin interface
AUDIO
Up to 4 synchronous audio interfaces (I2S/SAI)
1 SPDIF
Temperature sensor
Measurement of CPU junction temperature
Measurement of board ambient temperature
Measurement range: -55°C … +150°C
Misc. peripherals
FlexTimer/PWM
GPIOs
Interrupt inputs
Real Time Clock (RTC)
Current consumption (sleep mode)
<1µA
RTC voltage buffer
External battery or capacitor
Power Supply
Main Power Supply of Module (DVDD, D1VDD)
3.3V±5%
Rise Time
Max. 1V/ms
Voltage ripple
33mV @0…20MHz
Power Consumption (full load)
Max. 4.5W
Internal power supply domains
BVDD, DVDD, D1VDD, EVDD, USB_HVDD
3.3V
LVDD, L1VDD
2.5V
OVDD, O1VDD
1.8V

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Temperature range
Operating
-40°C/+85°C1
Storage
-55/+125°C
Humidity
Operating
10% …90%
Storage
<95%
MTBF
> 650000h @ 40°C
(applied standard: Siemens SN 29500)
Mechanical dimension
Board size
84mm x 55mm
Table 2: Technical data
1
For the full operating temperature range is to ensure sufficient cooling. For the connection to a heat
sink, a heat spreader is available (see accessories on SYS TEC web page http://www.systec-
electronic.com/, see also sec. 3.14).

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2.3 Block Diagram
The LS1021A signals are combined in signal groups. A signal group is selected using the RCW field
value. Some signal groups serve multiple functions multiplexed by RCW field.
ECUcore-1021
GbE0
DDR3
CLOCK
FLASH
°C RTC
WATCH
DOG
GbE Phy
QorIQ LS1021A
SPI1
EC1
EC2
LANE A
LANE B
LANE C
LANE D
UART1
UART2
I2C1
TDMA
TDMB
QSPI_A
QSPI_B
USB1
SDHC
GPIOs
IRQ0,1,2
JTAG
RGMII/CAN1-2/SAI1,2/FTM1/GPIO
PCIe
SATA/SGMII
SGMII/PCIe/SATA
SGMII
UART2-4/LPUART1,2,4/SPI2
DISPLAY/GPIO/UCC1/SAI3/FTM4
DISPLAY/GPIO/UCC3/SPDIF/SAI4/FTM4
SDHC/I2C2/LPUART2,3,5,6/GPIO
USB3.0
IRQs
GPIO/IRQ
I2C
SPI
QSPI
Battery
RESET
Trigger IN/OUT
CAN3-4/FTM2/GPIO
UART1
Module connector
3.3V
PMIC
Available Interfaces on Carrier Board:
TAMPER TAMPER-Detection
Figure 1: Block diagram ECUcore-1021

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The following table shows the primary and the alternative signal functions for off-board usable signals.
Field Name from
LS1021A RM
Voltage
domain
Primary signal functions
(defined by SYS TEC BSP)
Alternative signal functions
(defined by Customer specific BSP)
EC1
2.5V
CAN1, CAN2
RGMII, GPIO3, SAI1, SAI2, FTM1
EC2
2.5V
CAN3, CAN4
GPIO3, FTM2
EC3
2.5V
RGMII3
-
MDC/MDIO
2.5V
EMI1
-
RTC
1.8V
RTC
GPIO1_14
ASLEEP
1.8V
ASLEEP
GPIO1_13
EVT[9]_B
1.8V
EVT[9]_B
GPIO2_24
UART_EXT,
UART_BASE
3.3V
UART1, LPUART1, 2D-ACE
(Display)
GPIO1, UART2, UART3, UART4,
LPUART2, LPUART4, SPI2
QE/TDMA
3.3V
2D-ACE (Display)
GPIO4, UC1, SAI3, FTM4
QE/TDMB
3.3V
2D-ACE (Display)
GPIO4, UC3, SPDIF, SAI4, FTM4
IIC_EXT,
IIC_BASE
3.3V
IIC1, SDHC
GPIO4, IIC2, SPI2
SDHC_EXT,
SDHC_BASE
3.3V
SDHC
GPIO2, LPUART2, LPUART3,
LPUART5, LPUART6
SDHC
3.3V
GPIO4_23-GPIO4_26
SDHC
IRQ_EXT,
IRQ_BASE
2.5V
3.3V
IRQ3
IRQ4, IRQ5
-
CLK9-12
3.3V
CLK9-12
GPIO4_19-GPIO4_22, BRG01-4
SPI1
3.3V
SPI1 signals
IFC pins
Table 3: Overview to primary and alternative signal functions of LS1021A signal groups

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2.4 Module connector and pin assignment
This chapter describes the module pin and connector configuration. The connector on the module side is
called receptacle, the connector on the Carrier board is called plug-in connector.
Note: The connectors are COMexpress compatible types. However, the pin assignment and the
connector arrangement meet not the COMexpress standard!
2.4.1 Connector type for the Carrier board
The Carrier board shall use a 5mm or 8mm heights 220pin plug-in connector:
Supplier
Board-to-board stack height
Order number of supplier
Tyco Electronics
5mm
3-1827253-6
8mm
3-6318491-6
Foxconn
5mm
QT002206-2131-3H
8mm
QT002206-4131-3H
Table 4: Carrier board plug-in connector
2.4.2 Pin assignment row A and row B
The pin name corresponds to the primary pin name of the LS1021A called by NXP, unless there is only
an alternative function available. In this case the pin name corresponds to the alternative function only.
For description of primary and alternative function see the NXP data sheets.
A pin configuration is defined by the Reset Configuration Word (RCW). The RCW is pre-installed
according to the ordered module variant (see chapter 2.1).
In contrast to the description in the NXP data sheet and Reference Manual, the active-low signals are
denoted by “/” (example: UART2_RTS_B (NXP manual) is denoted as UART2_/RTS).
The module has two primary power supply domains (DVDD, D1VDD) and several domains that are on-
board generated (BVDD, EVDD, OVDD, O1VDD, ...). For every pin, the corresponding voltage domain is
specified. An internal pull-up resistor is connected to this voltage domain then. Signals that relates to
voltage domains lower than 3.3V are marked with the voltage value in the signal name.
For every pin, the recommendations of the manufacture must be noted. The information in the
data sheet of LS1021A must be observed.

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Pin
Name
Voltage
domain
Notes
A1
GND
-
A2
ASLEEP_1V8
O1VDD (1.8V)
Internal pull-up resistor (4.7kΩ)
A3
QSPI_DQS_B
BVDD (3.3V)
A4
QSPI_CK_B
BVDD (3.3V)
Note 1
A5
QSPI_/CS_B1
BVDD (3.3V)
A6
QSPI_/CS_B0
BVDD (3.3V)
A7
QSPI_DIO_B3
BVDD (3.3V)
A8
QSPI_DIO_B2 (IFC_/PERR)
BVDD (3.3V)
A9
QSPI_DIO_B1 (IFC_PAR1)
BVDD (3.3V)
A10
QSPI_DIO_B0 (IFC_PAR0)
BVDD (3.3V)
A11
GND
-
A12
IFC_CLK1
BVDD (3.3V)
A13
IFC_CLK0
BVDD (3.3V)
A14
IFC_/RB0
BVDD (3.3V)
This Pin has an internal pull-up resistor of
4.7kΩ.
A15
IFC_/WE0
BVDD (3.3V)
This Pin has an internal pull-down resistor of
4.7kΩ.
A16
IFC_CLE
BVDD (3.3V)
A17
IFC_/OE
BVDD (3.3V)
Pin must NOT be pulled down during power-on
reset.
A18
IFC_BCTL
BVDD (3.3V)
Pin is actively driven during reset.
A19
IFC_AVD
BVDD (3.3V)
Pin must NOT be pulled down during power-on
reset. This Pin has an internal pull-up resistor of
4.7kΩ.
A20
SPI1_SIN (IFC_AD15)
BVDD (3.3V)
Optionally, this pin can be configured as
IFC_AD15 signal on request (assembly variant,
see ).
A21
GND
-
A22
SPI1_SCK
BVDD (3.3V)
A23
SPI1_PCS0 (IFC_/CS1)
BVDD (3.3V)
A24
IFC_/CS0
BVDD (3.3V)
Note 1
A25
IFC_AD14
BVDD (3.3V)
Select Boot device:
1 = QSPI-Flash is Boot device (Default)
0 = SD-Card is Boot device
This pin is a reset configuration pin and has an
internal pull-up resistor of 10kΩ. According to
the external pin configuration see also Note 1.
A26
SPI1_SOUT (IFC_AD13)
BVDD (3.3V)
Note 2
A27
SPI1_PCS5 (IFC_AD12)
BVDD (3.3V)
Note 2
A28
SPI1_PCS4 (IFC_AD11)
BVDD (3.3V)
Note 2
A29
SPI1_PCS3 (IFC_AD10)
BVDD (3.3V)
Note 1
A30
SPI1_PCS2 (IFC_AD9)
BVDD (3.3V)
Note 2
A31
GND
-
A32
SPI1_PCS1 (IFC_AD8)
BVDD (3.3V)
Note 2
A33
IFC_AD7
BVDD (3.3V)
A34
IFC_AD6
BVDD (3.3V)

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Pin
Name
Voltage
domain
Notes
A35
IFC_AD5
BVDD (3.3V)
A36
IFC_AD4
BVDD (3.3V)
A37
IFC_AD3
BVDD (3.3V)
A38
IFC_AD2
BVDD (3.3V)
A39
IFC_AD1
BVDD (3.3V)
A40
IFC_AD0
BVDD (3.3V)
A41
GND
-
A42
USB1_TX_P
-
A43
USB1_TX_M
-
A44
USB1_RX_P
-
A45
USB1_RX_M
-
A46
USB1_DP
-
A47
USB1_DM
-
A48
USB1_VBUS
USB_VBUS
See CPU datasheet for interface
recommendation
A49
GPIO4_26
DVDD (3.3V)
A50
GPIO4_25
DVDD (3.3V)
A51
GND
-
A52
GPIO4_24
DVDD (3.3V)
A53
GPIO4_23
DVDD (3.3V)
A54
SDHC_DAT3
EVDD (3.3V)
A55
SDHC_DAT2
EVDD (3.3V)
A56
SDHC_DAT1
EVDD (3.3V)
A57
SDHC_DAT0
EVDD (3.3V)
A58
SDHC_CLK
EVDD (3.3V)
A59
SDHC_CMD
EVDD (3.3V)
A60
GND
-
A61
SDHC_WP/I2C2_SDA
DVDD (3.3V)
If configured as I2C interface signal this pin is
an open-drain signal and a pull-up resistor of
1kΩshould be placed on this pin to 3V3.
A62
SDHC_/CD/I2C2_SCL
DVDD (3.3V)
If configured as I2C interface signal this pin is
an open-drain signal and a pull-up resistor of
1kΩshould be placed on this pin to 3V3.
A63
VBAT
-
On-board RTC power supply pin (2.0V … 3.6V)
A64
RTC_1V8
OVDD (1.8V)
Internal pull-down resistor (10kΩ)
A65
TA_BB_RTC_1V0
TA_BB_VDD
(1.0V)
Internal pull-down resistor (10kΩ)
A66
/TA_TD_1V8
OVDD (1.8V)
Tamper Detect input TA_TMP_DETECT_B
(Internal pull-up resistor of 1kΩ)
A67
/TA_BB_TD_1V0
TA_BB_VDD
(1.0V)
Low Power Tamper Detect
(TA_BB_TMP_DETECT_B) (Internal pull-up
resistor of 1kΩ)
A68
/TEST_SEL_1V8
O1VDD (1.8V)
Internal pull-up resistor (1kΩ)
A69
THERM_/CRIT
DVDD (3.3V)
Open-drain output of CPU temperature sensor
to signal critical temperature values (Internal
pull-up resistor (4.7kΩ) to 3.3V), see chap. 3.11
A70
GND
-
A71
/EVT3_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ
A72
/EVT4_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ

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Pin
Name
Voltage
domain
Notes
A73
CLK2_25M_3V3
DVDD (3.3V)
25MHz Reference clock for external devices
A74
GND
-
A75
SD1_RX3_P
-
SERDES Lane D Receive data (positive)
A76
SD1_RX3_N
-
SERDES Lane D Receive data (negative)
A77
GND
-
A78
SD1_TX3_P
-
SERDES Lane D Transmit data (positive)
A79
SD1_TX3_N
-
SERDES Lane D Transmit data (negative)
A80
GND
-
A81
SD1_CLK0_P
-
PCIe 100MHz Reference clock (positive)
A82
SD1_CLK0_N
-
PCIe 100MHz Reference clock (negative)
A83
GND
-
A84
SD1_RX0_P
-
SERDES Lane A Receive data (positive)
A85
SD1_RX0_N
-
SERDES Lane A Receive data (negative)
A86
GND
-
A87
SD1_TX0_P
-
SERDES Lane A Transmit data (positive)
A88
SD1_TX0_N
-
SERDES Lane A Transmit data (negative)
A89
3V3
DVDD
Module power supply input (switchable) DVDD
A90
GND
-
A91
UART2_TX
D1VDD (3.3V)
Signal UART2_SOUT of LS1021A
A92
UART2_RX
D1VDD (3.3V)
Signal UART2_SIN of LS1021A
A93
UART2_/RTS
D1VDD (3.3V)
A94
UART2_/CTS
D1VDD (3.3V)
A95
UART1_RX
DVDD (3.3V)
Signal UART1_SIN of LS1021A
A96
UART1_TX
DVDD (3.3V)
Signal UART1_SOUT of LS1021A
A97
UART1_/RTS
DVDD (3.3V)
A98
UART1_/CTS
DVDD (3.3V)
A99
CLK11
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
A100
GND
-
A101
CLK12
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
A102
/MR
D1VDD (3.3V)
low-active Manual RESET input (internal pull-up
resistor of 10kΩ)
A103
/PORST
D1VDD (3.3V)
Open-drain RESET output of PMIC with internal
pull-up resistor of 10kΩ
A104
/HRESET_1V8
O1VDD (1.8V)
This pin has an internal pull-up resistor of 1kΩ.
A105
/RESET_REQ_1V8
O1VDD (1.8V)
This pin has an internal pull-up resistor of 1kΩ.
A106
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
A107
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
A108
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
A109
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
A110
GND
-
Table 5: Connector pin assignment (row A)

SYS TEC electronic GmbH
L-1589e-04 Hardware Manual ECUcore-1021
Page 18/30
Classification: Release
Pin
Name
Voltage domain
Notes
B1
GND
-
B2
I2C1_SCL
D1VDD (3.3V)
Signal IIC1_SCL of LS1021A (open-drain) with
internal pull-up resistor of 7.5kΩ
B3
I2C1_SDA
D1DVDD (3.3V)
Signal IIC1_SDA of LS1021A (open-drain) with
internal pull-up resistor of 7.5kΩ
B4
SDC_SWD_CLK
DVDD (3.3V)
Reserved (Internal pull-down resistor of 10kΩ)
B5
SDC_SWD_DIO
DVDD (3.3V)
Reserved (Internal pull-up resistor of 10kΩ)
B6
SDC_/BOOT
DVDD (3.3V)
Reserved (Internal pull-up resistor of 4.7kΩ)
B7
SDC_/RESET
DVDD (3.3V)
Reserved (Internal pull-up resistor of 4.7kΩ)
B8
WDTI
DVDD (3.3V)
Watchdog trigger input (floating to disable watchdog)
B9
WDTO
DVDD (3.3V)
Watchdog output
B10
SDC_ADC0
-
Reserved (SDC analog Input ADC0)
B11
GND
-
B12
SDC_CLKOUT
DVDD (3.3V)
Reserved (RTC clockout)
B13
/IRQ0_1V8
O1VDD (1.8V)
Internal pull-up resistor of 1kΩ
B14
/IRQ1_1V8
OVDD (1.8V)
Internal pull-up resistor of 1kΩ
This pin is connected internal to the PMIC interrupt
output (open-drain).
B15
/IRQ2_2V5
L1VDD (2.5V)
Internal pull-up resistor of 4.7kΩ
B16
/IRQ3_2V5
LVDD (2.5V)
Internal pull-up resistor of 4.7kΩ
This pin is connected internal to the Ethernet Phy
interrupt output (open-drain).
B17
/IRQ4_3V3
DVDD (3.3V)
Internal pull-up resistor of 4.7kΩ
This pin is connected internal to the SDC interrupt
output (optional, open-drain) and Temperature
sensor interrupt output (open-drain).
B18
/IRQ5_3V3
DVDD (3.3V)
Internal pull-up resistor of 4.7kΩ
B19
/EVT9_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ
B20
IFC_TE
BVDD (3.3V)
B21
GND
-
B22
EC1_TXD0
L1VDD (2.5V)
B23
EC1_TXD1
L1VDD (2.5V)
B24
EC1_TXD2
L1VDD (2.5V)
B25
EC1_TXD3
L1VDD (2.5V)
B26
EC1_RX_DV
L1VDD (2.5V)
B27
EC1_RXD0
L1VDD (2.5V)
B28
EC1_RXD1
L1VDD (2.5V)
B29
EC1_RXD2
L1VDD (2.5V)
B30
EC1_RXD3
L1VDD (2.5V)
B31
GND
-
B32
EC1_RX_CLK
L1VDD (2.5V)
B33
EC1_GTX_CLK
L1VDD (2.5V)
B34
EC1_GTX_CLK125
L1VDD (2.5V)
B35
EC1_TX_EN
L1VDD (2.5V)
B36
CLK3_25M_2V5
LVDD (2.5V)
B37
EMI1_MDC
L1VDD (2.5V)
Internal pull-up resistor of 4.7kΩ
B38
EMI1_MDIO
L1VDD (2.5V)
Internal pull-up resistor of 4.7kΩ
B39
EC2_RX_CLK
LVDD (2.5V)

SYS TEC electronic GmbH
L-1589e-04 Hardware Manual ECUcore-1021
Page 19/30
Classification: Release
Pin
Name
Voltage domain
Notes
B40
EC2_TX_EN
LVDD (2.5V)
B41
GND
-
B42
EC2_RX_DV
LVDD (2.5V)
B43
EC2_TXD0
LVDD (2.5V)
B44
EC2_TXD1
LVDD (2.5V)
B45
EC2_TXD2
LVDD (2.5V)
B46
EC2_TXD3
LVDD (2.5V)
B47
EC2_RXD0
LVDD (2.5V)
B48
EC2_RXD1
LVDD (2.5V)
B49
EC2_RXD2
LVDD (2.5V)
B50
EC2_RXD3
LVDD (2.5V)
B51
GND
-
B52
GBE0_D-
-
Gigabit Ethernet Interface 0:
MDI[3]-, negative signal of differential pair
B53
GBE0_D+
-
Gigabit Ethernet Interface 0:
MDI[3]+, positive signal of differential pair
B54
GBE0_C-
-
Gigabit Ethernet Interface 0:
MDI[2]-, negative signal of differential pair
B55
GBE0_C+
-
Gigabit Ethernet Interface 0:
MDI[2]+, positive signal of differential pair
B56
GBE0_B-
-
Gigabit Ethernet Interface 0:
MDI[1]-, negative signal of differential pair
B57
GBE0_B+
-
Gigabit Ethernet Interface 0:
MDI[1]+, positive signal of differential pair
B58
GBE0_A-
-
Gigabit Ethernet Interface 0:
MDI[0]-, negative signal of differential pair
B59
GBE0_A+
-
Gigabit Ethernet Interface 0:
MDI[0]+, positive signal of differential pair
B60
GND
-
B61
GBE0_LED2
Gigabit Ethernet Interface 0: LINK LED (Green)
LINK off: GBE0_LED2 = H => LED OFF
LINK on: GBE0_LED2 = L => LED ON
Note: Internal pull-down resistor of 1kΩ.
B62
GBE0_LED1
Gigabit Ethernet Interface 0: ACTIVITY LED (Yellow)
No Activity: GBE0_LED1 = H => LED OFF
Activity (Rx, Tx): GBE0_LED1 = Toggle => LED
Blinking
Note: Internal pull-up resistor of 10kΩ.
B63
JTAG_VREF_1V8
OVDD (1.8V)
Reference voltage of 1.8V for JTAG interface
(Internal series resistor of 270Ω)
B64
JTAG_/RESET
OVDD (1.8V)
This signal triggers the /PORESET signal of
LS1021A during boundary scan test session.
B65
JTAG_TMS
OVDD (1.8V)
Signal TMS of LS1021A
B66
JTAG_TCK
OVDD (1.8V)
Signal TCK of LS1021A (Internal pull-up of 10kΩ)
B67
JTAG_TDO
OVDD (1.8V)
Signal TDO of LS1021A
B68
JTAG_TDI
OVDD (1.8V)
Signal TDI of LS1021A
B69
/EVT0_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ
B70
GND
-
B71
/EVT1_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ
B72
/EVT2_1V8
O1VDD (1.8V)
Internal pull-up resistor of 10kΩ

SYS TEC electronic GmbH
L-1589e-04 Hardware Manual ECUcore-1021
Page 20/30
Classification: Release
Pin
Name
Voltage domain
Notes
B73
CLK1_25M_3V3
DVDD (3.3V)
B74
GND
-
B75
SD1_RX1_N
-
SERDES Lane B Receive data (negative)
B76
SD1_RX1_P
-
SERDES Lane B Receive data (positive)
B77
GND
-
B78
SD1_TX1_N
-
SERDES Lane B Transmit data (negative)
B79
SD1_TX1_P
-
SERDES Lane B Transmit data (positive)
B80
GND
-
B81
SD1_CLK2_N
PCIe 100MHz Reference clock (negative)
B82
SD1_CLK2_P
PCIe 100MHz Reference clock (positive)
B83
GND
-
B84
SD1_RX2_N
SERDES Lane C Receive data (negative)
B85
SD1_RX2_P
SERDES Lane C Receive data (positive)
B86
GND
-
B87
SD1_TX2_N
SERDES Lane C Transmit data (negative)
B88
SD1_TX2_P
SERDES Lane C Transmit data (positive)
B89
3V3
DVDD
Module power supply input (switchable) DVDD
B90
GND
-
B91
CLK10
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B92
CLK09
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B93
TDMB_RQ
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B94
TDMB_TSYNC
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B95
TDMB_TXD
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B96
TDMB_RSYNC
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B97
TDMB_RXD
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B98
TDMA_RQ
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B99
TDMA_TSYNC
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B100
GND
-
B101
TDMA_TXD
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B102
TDMA_RSYNC
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B103
TDMA_RXD
DVDD (3.3V)
This Pin has an internal series resistor of 33Ω.
B104
2V5_LVDD
LVDD
Power supply output 2.5V to supply external level
shifter
B105
3V3
DVDD
Module power supply input (switchable) DVDD
B106
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
B107
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
B108
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
B109
3V3_D1VDD
D1VDD
Module power supply input (always on) D1VDD
B110
GND
-
Table 6: Connector pin assignment (row B)
Note 1: This pin is a reset configuration pin and has an internal pull-up resistor of 4.7kOhm. The signal
must be high after reset. If there is any device on the net of customer carrier board that might pull down
the value of the net at reset, a pull-up or active driver is needed.
Note 2: This pin is a reset configuration pin and has an internal pull-down resistor of 1kOhm. The signal
must be low after reset. If there is any device on the net of customer carrier board that might pull up the
value of the net at reset, a pull-down or active driver is needed.