Tandy 26-3334 User manual

TANDY'
Service /~\
Ul
COLOR COMPUTER 3
IMTSC/PAL VERSION
with 512K Expansion RAM Card
Catalog Number: 26-3334
CUSTOM MANUFACTURED FOR RADIO SHACK, ADIVISION OF TANDY CORPORATION

TABLE OF CONTENTS
SECTION I. GENERAL
1.1 Introduction 5
1.2 System Description 5
1.3Memory Map 8
1.4 I/O Control Registers 9
1.5 Chip Control Registers 11
1.6 68B09E Vector Registers 22
SECTION II. SPECIFICATIONS
2.1 Technical 23
2.2 Physical 25
SECTION III. DISASSEMBLY/ASSEMBLY
3.1 Disassembly 26
3.2 Assembly 26
3.3 512K RAM Upgrade Instructions 27
SECTION IV. BLOCK DIAGRAM
4.1 NTSC Version 28
4.2 PAL Version 29
SECTION V. THEORY OF OPERATION
5.1 MC68B09E/MBL68B09E/HD68B09E (IC1) 30
5.2 Memory (RAM) 34
5.3 TCC1014 (VC2645QC) 36
5.4 PAL Encoder (PAL Version Only) 38
5.5 PIAs <IC4 and IC5) 39
5.6 Keyboard Interface (IC5) 40
5.7 ROM (IC2) 41
5.8 DAC Circuitry (IC7) 42
5.9 SALT Circuitry 44
5.10 Cassette Tape Format Information 47
5.11 RS-232C Connector (JK3) 47
5.12 Cartridge Connector (CNl) 49
5.13 Power Transformer 52
5.14 Joysticks 52
5.15 TV Switch Box (NTSC Version Only) 53
SECTION VI. TROUBLESHOOTING
6.1 Introduction 54
6.2 Video Problems 55
No Display/No Sync/Noisy Video 55
Wrong Color 55
No Color ,,55
Random Character/Clear Screen/No Sign-on ....55
RGB Problem 55
Composite Video Signal Adjustment
(PAL Version Only) 56
-2-

6.
3
Keyboard Problems 56
No Keyboard Entry/Wrong Character 56
6.4 Process ing Problem 56
6.5 Cassette Problems 56
Motor Control Problem 56
Write Problem 56
Read Problem 56
6.6 RS-232C Problem 57
6.7 Sound Problem 57
6.8 Joystick Problem 57
6.9 Cartridge Problem 57
6.10 Power Supply Check 58
NTSC Vers ion 58
PAL Version 61
6.11 Major Waveforms 64
NTSC Vers ion 64
PAL Version 70
SECTION VII. 512K EXPANSION RAM CARD
PCB VIEWS 78
ELECTRICAL PARTS LIST 79
SECTION VIII. NTSC VERSION
PCB VIEWS 82
ELECTRICAL PARTS LIST 84
EXPLODED VIEW PARTS LIST 90
EXPLODED VIEW 91
SEMICONDUCTOR INFORMATION 93
SCHEMATIC DIAGRAM 103
SECTION IX. PAL VERSION
PCB VIEWS 108
ELECTRICAL PARTS LIST 1 1
1
EXPLODED VIEW PARTS LIST 119
EXPLODED VIEW 121
SEMICONDUCTOR INFORMATION 122
SCHEMATIC DIAGRAM 126
-3-

LIST OF FIGURES
1-1. Color Computer 3Installation 7
1-2. Color Computer 3Memory Map 8
1-3. Memory Map for SAM Control Register 21
3-1. Removal of Top Cover 26
3-2
.
Removal of Main PCB 26
3-3. Main PCB ][ 27
3-4. 512K RAM Card 27
4-1. Block Diagram 28
NTSC Version 28
PAL Version 29
5-1. MC68B09E Programming Model 30
5-2. MC68B09E Pin Assignments 31
5-3. MC68B09E Read/Write Timing at 0.89 MHz 33
5-4. DRAM Block Diagram 34
5-5 .DRAM Timing 35
5-6. Color Computer 3Address Decoding 36
5-7. MMU Block Diagram 37
5-8. PIA Block Diagram 39
5-9. Color Computer 3Keyboard Array 40
5-10. DAC Block Diagram (IC7) 42
5-11. SALT Block Diagram (IC8) 44
5-12. Color Computer 3Power Supply 45
5-13. I/O Circuitry 45
5-14. RS-232C Connector Pinout 48
5-15. Joystick Schematic 52
5-16. Antenna Switch Box Schematic ....53
LIST OF TABLES
1Line Printer Variables 50
2Alternate Line Printer Variable Values 50
3Cartridge Connector Signals ,51
-4-

SECTION I. GENERAL
1.1 Introduction
The Color Computer 3is arefined
version of Tandy's popular Color
Computer 2. It is designed to provide
the same reliable operation as its
predecessor, but it incorporates the
latest in electronic technology.
Figure 1-1 shows atypical
installation of the Color Computer 3.
The Color Computer 3contains an
internal BASIC program in ROM which
is accessed when the unit is powered
up. Other program modules/cartridges
may be inserted into the receptacle
on the right side of the unit. An
optional Multi-pak Interface module
allows up to four program paks to be
installed at the same time, with
selection of the specific module
active at any one time selected
either by software or by aswitch on
the Multi-pak Interface. Additional
peripheral devices, such as an
external disk drive, may be added to
the Color Computer 3for additional
memory storage and retrieval.
All input and output ports for the
Color Computer 3, with the exception
of the program module/cartridge slot
and the RGB monitor output (for
CM-8), are located on the rear panel
of the unit. These include the
joystick input ports (right and
left), Serial I/O, Cassette I/O, TV
output jack (for standard color
television set and composite
monitor), POWER ON/OFF switch and
RESET switch. Arecessed channel
switch (for selecting either channel
on the TV -3/4 for NTSC and 1/2 for
PAL version) is also located on the
rear panel of the unit.
1.2 System Description
The primary functions of the Color
Computer 3are performed by four
Large Scale Integration (LSI) chips,
plus Random Access Memory (RAM) and
Read Only Memory (ROM). These four
chips are labeled on the block
diagram as CPU, ACVC and two PIAs.
With only these four chips, plus
Random Access Memory (RAM), Read Only
Memory (ROM) and apower supply, the
Color Computer 3will operate and
provide video output (RF, Composite,
Analog RGB). However, to allow
communication with the outside world,
I/O interfaces must be added.
The main component of any computer
system is the Central Processing Unit
(CPU, IC1). It is the function of the
CPU to provide or request data and
select the proper address for this
data. In addition, the CPU is capable
of performing alimited set of
mathematical and logical operations
on the data.
ROM (IC2) has the function of
providing the CPU with apredefined
set of instructions. Without ROM, the
CPU would run wild and randomly
execute instructions. In normal
operation, the CPU jumps to the start
address in ROM, after the reset
switch has been pressed, and then
performs the reset program to set up
all of the programmable devices.
Following this, the BASIC interpreter
residing in ROM is in control of the
CPU.
Note: Before installing any
peripheral device, always remember to
unplug the Color Computer's power
cord. This will prevent damage to the
device or to the Color Computer 3.
-5-

RAM (IC16 -IC19) provides storage
for the programs and/or data
currently being executed. In the
standard unit, these four ICs are 64K
x4but may be upgraded to sixteen
256K x1ICs as an option. (See
Paragraph 3.3 on page 28 for
instructions.) In addition, the same
RAM is used to generate the video
display. Normally, no conflict will
be observed because the program will
use one portion of RAM and the
display will use another. During
normal usage, the BASIC interpreter,
located in ROM, will control the
execution of programs located in RAM.
Acentral component in the Color
Computer 3is the Advanced Color
Video Chip (IC6). This chip provides
refresh and address multiplexing for
the RAM, It also provides all of the
system timing and device selection.
ACVC comprises the VDG (Video Display
Generator) function which supports
High-Resolution mode, in addition to
all other modes included in the Color
Computer 2. During High-Resolution
mode, it generates 40 x24 or 80 x24
text screen, and 320 x192 or 640 x
192 graphics screen. It is also
designed to output two different
video signals -composite video and
analog RGB.
ACVC can expand memory space up to
512K bytes. Having abuilt-in MMU
(Memory Management Unit), it can
support 2banks of 256K-byte RAM,
each with a9-line address bus, even
though the CPU possesses only 16
address lines.
The remaining circuitry in the Color
Computer 3is devoted to Input/Output
(I/O) communication. The most
important part of this circuitry is
the keyboard, which allows the
operator to enter information. Other
I/O circuits are provided to allow
joystick input, cassette input and
output, and RS-232C input and output.
-6-

-7-

1.3Memory Map
Figure 1-2 shows the breakdown of the $?FFfF
large blocks of memory in the Color
Computer 3.
The rest of the section itemizes the
following registers:
•I/O Control Register
•Chip Control Register
•68B09E Vector Register
S7FFOO
S7E000-
S7COO0-
S7A0O0-
$78000-
$70600-
$70400-
$70000-
S6E00O-
S6C000-
$68000-
$60000-
68B09E VECTOR, h
CONTROL
-REGISTER, I/O
SUPER EXTENDED BASIC
CARTRIDGE ROM
COLOR BASIC
EXTEND COLOR BASIC
STANDARD TEXT SCREEN
HIGH RESOLUTION
TEXT SCREEN
HIGH RESOLUTION
GRAPHIC SCREEN
SOOOOO
O
i-
o
o
5
o
u
X
5
<
n.
Figure 1-2. Color Computer 3
Memory Map
-8-

1.4 I/O Control Registers
FFOO -FF03 PIA IC5
FFOO: BIT =KEYBOARD ROW 1
KEYBOARD ROW 2
KEYBOARD ROW 3
KEYBOARD ROW 4
KEYBOARD ROW 5
KEYBOARD ROW 6
KEYBOARD ROW 7
JOYSTICK COMPARISON INPUT
FF01:
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT
BIT 1
and right joystick switch 1
and Left joystick switch 1
and right joystick switch 2
and Left joystick switch 2
Control of HSYNC (63.5us)
Interrupt
Control of Interrupt
Polarity
BIT
BIT
BIT
BIT
BIT
BIT
Normally 1:
SEL 1:
1Always
1Always
Not used
Horizontal sync interrupt flag
f=IRQ* to CPU Disabled
t1=IRQ* to CPU Enabled
(0 =Flag set on the
falling edge of HS
1=Flag set on the
rising edge of HS
=Changes FFOO to the data direction register
LSB of the two analog MUX select lines
FF02: BIT =KEYBOARD COLUMN 1
KEYBOARD COLUMN 2
KEYBOARD COLUMN 3
KEYBOARD COLUMN 4
KEYBOARD COLUMN 5
KEYBOARD COLUMN 6
BIT
BIT
BIT
BIT
BIT
BIT
BIT KEYBOARD COLUMN 7/RAM SIZE OUTPUT
KEYBOARD COLUMN 8
FF03:
CO =IRQ* to CPU Disabled
11=IRQ* to CPU Enabled
/"0 =sets flag on falling edge FS
u-
BIT Control of VSYNC (16.667ms)
Interrupt
BIT 1Control of Interrupt Polarity sets flag on rising edge FS
BIT 2=NORMALLY 1; =changes FF02 to the data direction register
BIT 3=SEL 2: MSB of the two analog MUX select lines
BIT 4=1Always
BIT 5=1Always
BIT 6=Not used
BIT 7=Field sync interrupt flag
-9-

FF20 -FF23 PIA IC4
FF20: BIT =CASSETTE DATA INPUT
BIT 1=RS-232C DATA OUTPUT
BIT 2=6BIT D/A LSB
BIT 3=6BIT D/A
BIT 4=6BIT D/A
BIT 5=6BIT D/A
BIT 6=6BIT D/A
BIT 7=6BIT D/A MSB
FF21; BIT
BIT 1
BIT
BIT
BIT
BIT
BIT
BIT
FF22:
fO =FIRQ* to CPU Disabled
\l =FIRQ* to CPU Enabled
fO =sets flag on falling edge CD
U=
Control of the CD
(RS-232C status)
Interrupt
Control of Interrupt
Polarity (^1 =sets flag on rising edge CD
Normally 1:0= changes FF20 to the data direction register
Cassette Motor Control: =OFF 1=ON
1Always
1Always
Not Used
CD Interrupt Flag
BIT =RS-232C DATA INPUT
BIT 1=SINGLE BIT SOUND OUTPUT
BIT 2=RAM SIZE INPUT
BIT 3=RGB Monitor Sensing INPUT
BIT 4=VDG CONTROL OUTPUT
BIT 5=VDG CONTROL OUTPUT
BIT 6=VDG CONTROL OUTPUT
BIT 7=VDG CONTROL OUTPUT
CSS
GMO &UPPER/LOWER CASE*
GM1 &INVERT
GM2
A*/G
FF23:
=FIRQ* to CPU Disabled
1=FIRQ* to CPU Enabled
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT
fO =sets flag on falling edge CART*
U=
BIT Control of the Cartridge
Interrupt
BIT 1Control of Interrupt
Polarity ^1 =gets flag on rising edge CART*
Normally 1: =changes FF22 to the data direction register
Sound Enable
1Always
1Always
Not used
7=Cartridge Interrupt Flag
FF40 -FFBF: Not used
Note: FF22, FF23 are duplicated in tcclOH (VC2645QC), and V.D.G Control Bit
(Bit 3through Bit 7) affects this IC (TCC1014) only.
-10-

1.5 Chip Control Registers
FF90 -FFDF ACVC IC6
FF90: Initialization Register (INITO)
BIT 7=COCO
BIT 6=M/P
BIT 5=IEN
BIT 4=FEN
BIT 3=MC3
BIT 2=MC2
BIT 1=MCI
BIT =MCO
=Color Computer 1and 2Compatible
=MMU enabled
=Chip IRQ output enabled
=Chip FIRQ output enabled
=DRAM at XFEXX is constant
=Standard SCS
ROM map control (See table below)
ROM map control (See table below)
MCI MCO ROM mapping
1
1
X
1
16K Internal, 16K External
32K Internal
32K External (except for vectors)
FF91: Initialization Register 1(INIT1)
BIT 7
BIT 6
BIT 5=TINS Timer Input Select: 1=70 nsec /
BIT 4
BIT 3
BIT 2
BIT 1
BIT =TR MMU Task Register Select
63 psec
FF92:
FF93:
Interrupt Request Enable Register (IRQENR)
Interrupt from Timer enabled
Horizontal Border IRQ enabled
Vertical Border IRQ enabled
Serial Data IRQ enabled
Keyboard IRQ enabled
Cartridge IRQ enabled
Fast Interrupt Request Enable Register (FIRQENR)
Interrupt from Timer enabled
Horizontal Border FIRQ enabled
Vertical Border FIRQ enabled
Serial Data FIRQ enabled
Keyboard FIRQ enabled
Cartridge FIRQ enabled
BIT 7-
BIT 6-
BIT 5=TMR
BIT 4=HBORD
BIT 3=VBORD
BIT 2=EI2
BIT 1=Ell
BIT =EIO
Fast Int
BIT 7-
BIT 6-
BIT 5=TMR
BIT 4=HBORD
BIT 3=VBORD
BIT 2=EI2
BIT 1=Ell
BIT =EIO
-11-

FF94: Timer Most Significant Nibble
FF95: Timer Least Significant Byte
TIMER: This is a12-bit interval timer. When avalue is loaded into the
MSB, the count is automatically begun. The input clock is either
14 MHz or horizontal sync, as selected by TINS (bit 5of FF91). As
the count falls through zero, an interrupt is generated (if
enabled), and the count is automatically reloaded,
FF96: Reserved
FF97: Reserved
FF98: Video Mode Register
BP =alphanumeric, 1=bit plane
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT =
BPI
MOCH
H50
LPR2
LPR1
LPRO
LPR2
1
1
1
1
1=Burst phase inverted
1=monochrome (on composite)
1=50 Hz vertical sync
Lines per row (See table below)
Lines per row (See table below)
Lines per row (See table below)
LPR1 LPRO
1
1
1
1
Lines per character row
one
two
three
eight
nine
(reserved)
twelve
(reserved)
(Graphics modes)
(CoCo 1and CoCo 2only)
(CoCo 1and CoCo 2only)
(CoCo 1and CoCo 2only)
FF99; BIT
BIT
BIT
BIT
Video Resolution Register
=LPF1
=LPFO
=HRES2
BIT 3=HRES1
BIT 2=HRESO
BIT 1=CRES1
BIT =CRESO
Lines per field (See table below)
Lines per field
Horizontal resolution (See Video resolution on page
17)
Horizontal resolution
Horizontal resolution
Color resolution (See Video resolution)
Color resolution
LPFI LPFO Lines per field
1
1
1
1
192
200
Reserved
225
-12-

FF9A: Border Register (AIL bits are for CoCo Iand CoCo 2compatibility).
BIT 7
BIT 6
BIT 5=RED1 Most significant red bit
BIT 4=GRN1 Most significant green bit
BIT 3=BLU1 Most significant blue bit
BIT 2=REDO Least significant red bit
BIT 1=GRNO Least significant green bit
BIT =BLUO Least significant blue bit
FF9B: Reserved
FF9C: Vertical Scroll Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3=VSC3 (Vert. Scroll)
BIT 2=VSC2
BIT 1=VSC1
BIT =VSCO
NOTE: In the CoCo mode, the VSC 'smust be initialized to OF hex.
FF9D: Vertical Offset 1Register
BIT 7=Y18 (Vert. Offset)
BIT 6»Y17
BIT 5=Y16
BIT 4=Y15
BIT 3=Y14
BIT 2=Y13
BIT 1=Y12
BIT =Yll
FF9E: Vertical Offset Register
BIT 7=Y10 (Vert, Offset)
BIT 6=Y9
BIT 5=Y8
BIT 4=Y7
BIT 3=Y6
BIT 2=Y5
BIT 1=Y4
BIT =Y3
NOTE: In CoCo mode, Y15 -Y9 are not effective, and are controlled by
SAM bits F6 -FO. Also in CoCo mode, Y18 -Y16 should be 1, all others 0.
-13-

FF9F: Horizontal Offset Register
BIT 7=HVEN! Horizontal Virtual Enable
BIT 6=X6 Horizontal Offset address
BIT 5=X5 Horizontal Offset address
BIT 4=X4 Horizontal Offset address
BIT 3=X3 Horizontal Offset address
BIT 2=X2 Horizontal Offset address
BIT 1=XI Horizontal Offset address
BIT =XO Horizontal Offset address
NOTE: HVEN enables ahorizontal screen width of 128 bytes regardless of
the HRES bits and CRES bits selected. This will allow a"virtual" screen
somewhat larger than the displayed screen. The user can move the "window"
(the displayed screen) by means of the horizontal offset bits. In
character mode, the screen width is 128 characters regardless of
attribute (or 64, if double-wide is selected).
-14-

Memory Management Unit (MMU)
XFFAO -XFFAF, 6bits (Write only)
The 8-bit CPU in the Color Computer 3can directly address only 64K bytes of
memory with its 16 address lines (AO -A15). The memory management unit (MMU)
extends the address lines to 19 (AO -A18). This allows the computer to address
up to 512K bytes of memory ($00000 -$7FFFF).
The MMU consists of amultiplexer and a16 x6-bit of RAM array. Each of the
6-bit elements in this RAM array is an MMU task register, and the task
registers are used by the computer to determine the proper 8K segment of memory
to address. These registers are divided into 2sets, 8registers per set. The
TR bit of FF91 (task register select bit) determines which set is selected.
The relationship between the data in the task register and the generated
address is as follows:
Bit
Corresponding
memory
address
D5 D4 D3 D2 Dl DO
A18 AI7 A16 A15 A14 A13
DO-D5
(CPU DATA)
AI3-AI5
TR bit
AO-A3
AI3-AI8
(Extended addresses)
When the CPU needs to access memory outside the standard I/O and control range
(XFF00 -XFFFF), CPU address lines A13 -A15 and the TR bit determine the
address of the task register which the MMU will access while SELECT is low.
When the CPU writes data to the MMU, A0 -A3 determine the address of the task
register to be written to when SELECT goes high.
-15-

The data from the MMU is then used as the upper 6address lines (A13 -A18) for
memory access, according to the following:
TR A15 A14 A13 (Address range) MMU location address
XOOOO -X1FFF FFAO
1X2000 -X3FFF FFA1
1X4000 -X5FFF FFA2
11X6000 -X7FFF FFA3
1X8000 -X9FFF FFA4
11XA000 -XBFFF FFA5
11XC000 -XDFFF FFA6
111XEOOO -XFFFF FFA7
XOOOO -X1FFF FFA8
1X2000 -X3FFF FFA9
1X4000 -X5FFF FFAA
11X6000 -X7FFF FFAB
1X8000 -X9FFF FFAC
11XA000 -XBFFF FFAD
11XC000 -XDFFF FFAE
111XEOOO -XFFFF FFAF
It is important to note that, in order for the MMU to function, the CoCo bit of
FF90 must be cleared, and the M/P bit of FF90 must be set. Prior to doing this,
the desired addressing information for each segment must be loaded into the
designated set of task registers. For example, if astandard 64K map is desired
in the top of 512K RAM, with the TR bit set to 0, the following values should
be pre-loaded into the MMU:
MMU Location
address Data (Hex) Data (Bin) Address range
FFAO 38 111000 70000 -71FFF
FFA1 39 111001 72000 -73FFF
FFA2 3A 111010 74000 -75FFF
FFA3 3B 111011 76000 -77FFF
FFA4 3C 111100 78000 -79FFF
FFA5 3D 111101 7A000 -7BFFF
FFA6 3E 111 110 7CO0O -7DFFF
FFA7 3F 111111 7E000 -7FFFF
NOTE; Data loaded can be selected freely within the range of $00 -$3F.
-16-

COLOR PALETTE
FFBO -FFBF: 16 addresses, 6bits each
For the RGB output, the bits are defined as follows:
Data Bit
Corresponding
RGB output
D5 D4 D3 D2 Dl DO
Rl Gl Bl RO GO BO
For the Composite output, the bits are defined as follows, where 1is
intensity level and Pis phase:
Data Bit
Corresponding
composite
output
D5 D4 D3 D2 Dl DO
II 10 P3 P2 PI P0
Some Color Examples:
Color RGB Composite
Binary Hex Binary Hex
White
Black
Bright Green
Medium Green
Dark Green
Medium Magenta
111111
000000
010010
010000
000010
101000
(3F)
(00)
(12)
(10)
(02)
(28)
110000
000000
100010
010010
000010
010101
(30)
(00)
(22)
(12)
(02)
(15)
For CoCo compatibility, the following values should be loaded upon
initialization. (NOTE: These are the RGB values.)
FFBO Green (12)
FFB1 Yellow (36)
FFB2 Blue (09)
FFB3 Red (24)
FFB4 Buff (3F)
FFB5 Cyan (10)
FFB6 Magenta (2D)
FFB7 Orange (26)
FFB8 Black (00)
FFB9 Green (12)
FFBA Black (00)
FFBB Buff (3F)
FFBC Black (00)
FFBD Green (12)
FFBE Black (00)
FFBF Orange (26)
NOTE: For the PAL version, ignore the table attributed to composite,
-17-

VIDEO RESOLUTION
The combination of HRES and CRES bits determine the resolution of the screen.
The following resolutions are supported:
Alphanumerics: BP =0, CoCo =
RES Bit
Mode
32 character
40 character
80 character
HRES2 HRES1 HRESO CRES1 CRESO
1
1
1
Graphics: BP =1,CoCo =
Pixels Colors HRES2 HRES1 HRESO CRES1 CRESO
640 41I1
640 21
512 411
512 2
320 16 111
320 411
256 16 11
256 41
256 21
160 16 111
In addition to the above modes, the previous CoCo modes are available.
COLOR COMPUTER MODE SELECTION
MC6883 (SAM)
DISPLAY MODE REG. FF22
V2 VI V0 76543
Alphanumerics XXCSS
Alphanumerics Inverted XXCSS
Semigraphics -4XXX
64 X64 Color Graphics 1CSS
128 X64 Graphics 11CSS
128 X64 Color Graphics 11CSS
128 X96 Graphics 1 1 11CSS
128 X96 Color Graphics 11CSS
128 X192 Graphics 1111CSS
128 X192 Color Graphics 1 1 1 1 CSS
256 X192 Graphics 11111CSS
-18-

ALPHANUMERIC MODES
Text screen memory:
Even Byte (Character byte)
BIT 7
BIT 6=Character bit 6
BIT 5=Character bit 5
BIT 4=Character bit 4
BIT 3=Character bit 3
BIT 2=Character bit 2
BIT 1=Character bit 1
BIT =Character bit
Odd Byte (Attribulte byte)
BIT 7=BLINK Characters
BIT 6=UNDLN Characters
BIT 5=FGND2 Foreground
BIT 4=FGND1 Foreground
BIT 3=PGNDO Foreground
BIT 2=BGND2 Background
BIT 1=BGND1 Background
BIT =BGNDO Background
blink at 1/2 sec. rate
are underlined
color bit (pallette addr.)
color bit (pallette addr.)
color bit (pallette addr.)
color bit (pallette addr.)
color bit (pallette addr.)
color bit (pallette addr.)
BOTE: Attributes are not available when CoCo 1.
-19-

GRAPHICS MODES
16 Color Modes: (CRES1 =1, CRESO =0)
Byte from DRAM
Bit 7PA3, First Pixel
Bit 6PA2, First Pixel
Bit 5PAI, First Pixel
Bit 4PAO, First Pixel
Bit 3PA3, Second Pixel
Bit 2PA2, Second Pixel
Bit 1PAI, Second Pixel
Bit PAO, Second Pixel
4Color Modes: (CRES1 =0, CRESO =1)
Byte from DRAM
Bit 7PAI, First Pixel
Bit 6PAO, First Pixel
Bit 5PAI, Second Pixel
Bit 4PAO, Second Pixel
Bit 3PAI, Third Pixel
Bit 2PAO, Third Pixel
Bit 1PAI, Fourth Pixel
Bit PAO, Fourth Pixel
2Color Modes: (CRES1 =0, CRESO =0)
Byte from DRAM
Bit 7PAO, First Pixel
Bit 6PAO, Second Pixel
Bit 5PAO, Third Pixel
Bit 4PAO, Fourth Pixel
Bit 3PAO, Fifth Pixel
Bit 2PAO, Sixth Pixel
Bit 1PAO, Seventh Pixel
Bit PAO, Eighth Pixel
Pallette Addresses
PA3 PA2 PAI PAO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address of Contents Displayed
FFBO
FFB1
FFB2
FFB3
FFB4
FFB5
FFB6
FFB7
FFB8
FFB9
FFBA
FFBB
FFBC
FFBD
FFBE
FFBF
-20-