Teac CT-W3270 User manual

SERVICE MANUAL
CTW3270
32” WIDE CTV
Effective: DEC01 CTW3270SERV

1
CONTENTS
Safety Precautions ........................................................................................................................................... 2
TV Set switched off ........................................................................................................................................... 2
Measurements ................................................................................................................................................. 2
PERI -TV SOCKET ............................................................................................................................................ 2
SC RT 1, SC RT 2 .......................................................................................................................................... 2
INTRODUCTION .............................................................................................................................................. 2
POWER SUPPLY (SMPS) ................................................................................................................................. 3
IF P RT ............................................................................................................................................................. 3-4
TUNER ............................................................................................................................................................. 4-5
S W FILTERS ................................................................................................................................................... 5
DIGIT L TV SOUND PROCESSING ................................................................................................................. 5-6
DOLBY PRO LOGIC PROCESSOR ................................................................................................................. 6-7
HE DPHONE OUTPUT .................................................................................................................................... 7
VIDEO OUTPUT ................................................................................................................................................ 7-8
VIDEO INPUT ND OUTPUT SOURCE SWITCHING ...................................................................................... 8
VIDEO OUTPUT MPLIFIER ST GE ................................................................................................................ 8-9
VERTIC L OUTPUT ST GE ............................................................................................................................. 9
MICROTEXT CONTROLLER ............................................................................................................................ 9-10
SERI L CCESS 32K EEPROM ...................................................................................................................... 10-11
DR M ................................................................................................................................................................ 11
EPROM ............................................................................................................................................................. 11
100Hz FE TURE BOX ...................................................................................................................................... 12
VPC32X5 (VIDEO PROCESSOR) ............................................................................................................... 12-13
CIP3250 ...................................................................................................................................................... 13-14
SD 9400 ..................................................................................................................................................... 14-15
DDP3310 .................................................................................................................................................... 15-16
K28 CH SSIS M NU L DJUSTMENTS PROCEDURE ............................................................................... 17
PRELIMIN RY ............................................................................................................................................. 17
SYSTEM VOLT GE JUSTMENT ................................................................................................................ 17
FC DJUSTMENT ..................................................................................................................................... 17
FOCUS DJUSTMENT................................................................................................................................17
SCREEN DJUSTMENT ............................................................................................................................. 17
IF DJUSTMENT FOR LMODE ................................................................................................................... 17
K28 CH SSIS PRODUCTION MODE DJUSTMENTS PROCEDURE ......................................................... 18
PRELIMIN RY ............................................................................................................................................. 18
HORIZONT L ND VERTIC L GEOMETRY LIGNMENTS ........................................................................ 18
V-SHIFT ....................................................................................................................................................... 18
V-SIZE .......................................................................................................................................................... 18
H-SHIFT ...................................................................................................................................................... 18
H-SIZE ......................................................................................................................................................... 18
S-COR ......................................................................................................................................................... 18
LINRT .......................................................................................................................................................... 18
NGLE ........................................................................................................................................................ 18
BOW ... ........................................................................................................................................................ 18
TRPEZ ......................................................................................................................................................... 18
P R B ......................................................................................................................................................... 18
U.COR ......................................................................................................................................................... 19
L.COR ......................................................................................................................................................... 19
VIDEO LIGNMENTS ........................................................................................................................................ 19
RGn, GGn, BGn,:WHITE B L NCE DJUSTMENT .................................................................................... 19
RRf, GRf, BRf .............................................................................................................................................. 19
YDF . ........................................................................................................................................................... 19
GC . .......................................................................................................................................................... 19
TL N . .......................................................................................................................................................... 19
PS . ........................................................................................................................................................... 19
T_T ............................................................................................................................................................ 19
T_P ............................................................................................................................................................ 19
EXT3 ............................................................................................................................................................ 19
CLT ............................................................................................................................................................ 19
SERVICE LIGNMENTS ................................................................................................................................... 20
IMPORT NT ................................................................................................................................................ 20
DJUSTMENTS GROUOP.......................................................................................................................... 20
OPTIONS GROUP ...................................................................................................................................... 20
SYSTEM GROUP ........................................................................................................................................ 20
GENER L BLOCK DI GR M OF CH SSIS K28 ........................................................................................... 21

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DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCH OFF
The mains supply side of the switch mode power supply transformer is live.
Use an isolating transformer.
The receivers fulfill completely the safety requirements.
Safety precautions
Servicing of this TV should only be carried out by a qualified person.
- Components marked with the warning symbol on the circuit diagram are critical for safety and must only be replaced
with an identical component.
- ower resistor and fusable resistors must be mounted in an identical manner to the original component.
- When servicing this TV, check that the EHT does not exceed 26kV.
TV Set switched off
Make short-circuit between HV-CRT clip and CRT ground layer.
Short C804 (150mF) before changing IC802 or other components in primary side of SM S.
Measurements
Voltage readings and oscilloscope traces are measured under following conditions.
Antenna signal 60dB from colourbar generator. (100% white, 75% colour saturation)
Brightness, contrast, colour set for a normal picture.
Mains supply, 220VAC, 50Hz.
PERI-TV SOCKET
SCART 1 (SC050) SCART 2 (SC051)
1 Audio right output 0.5Vrms / 1K 1 Audio right output 0.5Vrms / 1K
2 Audio right input 0.5Vrms / 10K 2 Audio right input 0.5Vrms / 10K
3 Audio left output 0.5Vrms / 1K 3 Audio left output 0.5Vrms / 1K
4 Ground AF 4 Ground AF
5 Ground Blue 5 Ground Blue
6 Audio left input 0.5Vrms / 10K 6 Audio left input 0.5Vrms / 10K
7 Blue input 0.7Vpp / 75ohm 7 Blue input 0.7Vpp / 75ohm
8 AV switching input 0-12VDC /10K 8 AV switching input 0-12VDC /10K
9 Ground Green 9 Ground Green
10 - 10 -
11 Green input 0.7Vpp / 75ohm 11 -
12 - 12 -
13 Ground Red 13 Ground Red
14 Ground Blanking 14 Ground Blanking
15 Red input 0.7Vpp / 75ohm 15 -
16 Blanking input 0-0.4VDC, 1-3VDC / 75ohm 16 -
17 Ground CVS output 17 Ground CVS output
18 Ground CVS input 18 Ground CVS input
19 CVS output 1Vpp / 75ohm 19 CVS output 1Vpp / 75ohm
20 CVS input 1Vpp / 75ohm 20 CVS input 1Vpp / 75ohm
21 Ground 21 Ground
INTRODUCTION
11Ak28 is a 100Hz flicker free colour television capable of driving 284:3/16:9, 334:3 and 294:3 real flat picture tubes.
The chassis is capable of operation in AL, SECAM, NTSC (playback) colour standards and multiple transmission standards
as B/G, D/K, I/I, and L/L´.Sound system output is supplying 12W (10%THD) for left, right and center outputs of 8ohm speakers,
and 2 x 7W for surround outputs of 2 x 4ohm speakers, connected in series.
TV supports the hightext (level 2.5) teletext standard. It is possible to decode transmissions including high graphical data.
The chassis is equipped with one full EuroScart, two other SCARTs for AV input/output, one front-AV input, one back-AV output,
one headphone output, one SVHS input (via SCART and SVHS connector), one VGA input, two external speaker outputs (left
and right), one centre speaker output, and one surround speaker output for two speakers in series.

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POWER SUPPLY (SMPS)
TDA16846
A SM S transformer controlled by the IC TDA16846, which is designed for driving, controlling, and protecting switching
transistor, provides the DC voltages required at various parts of the chassis. SM S generates the necessary 5V supply for
the micro-controller, 130V supply for the FBT, +/-16V supply for the audio amplifier, which are active in stand-by and others
8V, 12V and 5V for other different parts of the chassis.
When the TV is switched on, a reference voltage is provided to TDA16846 and the start-up operation occurs, then TV enters
into the stand-by position.
Two optocouplers are used to control the regulation of line voltage and stand-by power consumption. There are two regulation
circuits, one in primary side and one in secondary side. The primary regulation circuit provides a control voltage to pin3 of the
IC. Secondary regulation circuit produces a control voltage according to the changes in 130V DC voltage, via an optocoupler
(SFH617A) to pin4 of the IC.
During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to
the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred
to the second side such that the output voltage remains nearly independent of load variations. At the same time, the supply
voltages 12V, 8V, 5V are stabilised by the series regulators.
Features
nLine Current Consumption with FC
nContinuous Frequency Reduction with Decreasing Load
nStable and Adjustable Stand-by Frequency
nVery Low Start-up Current
nSoft-Start for Quiet Start-up
nAdjustable and Voltage Dependent Ringing Suppression Time
nSynchronization and Fixed Frequency Facility
nOver- and Under-voltage Lockout
nSwitch Off at Mains Under-voltage
nMains Voltage Dependent Fold Back oint Correction
nLow ower Consumption
nFree usable Fault Comparators
Pinning
1. OTC Off Time Circuit
2. CS rimary Current Simulation
3. RZI Regulation and Zero Crossing Input
4. SRC Soft-Start and Regulation Capacitor
5. OCI Opto Coupler Input
6. FC2 Fault Comparator 2
7. SYN Synchronization Input
8. N. C. Not Connected
9. REF Reference Voltage and Current
10. FC1 Fault Comparator 1
11. VC rimary Voltage Check
12. GND Ground
13. OUT Output
14. VCC Supply Voltage
IF PART
TDA4470 / TDA4472
The TDA44XX is an integrated bipolar circuit for multistandard video/sound IF (VIF/SIF) signal processing in TV/VCR and
multimedia applications. The circuit processes all TV video IF signals with negative modulation (e.g., B/G standard), positive
modulation (e.g., L standard) and the AM, FM/NICAM sound IF signals. Active carrier generation by F LL (frequency phase-
locked loop) is the principle for true synchronous demodulation. VCO circuit is operating on picture carrier frequency, the
VCO frequency is switchable for L´-mode. AFC without external reference circuit is alignment-free and polarity of the AFC
curve is switchable. VIF-AGC for negative modulated signals operates on peak sync detection principle and for positive
modulation on peak white / black level detection principle. Tuner AGC is adjustable with determining take over point. It has
alignment-free quasi-parallel sound (Q S) mixer for FM/NICAM sound IF signals. Intercarrier output sound is gain controlled
(necessary for digital sound processing). AM-demodulator is completely alignment-free with gain controlled AF output.
Operation of the AM demodulator and Q S mixer (for NICAM-L stereo sound is parallel. TDA4472 is used for negative
modulation and TDA4470 is used for both negative and positive modulation.

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Features
n5V supply voltage; low power consumption
nActive carrier generation by F LL principle (frequency-phase-locked-loop) for true synchronous demodulation
nVery linear video demodulation, good pulse response and excellent intermodulation figures
nVCO circuit is operating on picture carrier frequency, the VCO frequency is switchable for the L mode
nAlignment-free AFC without external reference circuit, polarity of the AFC curve is switchable
nVIF-AGC for negative modulated signals (peak sync detection) and for positive modulation (peak white/black level detector).
nTuner AGC with adjustable take over point
nAlignment-free quasi parallel sound (Q S) mixer for FM/NICAM sound IF signals
nIntercarrier output signal is gain controlled (necessary for digital sound processing)
nComplete alignment-free AM demodulator with gain controlled AF output
nSeparate SIF-AGC with average detection
nTwo independent SIF inputs
narallel operation of the AM demodulator and Q S mixer (for NICAM-L stereo sound)
nackage and relevant pinning is compatible with the single standard version TDA 4472;simplifies the design of an
universal IF module
Pinning
1. Input sensitivity, RMS value : 80mVrms
2. Input sensitivity, RMS value : 80mVrms
3. SIF Input selector switch : 2.0 V
4. Ground
5. IF gain control range : 65dB
6. Input sensitivity, RMS value : 80mVrms
7. Input sensitivity, RMS value : 80mVrms
8. IF gain control range : 65dB
9. Ground
10. Available tuner-AGC current : 2mA
11. Available tuner-AGC current : Min : 0.3V Max : 13.5V
12. Video output : Min : 1.8V Max : 2.2V
13. Standard switch : Min : 0V Max : 0.8V
14. L switch : Min : 0V Max : 3.0V
15. IF gain control range : 65dB
16. Ground
17. Internal reference voltage
18. F LL and VCO : Min : 1mA Max : 4mA
19. AFC switch : Min : 0V Max : 0.8V
20. F LL and VCO : Min : 1mA Max : 4mA
21. F LL and VCO : Min : 1mA Max : 4mA
22. AFC output : 0.7 mA/kHz
23. DC supplay : Min : 4.5V Max : 9.0V
24. DC output voltage : 2V
25. AF output-AM : 2.2V
26. F LL and VCO : Min : 1mA Max : 4mA
27. Input sensitivity, RMS value : 80mVrms
28. Input sensitivity, RMS value : 80mVrms
TUNER
The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the
Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L´, I/I´, and D/K. The
tuning is available through the digitally controlled I2C bus ( LL). Below you will find info on one of the Tuners in use.
General description of UV1316
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a
combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L, I and I. The low IF output impedance has been designed
for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.
Features of UV1316
nMember of the UV1300 family small sized UHF/VHF tuners
nSystems CCIR: B/G, H, L, L, I and I; OIRT: D/K
nDigitally controlled ( LL) tuning via I2C-bus
nOff-air channels, S-cable channels and Hyperband
nWorld standardised mechanical dimensions and world standard pinning
nCompact size
nComplies to CENELEC EN55020 and EN55013

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Pinning
1. Gain control voltage (AGC) : 4.0V, Max:4.5V
2. Tuning voltage
3. I²C-bus address select : Max:5.5V
4. I²C-bus serial clock : Min:-0.3V, Max:5.5V
5. I²C-bus serial data : Min:-0.3V, Max:5.5V
6. Not connected
7. LL supply voltage : 5.0V, Min:4.75V, Max:5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min:30V, Max:35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
SAW FILTERS
K9453 Two channels switchable sound IF saw filter of BG, DK, I, L systems for input channel 2 and of L´
system for input channel 1.
K3953 Two channel switchable video IF saw filter of BG, DK, I, L systems for input channel 2 and of L´
system for input channel 1.
J3950 Video IF saw filter for I system
DIGITAL TV SOUND PROCESSING
MSP3410D
The MS 3410D is an I2C controlled single-chip multistandard sound processor for applications in analog and digital TV
sets. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out is
performed in a single-chip covering all European TV-standards. It is designed to simultaneously perform digital
demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM-mono TV sound and two
FM systems according to the German or Korean terrestrial specs. It is also possible to do AM-demodulation according to
the SECAM system. There is AGC for analog inputs: 0.14 - 3Vpp. All demodulation and filtering is performed on chip and
is individually programmable. All digital NICAM standards (B/G, L, and I) are realised. Only one crystal clock (18.432Mhz)
is necessary. External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop
frequency of the internal LL and for stabilising the frequency in closed-loop operation. The higher the capacitors, the
lower the clock frequency result. The nominal free running frequency should match the centre of the tolerance range
between 18.433 and 18.431Mhz as closely as possible. By means of standardised I2S interface, additional feature
processors (D L35xx, Dolby rologic processor for this chassis) can be connected to the IC.
I2S bus interface consists of five pins:
I2S_DA_IN12 for input four channels (two channels per line) per sampling cycle (32Khz).
I2DA_OUT, for output, two channels per sampling cycle (32KHz).
I2S_CL, for timing of the transmission of I2S serial data, 1.024Mhz.
I2S_WS, for the word strobe line defining the left and right sample.
Features:
n5-band graphic equalizer (as in MS 3400C)
nEnhanced spatial affect (pseudo stereo / base-width enlargement as in MS 3400C)
nHeadphone channel with balance, bass treble, loudness
nBalance for loudspeaker and headphone channels in dB units (optional)
nAdditional pair of D/A converters for SCART2 out
nImproved over-sampling filters (as in MS 3400C)
nAdditional SCART input
nFull SCART in/out matrix without restrictions
nSCART volume in dB units (optional)
nAdditional I²S input (as in MS 3400C)
nNew FM-identification (as in MS 3400C)
nDemodulator short programming
nAuto-detection for terrestrial TV-sound standards
nrecise bit-error rate indication
nAutomatic switch from NICAM to FM/AM or vice versa
nImproved NICAM synchronisation algorithm
nImproved carrier mute algorithm
nImproved AM-demodulation
nADR together with DR 3510A
nDolby ro Logic together with D L 35xx A
nReduction of necessary controlling
nLess external components
nSignificant reduction of radiation

6
Pinning
1. ADR wordstrobe 35. Analog Shield Ground 1
2. Not connected 36. Scart input 3 in right
3. ADR data output 37. Scart input 3 in left
4. I²S 1 data input 38. Analog Shield Ground 4
5. I²S data output 39. Scart input 4 in, right
6. I²S wordstrobe 40. Scart input 4 in, left
7. I²S clock 41. Not connected
8. I²S data 42. Analog reference voltage high voltage part
9. I²S clock 43. Analog ground
10. Not connected 44. Volume capacitor MAIN
11. Standby (low-active) 45. Analog power supply 8.0V
12. I²C Bus address select 46. Volume capacitor AUX
13. Digital control output 0 47. Scart output 1, left
14. Digital control output 1 48. Scart output 1, right
15. Not connected 49. Reference ground 1 high voltage part
16. Not connected 50. Scart output 2, left
17. Not connected 51. Scart output 2, right
18. Audio clock output 52. Analog Shield Ground 3
19. Not connected 53. Not connected
20. Crystal oscillator 54. Not connected
21. Crystal oscillator 55. Not connected
22. Test in 56. Analog output MAIN, left
23. IF input 2 (if ANA_IN1+is used only, connect 57. Analog output MAIN, right to AVSS with 50 pF capacitor) 58.
24. IF common 58. Reference ground 2 high voltage part
25. IF input 1 59. Analog output AUX, left
26. Analog power supply +5V 60. Analog output AUX, right
27. Analog ground 61. ower-on-reset
28. Mono input 62. Not connected
29. Reference voltage IF A/D converter 63. Not connected
30. Scart input 1 in, right 64. Not connected
31. Scart input 1 in, left 65. I²S2-data input
32. Analog Shield Ground 2 66. Digital ground
33. Scart input 2 in, right 67. Digital power supply +5V
34. Scart input 2 in, left 68. ADR clock
DOLBY PRO LOGIC PROCESSOR IC
DPL3519A
The IC D L3519A processor family is designed to decode Dolby encoded surround sound. The IC integrate the complete
Dolby Surround ro Logic decoding on chip without any necessary external circuitry. It designed as a coprocessor of the
MS 34xx family.
It gets digitised sound from the audio processor IC MS 3410D for both C (centre) and S (surround) channels, and for
both L (left) and R (right) channels. The analog L and R outputs are supplied by MS 3410D, while the analog S and C
outputs are supplied by the D L33519A.
Two I2S busses obtain synchronisation between the MS and D L :
I2S_CL; for timing of the transmission of I2S serial data 1.024Mhz and I2S_WS; The word strobe line defining the left
and right sample at 32Khz. The IC is also I2C bus controlled to select the sound feature (Stereo, 3D- honic and Dolby
ro Logic).
Pinning
1. Not connected 16. Not connected
2. Not connected 17. Not connected
3. Not connected 18. Audio clock output
4. I2S1 data input 19. Digital control input
5. I2S1 data output 20. Crystal oscillator
6. I2S wordstrobe 21. Crystal oscillator
7. I2S clock 22. Test pin
8. I2C data 23. Not connected
9. I2C clock 24. Not connected
10. Not connected 25. Not connected
11. Standby (low-active) 26. Analog power supply +5 V
12. I2C-Bus address select 27. Analog ground
13. Digital control IO 0 28. Mono input
14. Digital control IO 1 29. Reference voltage
15. Not connected 30. Scart input 1 in, right

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31. Scart input 1 in, left 50. Scart output 2, left
32. Analog Shield Ground 1 51. Scart output 2, right
33. Scart input 2 in, right 52. Analog Shield Ground 3
34. Scart input 2 in, left 53. Not connected
35. Analog Shield Ground 2 54. Not connected
36. Scart input 3 in, right 55. Not connected
37. Scart input 3 in, left 56. Analog output Channel 1, left
38. Analog Shield Ground 4 57. Analog output Channel 1, right
39. Not connected 58. Reference ground 2 high voltage part
40. Not connected 59. Analog output Channel 2, left
41. Not connected 60. Analog output Channel 2, right
42. Analog reference voltage high voltage part 61. ower-on-reset
43. Analog ground 62. Not connected
44. Volume capacitor Channel1 63. Not connected
45. Analog power supply 8.0 V 64. I2S2-data output
46. Volume capacitor Channel 2 65. I2S2-data input
47. Scart output 1, left 66. Digital ground
48. Scart output 1, right 67. Digital power supply +5 V
49. Reference ground 1 high voltage part 68. Not connected
EADP ONE OUTPUT
TDA1308
The TDA1308 is an integrated class AB stereo headphone driver. It gets its input from two analog audio outputs (DACA_L
and DACA_R) of MS 3410D. The gain of the output is adjustable by the feedback resistor between the inputs and outputs.
Features
nWide temperature range
nNo switch ON/OFF clicks
nExcellent power supply ripple rejection
nLow power consumption
nShort-circuit resistant
nHigh performance - high signal-to-noise ratio
- high slew rate
- low distortion
nLarge output voltage swing
Pinning
1. Output A (Voltage swing) : Min : 0.75V, Max : 4.25V
2. Inverting input A : Vo(clip) : Min : 1400mVrms
3. Non-inverting input A : 2.5V
4. Ground
5. Non-inverting input B : 2.5V
6. Inverting input B : Vo(clip) : Min : 1400mVrms
7. Output B (Voltage swing) : Min : 0.75V, Max : 4.25V
8. ositive supply : 5V, Min : 3.0V, Max : 7.0V
AUDIO OUTPUT
TDA7265
The TDA7265 is a 25W+25W stereo sound amplifier with mute/stand-by facility. ST A control signal coming from microcontroller
(when it is at high level) activates the mute function. IC is muted when mute port is at low level. Two stereo audio signals
coming from audio module is injected to the inputs of the IC and a power of 12Wrms (10%) is obtained. An external pop-
noise circuitry pulls AF inputs of the IC in order to eliminate pop noise when TV is turned on or off via mains supply
connection. It is possible to adjust the gain of the amplifiers by feedback external resistors.
Features
nWide supply voltage range (up to 50V ABS Max.)
nSplit supply
nHigh output power: 25+25 W @ TDA = 10%, RL = 8ohm, VS = ±20V
nNo pop at turn-on / off
nMute (pop free)
nStand-By feature (low IQ)
nFew external components
nThermal overload protection
nAdjustable gain via an external resistor

8
Pinning
1. Output (1)
2. +Vs
3. Output (2)
4. Mute / St-By
5. -Vs
6. Input (2)
7. Ground
8. Input (1)
VIDEO INPUT AND OUTPUT SOURCE SWITC ING
TEA6415C
Video switching is performed by the I2C controlled IC TEA6415C with a gain of 0dB. Inputs to the video switch are IF_CVBS,
three SCART video signals, front-AV video signal, SVHS luma signal, and one of SC1_R or SVHS_C. Outputs of the video
switch are three SCART video signals (SC1_OUT_V and SC3_OUT_V are the same), one video output for the I module,
Chroma signal (C), and luma (Y) or CVBS signal.
Features
n20 MHz Bandwith
nCascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
n8 inputs (CVBS, RGB, Mac, CHROMA, )
n6 Outputs
nossibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge
nBus controlled
n6.5dB gain between any input and output
n-55dB crosstaljk at 5MHz
nFully ESD protected
Pinning
1. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
2. Data : Low level : -0.3V Max : 1.5V,
High level : 3.0V Max : Vcc+0.5V
3. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
4. Clock : Low level : -0.3V Max : 1.5V,
High level : 3.0V Max : Vcc+0.5V
5. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
6. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
7. rog
8. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
9. Vcc : 12V
10. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
11. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
14. Output : 5.5Vpp, Min : 4.5Vpp
15. Output : 5.5Vpp, Min : 4.5Vpp
16. Output : 5.5Vpp, Min : 4.5Vpp
17. Output : 5.5Vpp, Min : 4.5Vpp
18. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
VIDEO OUTPUT AMPLIFIER STAGE
TDA6111Q
The TDA6111Q is a video output amplifier with 16Mhz bandwidth. It has a high slew rate. Automatic black-current stabilisation
is possible by black-current measurement output. It has two cathode outputs: one for DC currents and one for transient
currents. A feedback output is separated from the cathode outputs. An internal protection exists against positive appearing
cathode-ray-tube flashover discharges with ESD protection.
Features
nHigh bandwidth and slew rate
nBlack-current measurement output for Automatic Black-current Stabilisation (ABS)
nTwo cathode outputs; one for DC currents, and one for transient currents
nA feedback output separated from the cathode outputs
nInternal protection against positive appearing cathode-ray Tube (CRT) flashover discharges
nESD protection
nSimple application with a variety of colour decoders
nDifferential input with a designed maximum common mode input capacitance of 3pF, a maximum differential
mode input capacitance of 0.5 pF and a differential input voltage temperature drift of 50 uV/K
nDefined switch-off behaviour.

9
Pinning
1. Non-inverting voltage input
2. Supply voltage LOW
3. Inverting voltage input
4. Ground, substrate
5. Black current measurement output
6. Supply voltage HIGH
7. Cathode transient voltage output
8. Cathode CD voltage output
9. Feedback voltage output
VERTICAL OUTPUT STAGE
TDA9379FA
The IC TDA9379FA is the vertical deflection booster circuit. Two supply voltages, +12V and 12V are needed to scan the
inputs VERT+ and VERT-, respectively. And a third supply voltage, +45V for the flyback limiting are needed. The vertical
deflection coil is connected in series between the output and feedback to the input.
Features
n ower Amplifier
n Thermal rotection
n Output Current up to 2.6App
n Flyback Voltage up to 90V
n External Flyback Supply
Pinning
1. Inverting Input
2. Supply Voltage
3. Flyback Supply
4. GND or Negative Supply
5. Output
6. Output Stage Supply
7. Non-inverting Input
MICROTEXT CONTROLLER
SDA30C264
The SDA30C264 is the microcontroller used with the Megatext IC. Its architecture and instruction set are based upon
that of the 8051 microcomputer. Like the 8051 it has many features which increase programming ease; extended internal
data memory-space, variable manipulation in internal data memory, free stack location in data RAM, 4 register banks,
special function registers, memory mapped I/O, individually addressable bits, and a Boolean processor which gives the
programmer the ability to improve the power of the software development. The IC produces the following input or output
control signals; AGC_CON, MODE_SW, L / L, I _MODS, I _SEL, ON/OFF (stand-by), SC1..3_IN_AV (pin 8
information from 3 SCARTs), AFC, MUTE (to mute audio output IC), I2CEN.
The SDA30C26x family, a derivative of the SAB C501, is a member of family of single-chip computers, in which the
emphasis is no longer placed on purely numeric computational performance, but on application-specific controller
functions.
Architecture and instruction set are based upon that of the 8051 microcomputer. Like the 8051 has many features which
increase programming ease; extended internal data memory-space, variable manipulation in internal data memory, free
stack location in data RAM, 4 register banks, special function registers, memory mapped I/O, individually addressable
bits and a Boolean processor give the programmer the ability to improve the power of software development. Numerical
problems can be processed with binary as well as with BCD-arithmetic. The many bit handling instructions also
contribute to the computers efficiency as a controller, Extended memory is controlled by an 8-bit data and a (16+3)-bit
address bus without any additional devices such as latches or logic elements, even when all 512K of the program
address space is used. All this leads, in suitable applications, to a reduction in the peripheral hardware and to a
simplification of the software and thus to reduced development and component costs. The controller, specially developed
for entertainment electronic applications, can also be recommended where both lowest component costs and a large
production volume are prime requirements.
The SDA 30C36x family members contain a 1024 + 256-byte or a 2048 + 256-byte data memory (XRAM + RAM), two
independent 16-bit timers /-counters and a seven-source, four-priority-level, nested interrupt structure, on-chip oscillator
and clock circuits. The 30 digital I/O-lines include four 8-bit ports ( 1 and 3 contain I/O-lines with multifunction options)
and one 2-bit port. One or two serial interfaces are included, one behaves like the 8051 UART, the other is a I²C Bus
interface (SDA 30C264 only)
The second multifunction port consists of port 1, which alternatively can be used as up to eight independent pulse width
modulated output channels ( WM). Controlled via special function registers, the WM-circuitry provides flexibility in time
resolution and system configuration.
Specially the realisation of D/A-outputs using pulse width modulation will be a cost saving advantage in analog
applications.