Teac EU-34T User manual

TECHNICAL BULLETIN 10th Sep 1999
Page 1of 1
MODEL: EU-34T (AK20 CHASSIS)
PROBLEM: “White Dot Noise” pattern visible on low RF signal input.
File: EU-34T (Whitedot).doc / EU-34T (Whitedot).pdf
White dot noise pattern occurs when signal RF input is too low. This modification will improve the signal/noise
vastly.
Instructions:
1. Remove C820 (Ceramic Cap 270pF 1KV)
2. Insert (Ceramic Cap 470pF 1KV) into location C820
3. Add a 0.22nF 630V capacitor in parallel with D806.
Regards,
Fabian Lubanovic
TEAC Australia Pty Ltd.

1
11AK20 CHASSIS CIRCUIT DESCRIPTION
1. GENERAL INFORMATION :
This document provides detailed information about the fully I2C controlled Television Chassis named 11AK20.
11AK20 is based on the bus controlled circuits in which all the filters, traps and delay lines have been integrated.
Therefore the numbers of external components are reduced and the user, service and factory adjustments are made
through I2C BUS control.
This chassis has been designed mainly for the 90°, 14 and 15 picture tubes.
This chassis has a SMPS circuitry which has been designed to get low stand-by power consumption
(less than 3W) as an option. On the other hand, it also has wide range (90-270V 50/60 Hz) mains as an option.
The chassis covers almost all the existing worldwide transmission and colour standards as PAL B/G/I/M/N,
SECAM B/G/D/K/K/L/L and NTSC M (3.58), NTSC (4.43) using same Main Printed Circuit Board by means of
optional components and settings. Tuning system is Voltage Synthesized for all systems Except NTSC M and
PAL M/N applications but it is Frequency Synthesized for NTSC M and PAL M/N applications.
Furthermore, chassis has also European Wide-range teletext solution as an option. This solution supports all
the European teletext standards optionally as 1 page normal, fast and top text modes.
The chassis has Euro AV Plug (Scart Socket) for Peritel and SVHS connections. The pictures in 16 - 9 format can
be displayed via this Peritel connection. Other optional external connections are front AV input RCA jacks, back AV
output RCA jacks and Headphone jack.
The software has been developed with a menu driven user interface supporting all possible chassis versions
with a storage capacity of 100 programs.
2. IF STAGE :
The inputs for IF stage are IF inputs from Tuner to produce front-end Video and Audio, Video and Audio from
Scart or front AV RCA jack to be able to select the internal or external video and audio according to the control
signals which comes from microcontroller and STV 2118. Then, the resultant video and audio signals are sent to
video processing stage and audio output stage, respectively. Furthermore, front-end video and audio signals are sent
to scart and or back AV RCA jacks. This part also produces some control signals for tuner and microcontroller.
This stage was designed for processing positive (optional) and negative modulated mono and one scart
applications.
STV 8223 is the IF IC that is used in only negative modulation. There is an alignment which is the VCO
adjustment (VL101). The procedure of alignment can be described briefly as follows :
The IF signal is applied to the IF inputs in accordance with the standards (for B/G 38.9MHz) at pin # 1 and 2 of
SAW filter (Z101).
 Adjust the VL101 until getting 2.5 V
dc
at pin # 9 of uC (IC501).
This stage is also used for negative and positive modulated, mono applications. STV 8224 (negative and positive
modulation and FM sound) (IC 101) and STV 8225 (AM sound) (IC102) are the IF ICs.
There are two alignments in this case, which are the VCO adjustment (VL101) for B/G - L standards and VC101 for
L standard. The procedure of the alignments can be described briefly as follows :
The system is Switched to B/G standard reception,
 The IF signal is applied to the IF inputs in accordance with the standards (for B/G 38.9MHz) at pin # 1 and 2 of
SAW Filter Z101.
 Adjust the VL101 until getting 2.5 V
dc
at pin # 9 of uC.
 The system is Switched to L standard reception,
 The IF signal is applied to the IF inputs in accordance with the standards (for L 33.9MHz) at pin # 1 and 2 of
SAW Filter Z101.
 Adjust the VC101 until getting 2.5 V
dc
at pin # 9 of uC.
2.1 Video and Sound IF System & Switch IC STV8223:
STV 8223 is a picture and sound IF processor for negative application. The architecture of the video and sound
demodulator, which are both based on PLL structure, allows a very good linearity of the Intermediate Frequency
Response and an application with very few external components and adjustments.
The volume on the audio signal is controlled through a DC level (pin # 13) which is provided from
STV 2112/2116/2118 where all the I2C decoding is realized.
STV 8223 also provides the audio and video switches for scart - AV applications.
The IF inputs at pins # 19 and # 20 are driven by Tuner via Saw filter (Z101). The baseband signal produced from
these IF inputs appears at pin # 3. This signal is used to produce sound trapped video signal and intercarrier sound signal.
For multi-standard models, a switched trap circuitry is used (Q103, Q104, Q105). This internal video signal is fed to
pin # 10 of this IC for internal-external (coming from scart) video switching and to the base of the buffer transistor Q102
for the video output of the scart connector. The intercarrier signal used for reproducing sound, passes through the
band pass filter Z103 with center frequency 5.5MHz for B/G standard or Z104 for I (6.0MHz) or Z105 for D/K (6.5MHz)
or Z106 for M/N (4.5MHz) in according to selected system by intercarrier signal switching circuitry (D106, D107,
D108, D109, D110) and resultant signal is applied to the pin #8 of the IC which is the input of limiter and SIF PLL stage.

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The switch control signal is supplied by microcontroller. The limiter and SIF PLL output pin # 15 which is connected to
the deemphasis capacitor drives audio out of the scart connector and AV jack. The external inputs of IC, which are pin
# 12 for video and pin # 16 for audio, are connected to the related scart connector inputs or AV RCA jack inputs.
The internal-external signal selection for monitoring is made by control voltage at pin # 8 produced by STV 2118.
The selected video at pin # 11 drives video processing stage. On the other hand, the selected audio is processed in
volume control stage in according with DC control voltage at pin # 13 and then, it is sent from pin # 14 to sound
output stage.
The IF block produces control signals, which are AGC for tuner at pin # 23 in according to voltage of pin
# 24 controlled by microcontroller pin # 2.
2.2 Multi-Standard Video and Sound IF System & Switch IC STV 8224 and AM SIF IC STV 8225 :
STV 8224 is a picture and sound IF processor for negative and positive applications. The architecture of the
video and sound demodulator, which are both based on PLL structure, allows a very good linearity of the Intermediate
Frequency Response and an application with very few external components and adjustments.
The volume on the audio signal is controlled through a DC level (pin #13) which is provided from
STV 2112/2116/2118 where all the I2C decoding is realized.
STV 8224 also provides the audio and video switches with STV 8225 for one scart applications.
The IF inputs at pins # 19 and # 20 are driven by Tuner via SAW filter (Z101) which is K6256 for B/G - L/L
applications. This saw filter is switchable according to the control signals produced by microcontroller.
The baseband signal at pin # 3 is produced from these IF inputs according to the control signal at pin # 4.
This control signal comes from STV 2118 Multi-Switch Output according to the selected system standard.
The baseband signal is used to produce sound trapped video signal and on the other hand to produce intercarrier
sound signal for B/G standard. This internal video signal is fed to pin # 10 of this IC for internal-external
(coming from scart) video switching and to the base of the buffer transistor Q102 for the video output of the scart
connector. For the internal and external video switching, external video enters from pin #12, and then, selected video
is sent from pin # 11 to video processing part.
The intercarrier signal used for reproducing sound, passes through the band pass filter Z103 with center frequency
5.5MHz for B/G standard and resultant signal is applied to the pin # 8 of the IC STV 8224 which is the input of limiter
and SIF PLL stage. The limiter and SIF PLL output pin # 15 which is connected to the deemphasis capacitor drives
pin # 5 of the IC STV 8225 as FM Sound Input in order to be able to select the appropriate (FM or AM) audio signal
for producing audio out of the scart connector. The selected signal at pin # 9 of STV8225 drives external audio
output connections. On the other hand, the audio switch in STV 8224 is used to select the internal FM signal or the output
of STV 8225 (pin # 7), which selects the internal AM signal or External audio signal (at pin # 11) coming from scart socket.
The selected audio is processed in volume control stage in according with DC control voltage at pin # 13 and then, it is sent
from pin # 14 to sound output stage. The IF signal is filtered at Z102 saw filter which is switchable according to the
control signals produced by microcontroller for L or L mode. Output of SAW is connected to pin # 1 and 14 of SIF IC
STV 8225(IC 102) for AM sound producing. The audio switches in STV 8225 selects the signals according to DC voltage
at # 10 of STV 8225 .
The IF block produces control signals, which are AGC for tuner at pin # 23 in according to voltage of pin # 24
controlled by microcontroller and AFC for microcontroller at pin # 2.
There are two main switching circuits. First one is the VCO Frequency Switching circuit and the second one is
the Saw Filter Switching circuit which covers both Video and Sound saw filters.
The control voltage for VCO switching circuitry is the L/L signal produced by microcontroller. The logic of this signal,
which is defined by MAC-15, is as given in Table 2.1.
Table 2.1 The Logic of the L/L Switching Voltage (based on MAC-15)
Selected Mode L/L Switching Voltage Adjusted Frequency
Modes other than L HIGH 38.9 MHz
L LOW 33.9 MHz
This control voltage is applied to R121. When this voltage is LOW, diode D105 is ON and VC101, C129 and
C130 are connected in parallel to the reference tank circuit VL101. On the other hand, This circuit is disconnected
when L/L voltage is HIGH since D105 is OFF.
In according to selected system configuration, it must be used multistandard switched type SAW filters.
For this reason an optional circuitry is applied this stage by D101, D102, (and if using L/L, D103 ,D104 for SIF SAW Z102).
3. SIGNAL PROCESSING PART :
This part processes video coming from IF part, RGB coming from Scart, Teletext and Controller in order to
drive Horizontal and Vertical deflection stages and CRT baseboard and to produce some control voltages by means of
Bus-controlled PAL-SECAM-NTSC TV Processor IC, STV 2112/2116/2118 and 64msec Delay Line IC, STV2180.
The detailed functional descriptions of these ICs are given in the following subsections.

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3.1 Bus-controlled Multi-Standard TV Processor IC, STV 2118 :
The STV 2118 (IC 401) is a fully bus controlled IC for TV Luma, Chroma and Deflection processing. In order to
make the alignments by microcontroller via I2C, the required data are transferred from microcontroller into the
related registers of STV 2118. The main input for this IC are as follws :
I
2
C Inputs from microcontrolle
 Y/CVBS Input from IF Part, external CVBS coming from scart or front AV RCA jack, external RGB and Fast
Blank signals coming from Scart, R input is also used for Chroma input in SVHS Mode
 OSD and TELETEXT RGB and Fast Blank signals coming form both microcontroller and teletext processor IC
 BCI (Black Current Information) coming from CRT Baseboard
 BCL (Beam Current Limiting) information from Horizontal Output Stage
 Line Flyback Sample coming from Horizontal Output Stage
 Delayed R-Y and B-Y signals coming from Delay Line IC STV 2180
Detailed Features and the internal block diagram of the IC STV 2118 are given in following subsections:
3.1.1 Deflection Circuit :
The deflection part includes a fully integrated sync-separator locked to a 500 kHz VCO with external resonator
(X401), two phase locked loops for horizontal deflection, vertical count down with 50 Hz and 60 Hz operation for field
frequency.
Vertical output pulse is 10.5 lines long at pin # 35, furthermore horizontal output pulse is 28 msec on open
collector pin # 36.
The horizontal output is at high level when Vcc increases from 0V to 6.8V. On shutting down, the horizontal pulse
disabled when Vcc is below 6.2V.
When vertical pulses are disappeared, horizontal output is disabled by microcontroller for keeping CRT phosphor.
Line position adjustment is controlled by bus using related service mode.
Bus controlled output voltage at pin # 34 is used to adjust vertical amplitude at vertical output stage via R705,
R706 and R707.
Bus controlled vertical position information is produced from high level of the vertical pulse pin # 35 and this
signal is used to adjust vertical positioning at vertical output stage via R701, R703, R704, C701, D701 and Q701.
The sandcastle signal at pin # 37 is used to control the external baseband chroma delay line
(STV 2180 -IC 402- pin # 6).
3.1.2 Filters :
All filters (integrated trap filter, integrated chroma bandpass, integrated bell filter for SECAM, integrated delay line)
are tuned with a reference PLL.
The PLL consists of a lowpass filter, a phase comparator, a loop filter (an external capacitor C423 on pin # 8).
The reference signal is the continuous carrier wave from the VCO (4.43 MHz or 3.58 MHz). The PLL will adjust the
center frequency of the lowpass so that it will be equal to the reference signal. The tuning voltage of the PLL
(memorized on pin # 8) will adjust all other filters.
The cloche filter is fine-tuned with a second PLL operating during frame retrace. Tuning voltage is memorized on an
external capacitor C424 at pin # 9.
3.1.3 Video Circuit :
Video part includes two RGB inputs, automatic cut-off control, DC cut-off adjustment, RGB gain adjustments,
beam current limiting. Furthermore, user video settings (contrast, saturation, brightness and sharpness controls)
are performed by this block. RGB output pins are as follows: R output is pin # 29, G output is pin # 28 and B output
is pin # 27.
The beam current information is fed to pin # 31 via R411 and D403. This control voltage will act on contrast first,
then the brightness will be decreased when contrast attenuation reaches -5dB.
Automatic cut-off function is realized according to the BCI information at pin # 30. Sequential cut-off current
measurements are made during three lines after frame blanking signal.
3.1.4 Chroma Circuit :
The chroma part includes PAL, SECAM, NTSC demodulator. An external base band delay line (STV 2180 IC402)
is used in this concept. R-Y and B-Y outputs of STV 2118 (pin # 40 and pin # 41) are sent to STV 2180 to get 64msec
delayed signals.
The PAL, SECAM or NTSC standard selection is made by automatic standard identification.
Three Xtals for PAL M (X404), PAL N (X405) and NTSC M (X403) and their switching circuitry (Q401, Q402, Q403,
Q404, D401, D402) are used in PAL M/N and NTSC M models only.
SVHS selection is made by microcontroller via bus control.

4
3.1.5 Other Functions :
Volume Control and Mute output is pin # 10. The voltage range for volume control is 0.5V to 5V, whereas below
0.1V is used for muting. The output of this pin is controlled by microcontroller via bus and the value is saved in related
register of the STV 2118.
The selection of the IF standard (Positive or Negative Vision Modulation) and the TV / SCART(AV) mode is
controlled by bus. The selection is converting in four voltages which are used to control the IF ICs STV 8224 and
STV 8225 on pin # 11. Related voltage levels and their situations are tabulated as follows:
Table 3.1 Related voltage levels and their situations for pin # 11 of STV 2118.
SITUATION VOLTAGE RANGE (V
11
)
STANDARD SOURCE MIN. MAX.
NEGATIVE TV 0 0.7
POSITIVE TV 2.9 3.8
POSITIVE SCART 5.2 6.1
NEGATIVE SCART 7.88 9
3.2 Base Band Chroma Delay Line IC STV 2180 :
The STV 2180 is an integrated base band chroma delay line with one line delay, which has been designed to
match chroma decoders with color difference signal outputs (R-Y) and (B-Y). This IC has dual switched capacitors
delay line with 3 MHz clock and integrated filters to suppress the residual clock components. It designed to work in
conjunction with STV 2112/2116/2118 and it allows an adjustment free application.
The inputs for this IC are as follows :
 (R-Y) at pin # 2 coming from STV 2118
 (B-Y) at pin # 14 coming from STV 2118
 Sandcastle Pulse at pin # 6 coming from STV 2118
On the other hand, outputs of this IC are as follows :
 Delayed (R-Y) at pin # 3
 Delayed (B-Y) at pin # 4
4. HORIZONTAL OUTPUT AND EHT STAGE :
The horizontal pulses, from pin #36 of IC401, are connected to base of driver transistor Q601 through Q601,
R603, C601. The driver circuitry (Q601, R604, C602, L602, R608) drives the horizontal deflection output transistor
BU808DFI (Q602). TR601 is the EHT (Extra High Tension) transformer. The 112V supply voltage for the stage is
connected at # 2. TR601 transformer generates EHT, focus and G2 voltages, required by picture tube. Furthermore,
the 200V supply for video output, 26V supply for vertical output and heater drive current are derived from this
transformer. The beam current information from pin #8 of TR601 is used for reducing the contrast at excessive long
term average beam current and compensation voltage to vertical output to stabilize picture height. The flyback signal
sample (AC coupled and clipped by R606, C614, C604, D602, D601) is used to generate sandcastle pulse for video
processor IC and horizontal pulse (Q603) required by uC.
5. VERTICAL OUTPUT STAGE (TDA 1771)
The TDA1771 (IC701) vertical deflection integrated circuit is used for output of vertical stage. Trigger pulses from
STV2118 feeds to pin # 3 of TDA1771. The signal produced by built in ramp generator synchronizes input trigger pulses.
Amplitude is adjusted by an independent input pin (# 4). Built in voltage generator output, feedback information by pin # 8,
internal sawtooth signal and amplitude information are applied to output OP-AMP. This output stage has also thermal
protection and flyback generator for reliability and effectivity. Applied pulse from STV2118, contains vertical position
information as maximum dc level of signal and is extracted by Q701 and fed as a part of feedback to output stage.
Vertical shift DC supply is obtained via R716. The amplitude control is supplied by STV2118. Vertical deflection output
stage is supplied by +26V output of FBT and D605, C603 circuitry.
6. SOUND OUTPUT STAGE (TDA2822M) :
TDA2822M is used as the AF output amplifier. It is supplied by +12V coming from a separate winding in the SMPS
transformer (T802). Pin #14 of the STV8223 ( or STV 8224) is AC coupled to the input pin #7 of the TDA2822M via a
resistor divider. Maximum audio output power at 10% THD is 1.5W. Q301 for start up muting and Q302 for muting by uC
are used, and an alarm signal by uC is fed to this input.

5
7. POWER SUPPLY (SMPS) :
The DC voltage sources required at various stages of the chassis are provided by an SMPS controlled by the
IC801 (MC44603 for common models and MC44604 for low power consumption on stand by mode models).
This IC is designed for driving, controlling and protecting the switching MOSFET transistor of SMPS (Q801).
This supply has three outputs; one 112V output which is used for horizontal output and 33V generation needed by
tuner section, one 16V output for all small signal sections an uC and one for audio output section. This chassis may
be used in 90 - 270 volt with appropriate optional circuitry and components. The uC which is supplied by a source
designed regulator with zener diode (D814) controls stand by mode by switching Q803 (for 44604 application Q806).
8. uC (MICROCONTROLLER) :
The microcontroller hardware that is member of the ST6 family has a TV receiver control software with menu
control. It controls the chassis through IIC bus, PWM outputs and I/O ports. Dominant features of controller are control
of optional teletext, outputs for OSD, IR control signal receiving, and internal EEPROM.
The controller has IIC communication port at # 40 , # 41 and OSD driver (R,G,B,FBl) at # 22, # 23, # 24, # 25.
PWM control outputs are tuning # 34; vertical linearity adjustment # 1; AGC adjustment # 2. Other control outputs are
Muting - video ident # 3; led driver # 4; system switches # 5, # 6, # 8, # 19, # 20, # 36; tuner switches # 18, # 19 and
inputs are AFC information from IF # 9; keyboard # 10, # 11, # 13, # 14; scart mode ident (4/3-16-9) # 38, # 39;
horizontal sync # 26; vertical # 27; infrared # 35 and reset # 33.
The uC starts system according to option diodes configuration (D501, D503, D505, D506, D508).
The controller has also a software which is able to control some service adjustments: R,G,B gain; R,G cut off;
vertical position; vertical linearity; horizontal position; vertical amplitude; AGC; language selection for teletext.
For enter to service mode followed procedure must be act within four seconds:
1- Press volume down button on the keyboard;
2- Press prog button on the R/C hand set;
3- Press - - button on the R/C hand set;
4- Press TV  button on the R/C hand set;
Parameters can be sellected by program up and down, parameter adjustments can be done by volume up and
down buttons. Memorizing the adjusted parameters can be done by pressing red button. For exit from service mode
Press  TV  button.
9. TELETEXT :
The video signal coming from IF stage is fed to Data Slicer IC001. Then, there are two possibilities for decoding part;
CF70095 or CF70195 for 1-Page simple text applications and CF7020X family for fastext and toptext applications.
Finally, R, G, B and FBL signals are sent to the related inputs of STV2118.
The alignment procedure for CF70095 or CF70195 application is as following:
1- Apply a video with teletext transmission and select for teletext.
2- Adjust the coil (VL001) for the voltage at pin # 28 2.5V.
10. CRT BASE-BOARD :
When RGB signals enter the input of the video amplifier stage (CRT base-board), they are amplified by means
of three symmetrical video amplifier stages. For this purpose three 2SC2482 high voltage, video output transistors
are used. So, high gain-bandwidth product is achieved. Furthermore black level changes at the output amplifiers
caused by temperature or component agings are compensated by means of a closed loop control system.
For this reason the cathode current information (ICAT) is sent to STV2118.

6
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MC44603
Advance Information
Mixed Frequency Mode GreenLine PWM Controller:
Fixed Frequency, Variable Frequency, Standby Mode
GENERAL DISCRIPTION
The MC44603 is an enhanced high performance controller that is specifically designed for off-line and dc-to-dc converter
applicitions. This device has the unique ability of automatically changing operating modes if the converter
output is overloaded, unloaded, or shorted, offering the designer additional protection for increased system reliability.
The MC44603 has several distinguishing features when compared to conventional SMPS controllers.
These features consist of a foldback facility for overload protection, a standby mode when the converter output is
slightly loaded, a demagnetization detection for reduced switching stresses on transistor and diodes, and a high current
totem pole output ideally suited for driving a power MOSFET. It can also be used for driving bipolar transistor in low
power converters (<150 W). It is optimized to operate in continuous mode. Its advanced design allows use in current
mode or voltage mode control applications.
FEATURES :
Current or Voltage Mode Controller
nOperation up to 250 kHz Output Switching Frequency
nInherent Feed Forward Compensation
nLatching PWM for Cycle-by-Cycle Current Limiting
nOscillator with Precise Frequency Control
High Flexibility
nExternally Programmable Reference Current
nSecondary or Primary Sensing
nSynchronization Facility
nHigh Current Totem Pole Output
nUndervoltage Lockout with Hysteresis
Safety/Protection Features
nOvervoltage Protection Against Open Current and Open Voltage Loop
nProtection Against Short Circuit on Oscillator Pin
nFully Programmable Foldback
nSoft-Start Feature
nAccurate Maximum Duty Cycle Setting
nDemagnetization (Zero Currrent Detection) Protection
nInternally Trimmed Reference
GreenLine Controller: Low Power Consumption in Standby Mode
nLow Startup and Operating Current
nFully Programmable Standby Mode
nControlled Frequency Reduction in Standby Mode
nLow dV/dT for Low EMI Radiations.
PINNING
1- VCC This pin is the positive supply of the IC. The operating voltage range after startup is 9.0 to 14.5V.
2- VC The output high state (VOH) is set by the voltage applied to this pin.
With a separate connection to the power source, it can reduce the efffects of switching noise on the control circuitry.
3- OUTPUT Peak currents up to 750mA can be sourced or sunk, suitable for driving either MOSFET or
Bipolar transistör. This output pin must be shunted by a Schottky diode, 1N5819 or equivalent.
4- GND The ground pin is a single return, typically connected back to the power source;it is usedas control and power ground.
5- Foldback Input The foldback function provides overload protection. Feeding the foldback input with aportion of
the VCC voltage (1.0V max) establishes on the system control loop a foldback characteristic
allowing a smoother startup and sharper overload protection. Above 1.0V foldback input is inactive.
6- Overvoltage Protection When the overvoltage protection pin receives a voltage greater than 17V, the device is
disabled and requires a complete restart sequence. The overvoltage level is programmable.
7- Current Sense Input A voltage proportional to the current flowing in to the power switch is connected to this input.
The PWM latch uses this information to terminate the conduction of the output buffer when working in a corrent mode
of operation. A maximum level of 1.0V allows either current or voltage mode of operation.
8- Demagnetization A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an
Detection indication of the magnetization state of the flyback transformer. A zero voltage detection corresponds to complete
core saturation. The demagnetization detection ensures a discontinuous mode of opertion.
This function can be inhibited by connecting Pin 8 to Gnd.
9- Synchronization Input The synchronization input pin can be activated with either a negative pulse going from a level between 0.7V and 3.7V
to Gnd or a positive pulse going from a level between 0.7 and 3.7V up to a level higher than 3.7V. The oscillator runs
free when Pin 9 is connected to Gnd.
10- CT The normal mode oscillator frequency is programmed by the capacitor CT choice together with the Rref resistance
value. CT, connected between Pin 10 and Gnd, generates the oscillator sawtooth.
11- Soft-Start/Dmax A capacitor, resistor or a voltage source connected to this pin limits The switching duty-cycle.
/Voltage-Mode This pin can be used as a voltage mode control input. By connecting Pin11 to Ground,
the MC44603 can be shut down.
12- RP Standby A voltage level applied to the RP Standby pin determines the output power level at which the oscillator will turn into the
reduced frequency mode of operation (i.e. standby mode).
An internal hysteresis comparator allows to return in the normal mode at a higher output power level.
13- E/A Out The error amplifier output is made avaliable for loop compensation.
14- Voltage Feedback This is the inverting input of the Error Amplifier. It can be connected to the switching power supply output through
an optical (or other) feedback loop.
15- RF Standby The reduced frequency or standby frequency programming is made by the RF Standby resistance choice.
16- Rref Rref sets the internal reference current. The internal reference current ranges from 100µA to 500 µA.
This requires that 5.0kW < Rref < 25 kW.

8
ST 6385
8 BIT HCMOS MCUs FOR
TV VOLTAGE SYNTHESIS WITH OSD
GENERAL DESCIRIPTION
The ST6385,86,87,88 microcontrollers are member of the 8-bit HCMOS ST638X family, a series of devices
specially oriented to TV applications. Different pin-out and peripheral configýration are avaiable to give the maximum
aplication and cost flexibility. All ST638X members are based on a building block appoach: a common coreis
surrounded by a combination of on-chip peripherals (macrocells) avaiable from a standard library. These peribherals
are designed with the same Core technology providing full compatibility and short desing time. Many of these macrocells
are specially dedicated to TV applications. The macrocells of the ST638X family are : two Timer peripherals each
including an 8-bit counter with a 7 bit software programmable precaler (Timer), a digital hardware activated watchdog
function (DHWD), a 14-bit voltage synthesis tuning pripheral, a serial peripheral interface (SPI), up to six 6-bit PWM
D/A converters, an AFC A/D converter with 0.5V resolution, an on-screen display (OSD) with 15 characters per line,
128 characters (in two banks each of 64 chracaters). In addition the following memory resources are available:
program ROM (20K), data RAM (256 bytes),
EEPROM (384 bytes). Refer to pin configurations figures and to ST638X device summary (Table 1)
for the definition of ST638X family members and a summary of differences among the different types.
FEATURES
n8-bit Architecture
nHCMOS Technology
n8Mhz Clock
nUser Program ROM: 20140 bytes
nReserved Test ROM: 336 bytes
nData ROM: User selectable size
nData RAM: 256 bytes
nData EEPROM: 384 bytes
n42-Pin Shrink Dual in Line Plastic Package
nUp to 22 software programmable general purpose Inputs/Outputs,including 2 direct LED driving nOutputs
nTwo Timers each including an 8-bit counter with a 7-bit programable prescaler
nDigital Watchdog Fuction
nSerial Peripheral Interface (SP) supporting S-BUS/ I2C BUS and standart serial protocols
nUp to Six 6-Bit PWM D/A Converters
n62.5KHz Output Pin (ST6386,88 Only)
nAFC A/D converter with 0.5V resolution
nFive interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR INT.)
n14 bit counter for voltage synthesis tuning
nOn-chip clock oscillator
n5 Lines by 15 Characters On-Screen Diplay Generator with 128 Characters
nByte efficient instruction set
nBit test and jump instructions
nWait and Bit Manipulation insructions
nTrue LIFO 6-level stack
nAll ROM types are supported by pin-to-pin piggy-back versions.
nThe develeopment tool of the ST638X microcon-trollers consists of the ST638X-EMU emulation and
development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.
PINNING
1- DA0 Output, Open-Drain, 12V
2- DA1 Output, Open-Drain, 12V
3- DA2 Output, Open-Drain, 12V
4- DA3 Output, Open-Drain, 12V
5- DA4 Output, Open-Drain, 12V
6- DA5 Output, Open-Drain, 12V
7- 62.5KHz OUT Output, Open-Drain, 12V
8- AFC Input, High Impedance, 12V
9- VS Output, Push-Pull
10- R,G,B, BLANK Output, Push-Pull
11- HSYNC, VSYNC Input, Pull-up, Schmitt Trigger
12- OSDOSCIN Input , High Impedance
13- OSDOSCOUT Output, Push-Pull
14- TEST Input Pull-Down
15- OSCIN Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
16- OSCOUT Output, Push-Pull
17- RESET Input, Pull-up, Schmitt Trigger Input
18- PA0 I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input