Tektronix Dc 502 User manual

TEKTRONIX®

550

MHz

COUNTER

DC

502

INSTRUCTION

MANUAL

Tektronix,

Inc.

P.O.

Box

500

Beaverton,

Oregon

97005

Phone:

44-01 1

Cables:

Tektronix

070-1412-00

872

WARRANTY

All

TEKTRONIX

instruments

are

warranted

against

defective

materials

and

workmanship

for

one

year.

Any

questions

with

respect

to

the

warranty

should

be

taken

up

with

your

TEKTRONIX

Field

Engineer

or

representative.

All

requests

for

repairs

and

replacement

parts

should

be

directed

to

the

TEKTRONIX

Field

Offic

e

or

representative

in

your

area.

This

will

assure

you

the

fastest

possible

service.

Pleas

e i

nclude

the

l

nst

rument

Ty

pe

Number or Part

Number

and

Serial

Number

with

all

req

uests for

parts

or

services.

Specif

ications

and

price

change

privileges

reserved.

Copyright

©

1972

by

Tektronix,

Inc.,

Beaverton,

Oregon.

Printed

in

the

United

States

of

America.

All

rights

reserved.

Contents

of

this

publication

may

not

be

reproduced

in

any

form

without

permission

of

Tektronix,

Inc.

U.S.A.

and

foreign

TEKTRONIX

products

covered

by

U.S.

and

foreign

patents

and/or

patents

pending.

TEKTRONIX

is

a

registered

trademark

of

Tektronix,

Inc.

DC

502

TABLE

OF

CONTENTS

SECTION

1

OPERATING

INSTRUCTIONS

Page

Introduction

1-1

Description

1-1

Installation

1-1

Operational

Check

1-2

Display

Check

1-2

Frequency

Measurements

1-2

Totalizing

1-2

Using

the

Counter

1-3

DIRECT

INPUT

Attenuation

and

Trigger

Level

Adjustment

1-3

Signal

Connection

1-3

Measurement

Interval

and

Display

Time

Controls

1-3

Rear

Connector

I/

O

Assignments

1-4

Option

1

—

Precision

Time

Base

1-4

Specifications

1-4

SECTION

2

THEORY

OF

OPERATION

)

Input

Circuits

2-1

Time

Base

and

Control

Circuit

2-2

Counter

Circuits

2-3

Decode

and

Display

Multiplex

2-4

Power

Supplies

and

Input/Output

Lines

2-5

SECTION

3

SERVICE

INFORMATION

Symbols

&

Reference

Designators

3-1

Electrical

Parts

List

3-2

Controls

and

Connectors

Illustration

3-9

Adjustments

Illustration

3-9

Parts

Location

Grid

3-10

Block

Diagram

Counter

Time

Base

and

Control

Schematic

3-11

I

j

!

Counters

and

Display

Schematic

Mechanical

Parts

List

Fig.

1

Exploded

View

Accessories

&

Repackaging

3-14

)

;

®

)

DC

502

Section

1

—

DC

502

SECTION

1

OPERATING

INSTRUCTIONS

INTRODUCTION

Description

The

DC

502

550

MHz

Frequency

C unter

measures

frequencies

fr m

10

Hz

t

550

MHz

r

t talizes

events

t

10

7

at

a

maximum

rate

f

550

MHz.

The

DC

502

perates

in

a

TEKTRONIX

TM

500

P wer

M dule

nly.

Frequency

measurements

are

acc mplished

using

ne

f

tw

BNC

inputs

n

the

fr nt

panel.

The

DIRECT

INPUT

has

a

frequency

range

f

10

Hz

t

110

MHz

with

a

300

mV

peak-t -peak

sensitivity,

selectable

attenuat rs,

and

an

adjustable

trigger

level

range.

The

÷10

PRE-SCALE

INPUT

has

a

frequency

range

f

50

MHz

t

550

MHz

with

a

500

mV

peak-t -peak

sensitivity

and

a

50



input

impedance.

The

same

f ur

measurement

interval

times

are

selectable

f r

each

input.

Fr nt

panel

c ntr ls

reset

the

C unter

and

pr vide

Start/St p

c mmands

f r

the

manual

t talizing

m de

f

each

input.

Measurement

display

is

acc mplished

with

seven-segment

LED's

in

a

7-digit

read ut.

The

decimal

p int

is

aut matically

p siti ned

by

the

MEASUREMENT

INTERVAL

selected,

and

leading

zer s

(t

the

left

f

the

m st

significant

digit

r

the

decimal

p int)

are

blanked.

LED's

indicate

when

the

GATE

is

pen,

when

the

kHz

r

MHz

units

are

displayed,

and

when

OVERFLOW

ccurs.

Installation

The

DC

502

is

calibrated

and

ready

t

use

as

received.

Referring

t

Fig.

1-1,

install

the

DC

502

int

the

P wer

M dule

and

turn

n

the

p wer.

Fig.

1-1.

Plug-in

module

installation/removal.

1-1

@1

REV.

MAY

1974

Operating

Instructions

—

DC

502

OPERATIONAL

CHECK

Display

Check

Press

the

RESET

butt n

t

check

the

7

character

segments

f

each

digit;

the

numerical

display

sh uld

be

a

r w

f

eights.

T

check

the

decimal

p int

p siti n

and

the

units

indicat rs,

set

the

MEASUREMENT

INTERVAL

switch

as

f ll ws:

Switch

Position

.01

SEC

I

.1

SEC

1

_

(

DIRECT

1

SEC

/

.

I

INPUT

10

SEC

I

MANUAL

/

MANUAL

1

M0

10

SEC

I

.

I

PRE-

1

SEC

>

.1

SEC

SCALE

1

INPUT

.01

SEC

1

Numerical

Display

Units

.0000

MHz

.00000

MHz

.000

kHz

’

.0000

kHz

000

.000

kHz

.00000

MHz

.0000

MHz

.000

MHz

In

the

MANUAL

p siti n,

n

decimal

p int

will

be

displayed.

Press

the

START

butt n

and

check

that

the

GATE

indicat r

lights,

then

release

the

butt n

(STOP)

and

check

that

the

GATE

light

g es

ut.

T

check

the

OVERFLOW

indicat r,

set

the

MEASUREMENT

INTERVAL

switch

t

10

s

and

apply

15-

r

20-MHz

t

the

INPUT

c nnect r.

The

length

f

time

a

display

can

be

held

is

determined

by

the

DISPLAY

TIME

c ntr l,

and

will

be

discussed

in

the

paragraphs.

Then

turn

the

MEASUREMENT

INTERVAL

switch

t

the

p siti n

that

gives

the

desired

reading.

Generally,

use

the

sh rter

measurement

intervals

f r

high-frequency,

l w-

res luti n

measurements

and

the

l nger

intervals

f r

measurements

requiring

a

high

res luti n.

NOTE

The

OVERFLOW

indicator

can

be

lit

for

high-

resolution

measurements,

allowing

the

fre uency

to

be

indicated

to

0.1

Hz.

Refer

to

the

Specifications

at

the

end

of

this

section

for

resolution

and

accuracy

at

each

position

of

the

MEASUREMENT

INTERVAL

switch.

The

display

is

updated

at

a

rate

determined

by

the

DISPLAY

TIME

c ntr l.

Each

time

a

sample

f

the

input

signal

is

taken,

the

GATE

light

will

flash

and

the

new

reading

will

be

displayed.

T

change

the

display

time,

which

is

c ntinu usly

variable

fr m

ab ut

0.1

sec nd

t

10

sec nds,

r

t

h ld

a

display

indefinitely,

turn

the

DISPLAY

TIME

c ntr l.

÷10

Pre-Scale

Input.

The

DC

502

als

pr vides

a

pre



scaled,

AC-c upled

input

t

measure

the

average

frequency

f

signals

fr m

50

MHz

t

550

MHz.

This

input

has

a

sensitivity

f

500

mV,

peak-t -peak,

and

a

maximum

input

v ltage

limit

f

10

V,

peak-t -peak.

Signals

greater

than

10

V

may

damage

the

di des

f

the

input

circuit.

The

ATTEN

c ntr ls

d

n t

apply

t

this

input.

Frequency

Measurements

Direct

Input.

The

DC

502

pr vides

direct

measurement

f

the

average

frequency

f

signals

fr m

ab ut

10

Hz

t

110

MHz.

The

input

sensitivity

is

300

mV

peak-t -peak,

s

select

the

pr per

attenuati n

(X

1

,

X5,

X10,

r

X50)

f r

the

given

signal.

The

input

signa!

must

not

exceed

500

volts.

Apply

a

50

MHz

t

550

MHz

signal

f

at

least

500

mV

amplitude

t

the

÷10

PRE-SCALE

INPUT.

Set

the

MEASUREMENT

INTERVAL

switch

t

.01

SEC

and

bserve

the

read ut.

Leading

zer s

sh uld

be

blanked.

Select

a

MEASUREMENT

INTERVAL

which

gives

the

best

accuracy

and

res luti n.

As

with

the

DIRECT

INPUT,

sh rter

measurement

intervals

give

higher

frequency,

l wer

res luti n

measurements;

l nger

intervals

ffer

greater

res luti n,

especially

when

verfl w

is

empl yed.

Apply

a

signal

t

the

INPUT

c nnect r.

Set

the

MEASUREMENT

INTERVAL

switch

t

the

.01

SEC

p si



ti n

and

the

DISPLAY

TIME

c ntr l

fully

CCW.

Observe

the

numerical

read ut

display.

Adjust

the

TRIGGER

LEVEL

c ntr l

f r

a

stable

reading.

The

zer es

leading

the

m st

significant

digit

in

the

display

sh uld

be

blanked.

Totalizing

DIRECT

INPUT.

The

DC

502

will

c unt

and

display

the

accumulated

number

f

signals

(events)

applied

t

the

DIRECT

INPUT

c nnect r

up

t

the

register

capacity

f

9,999,999

during

the

time

interval

between

START/STOP

c mmands

fr m

the

fr nt-panel

pushbutt n.

Input

signal

rate

sh uld

n t

exceed

110

MHz.

®ï

1-2

REV.

MAY

1974

Operating

Instructions

—

DC

502

Set

the

MEASUREMENT

INTERVAL

switch

t

MANUAL,

apply

the

signal,

and

push

the

START

butt n.

The

GATE

indicat r

will

light

and

the

pr gressing

c unt

will

be

displayed.

Adjust

the

ATTEN

and

TRIGGER

LEVEL

c ntr ls

as

necessary

f r

a

steady

c unt.

T

st p

the

c unting,

release

the

START

butt n.

The

GATE

light

will

g

ut

and

the

displayed

c unt

will

be

held.

The

displayed

c unt

can

c ntinue

when

the

START

butt n

is

depressed

again.

The

c unter

can

be

cleared

t

zer

at

any

time

by

pressing

the

RESET

butt n

r

by

m ving

the

MEASUREMENT

INTERVAL

switch

t

an ther

p siti n.

4-10

PRE-SCALE

INPUT.

In

the

MANUAL

m de

this

input,

the

displayed

c unt

advances

ne

c unt

f r

every

ten

inc ming

events.

The

inc ming

events

must

have

transiti n

times

and

peri ds

suitable

f r

the

50



pre-scale

input

triggering

requirements.

USING

THE

COUNTER

DIRECT

INPUT

Attenuation

and

Trigger

Level

Adjustment

Signals

t

be

c unted

in

the

DIRECT

INPUT

channel

may

have

a

wide

variety

f

shapes

and

amplitudes,

many

f

which

are

unsuitable

t

drive

the

c unting

circuits.

Because

f

this,

the

signal

is

first

passed

thr ugh

an

attenuat r,

then

applied

t

a

signal-shaping

circuit

which

c nverts

it

t

rectangular

pulses

f

unif rm

amplitude.

This

circuit

includes

a

reference

level

adjustable

between

+

and

—

2

v lts

t

which

the

inc ming

signal

is

c mpared,

all wing

the

300-milliv lt

sensitivity

wind w

f

the

signal-shaping

circuit

t

be

adjusted

t

a

c nvenient

amplitude

n

the

inc ming

wavef rm

(see

Fig.

1-2).

Obtaining

a

steady,

reliable

reading

is

dependent

up n

the

pr per

selecti n

f

input

attenuati n

and

pr per

adjustment

f

the

TRIGGER

LEVEL

c ntr l.

Noise

Impulses

200-millivolt

Fig.

1-2.

Two

examples

of

triggering

circuit

output

showing

how

proper

adjustment

of

TRIGGER

LEVEL

control

can

avoid

an

erroneous

count.

Generally,

the

best

p int

n

a

wavef rm

f r

triggering

the

c unter

is

where

the

sl pe

is

steep

and

theref re

usually

free

f

n ise.

On

a

sine-wave

signal,

f r

example,

the

steepest

sl pe

ccurs

at

the

zer -cr ssing

p int.

N ise

pulses

r

ther

signal

c mp nents

f

sufficient

amplitude

t

pr duce

unwanted

trigger

pulses

will

cause

an

erratic

r

inc rrect

c unt.

Fig.

1-2

sh ws

the

TRIGGER

LEVEL

c ntr l

adjusted

t

av id

err r.

In

critical

measurement

applicati ns,

m nit r

the

inc ming

signal

with

a

test

scill sc pe.

Signal

Connection

C axial

cables

and

pr bes

ffer

very

c nvenient

means

f

c nnecting

the

signals

t

the

fr nt-panel

input

BNC

c nnect rs.

These

devices

are

shielded

t

prevent

pickup

f

electr static

interference

which

can

cause

err ne us

trig



gering

and

a

faulty

c unt.

F r

the

DIRECT

INPUT,

a

X10

pr be

n t

nly

reduces

the

size

f

the

signal,

but

als

presents

a

high

input

impedance

t

all w

the

circuit

under

test

t

perf rm

very

cl se

t

n rmal

perating

c nditi ns.

F r

the

4-10

PRE-SCALE

INPUT,

the

50



input

requires

careful

impedance

matching.

If

the

signal

must

be

atten



uated

t

av id

exceeding

the

maximum

input

limit

f

10

V,

use

50



attenuat r

pads

terminated

by

the

50



input

impedance

f

the

DC

502.

Measurement

Interval

and

Display

Time

Controls

The

MEASUREMENT

INTERVAL

switch

selects

the

time

interval

(als

called

gate

time)

during

which

the

DC

502

c unts.

The

internal

time-base

circuit

derives

gate

times

fr m

an

accurate

1-MHz

reference

signal

t

make

frequency

measurements.

These

gate

times

are

0.01

s,

0.1

s,

1

s,

r

10

s.

The

measurement

interval

selected

determines

the

measurement

range

and

res luti n.

Als ,

the

displayed

decimal

p int

is

p siti ned

c rrectly

and

the

c rrect

measurement

units

(MHz

r

kHz)

are

indicated

f r

the

c rresp nding

switch

p siti n.

The

DISPLAY

TIME

c ntr l

sets

the

length

f

time

a

measurement

can

be

held

in

the

c unter

and

displayed.

The

HOLD

detent

p siti n

all ws

a

measurement

t

be

held

indefinitely,

r

until

the

c unter

is

reset

t

zer

by

the

fr nt-panel

RESET

butt n.

1-3

Operating

Instructions

—

DC

502

Contact

28B

27A

27B

2 A

25A

25B

24B

23B

22B

20B

20A

21B

19A

19B

Assignment

Second

decimal

point

(D2)

output.

Internal

scan

clock

disable

input.

MHz

light

output.

Reset

input/output.

TS0

(Time

Slot

Zero)

output.

External

scan

clock

input.

Internal

scan

clock

(2

kHz)

output.

Overflow

output.

MSD

(Most

Significant

Digit)

output.

8

4

2

1

BCD

output,

serial

by

digit.

Data

good

output.

Fig.

1-3.

Input/Output

assignments

at

rear

connector.

Rear

Connector

I/O

Assignments

Input

and

utput

data

access

t

the

DC

502

is

available

at

the

rear

f

the

main

circuit

b ard.

Fig.

1-3

identifies

the

c ntacts

and

their

respective

I/O

assignments.

A

P wer

M dule

mainframe

pti n

is

available

which

pr vides

a

rear-panel,

multi-pin

c nnect r

t

which

these

data

can

be

hard-wired

f r

external

access.

Als

p ssible

are

intra



c mpartment

c nnecti ns

with

ther

plug-in

m dules

when

using

a

multi-c mpartment

P wer

M dule.

SPECIFICATIONS

Option

1

—

Precision

Time

Base

The

DC

502

can

be

rdered

with

a

temperature-

c mpensated

5-MHz

crystal

scillat r

t

pr vide

a

highly

stable

(5

parts

in

10

7

)

and

precise

internal

time

base.

This

pti n

includes

a

divide-by-five

1C

c unter

t

pr duce

the

1-MHz

cl ck.

Measurement

Ranges,

Resolution,

and

Accuracy

Frequency,

10

Hz

t

550

MHz;

Gate

times,

0.01

s,

0.1

s,

1

s,

and

10

s;

Display

time,

ab ut

0.1

s

t

10

s

t

HOLD;

T talizing

capacity,

0

t

10

7

;

Res luti n

(DIRECT

INPUT),

100

Hz

at

0.01

s

gate

time,

10

Hz

at

0.1

s,

1

Hz

at

1

s,

and

0.1

Hz

at

10

s;

Res luti n

(4-10

PRE-SCALE

INPUT),

1000

Hz

at

0.01

s,

100

Hz

at

0.1

s,

10

Hz

at

1

s,

and

1

Hz

at

10

s;

Accuracy,

±1

c unt

±

time

base

accuracy.

Direct

Input

Frequency,

10

Hz

t

110

MHz;

Sensitivity,

300

mV

peak-t -peak;

Trigger

level

range,

±2

V;

Attenuators,

X1,

X5,

X10,

and

X50;

Coupling,

AC;

Input

impedance,

appr ximately

1

M

paralleled

by

ab ut

20

pF;

Maximum

input

volts,

500

V

(DC

+

peak

AC,

r

peak-t -peak

AC).

÷10

Pre-Scale

Input

Frequency,

50

MHz

t

550

MHz;

Sensitivity,

500

mV

peak

t

peak;

Coupling,

AC;

Input

impedance,

appr xi



mately

50

;

Maximum

input

volts,

10

V

peak-t -peak.

Data

Inputs

and

Outputs

Available

via

plug-in

c nnect r

t

multi-pin

c nnect r

at

rear

f

P wer

M dule.

Input

lines

are

available

f r

internal

and

external

scan

cl ck

c ntr l.

Output

lines

are

available

f r

BCD

utput

(serial-by-digit),

and

t

indicate

status

f

timing,

data

g d,

reset,

scale,

decimal

p int

and

verfl w.

Internal

Time

Base

Standard

Option

1

Crystal

Frequency

1

MHz

5

MHz

Stability

(0°C

t

+50°

C),

after

1/2

h ur

warm-up

Within

1

part

in

10

5

Within

5

parts

in

10

7

L ng-term

Drift

1

part

r

less

in

10

5

per

m nth

1

part

in

10

7

per

m nth

Accuracy

Adjustable

t

within

1

part

in

10

7

Adjustable

t

within

5

parts

in

10

9

Other

Temperature

Range,

Operating:

0°C

t

+50°C;

N n



perating:

—

40°

C

t

+75°C.

Altitude

Range,

Operating:

t

15,000

feet;

N n-

)

perating:

50,000

feet.

1-4

REV.

MAY

1974

®2

Section

2

—

DC

502

SECTION

2

THEORY

OF

OPERATION

INPUT

CIRCUITS

Direct

Input

Attenuators.

Signals

t

be

c unted

are

applied

via

fr nt-panel

DIRECT

INPUT

c nnect r

J100

t

the

attenu



at rs.

The

attenuat rs

are

frequency-c mpensated

v ltage

dividers

c nsisting

f

resist rs

R102-R107

and

capacit rs

C102-C107.

Switches

S100A

and

S100B

all w

fr nt-panel

selecti n

f

X1,

X5,

X10,

r

X50

attenuati n

f

the

input

signal.

C1

10

pr vides

AC

c upling.

FET

s urce

f ll wer

Q115

and

emitter

f ll wer

Q122

present

a

high

impedance

t

the

input

signal.

The

di des

in

the

base

circuit

f

E.

F.

Q128

f rm

a

series-limiter

and

clamping

netw rk,

which

reduces

the

input

signal

t

limits

suitable

f r

driving

the

shaping

circuits.

The

clamping

di des

limit

the

v ltage

at

the

emitter

f

Q128

t

a

dynamic

range

f

ab ut

1.2

v lts.

Signal-Shaping.

U150B,

an

OR

gate

integrated

circuit

with

push-pull

utputs,

is

c nnected

as

a

Schmitt

trigger.

It

shapes

the

input

signal

int

a

square

wave.

Its

“

hysteresis

wind w

“

is

a

width

f

ab ut

200

mV.

The

utput

changes

states

when

the

signal

v ltage

passes

thr ugh

the

upper

thresh ld,

then

reverts

t

its

riginal

state

when

the

signal

v ltage

passes

thr ugh

the

l wer

thresh ld.

F r

this

reas n,

an

input

signal

smaller

in

amplitude

than

the

width

f

the

hysteresis

wind w

cann t

activate

the

c unting

circuits.

The

quiescent

level

at

the

input

f

U150B

can

be

adjusted

t

verc me

s me

f

the

triggering

difficulties

arising

fr m

vari us

input-signal

shapes

and

frequencies.

Integrated-circuit

perati nal

amplifier

U135

and

its

ass ciated

discrete

c mp nents

are

c nnected

as

a

v ltage

f ll wer.

TRIGGER

LEVEL

p tenti meter

R135

selects

a

v ltage

between

gr und

and

ab ut

—

2

v lts

and

applies

it

t

3

f

U135.

This

level

is

then

established

at

2,

and

hence,

the

input

f

U150B,

thr ugh

the

acti n

f

the

perati nal

amplifier.

The

utput

f

U150B

is

applied

t

U150A,

wh se

push-pull

utputs

drive

Q160

and

Q162,

which

are

c nnec



ted

as

a

differential

pair.

This

circuit

pr vides

a

level

shift

t

TTL

level,

and

further

shapes

the

signal

t

be

c unted.

A

wavef rm

with

fast

rising

and

falling

edges

is

pr duced

at

the

c llect r

f

Q160.

CR165

limits

the

amplitude

f

the

c unt

signal

t

5

v lts,

clamping

the

negative-g ing

p rti n

f

the

signal

t

gr und.

The

signal

is

then

passed

thr ugh

emitter

f ll wer

Q170

t

U160B,

where

it

receives

a

final

phase

inversi n

(t

c rresp nd

with

the

input

signal)

and

bec mes

the

decade

input.

4-10

Pre-Scale

Input

Circuit

50

MHz

t

550

MHz

signals

applied

t

J180

are

AC-c upled

int

a

50

envir nment.

A

quiescent

10

mA

current,

set

by

R185

and

R187,

keeps

CR185,

186,

187

and

188

in

the

di de

clamping

bridge

turned

n

until

the

input

signal

amplitude

reaches

ab ut

±0.4

V.

While

the

bridge

is

turned

n,

the

signal

s urce

sees

ab ut

20

equivalent

resistance

f

the

bridge

in

series

with

R189,

24,

and

the

emitter

resistance

f

Q190,

ab ut

5.

As

the

signal

amplitude

exceeds

±0.4

V,

ne

pair

f

di des

(CR185,

CR188)

begins

t

turn

ff

during

p sitive-g ing

excursi ns,

while

the

ther

pair

(CR186,

CR187)

turns

ff

during

negative-g ing

excursi ns.

As

these

di de

pairs

alternately

turn

ff

with

signal

amplitude

changes,

a

matched

pair

f

di des

(CR181A,

CR181B)

n

the

input

side

f

the

c upling

capacit r,

C182,

alternately

turn

n

t

maintain

the

50

input

impedance.

C181

prevents

CR181A

&

CR181B

fr m

being

biased

n

r

ff

by

DC

levels

which

may

be

part

f

the

input

signal.

The

clamping

acti n

f

the

bridge

di des

limits

the

changing

DC

level

at

the

bridge

utput

t

a

maximum

0.8

V

peak-t -peak.

This

signal

is

then

c upled

by

C188

t

Q190

via

the

high-frequency

peaking

netw rk,

C189-R189.

C192

c uples

the

amplified

signal

t

10,

the

high

impedance

input

f

the

4-10

c unter,

U190.

C192

is

m unted

n

the

circuit

b ard

with

special

lead

dress

t

aid

high

frequency

resp nse

at

minimum

signal

amplitudes.

Bead

L192

is

m unted

n

ne

lead

f

C192

t

suppress

high

frequency

scillati ns.

R191

establishes

a

bias

at

10

f

U190.

C191,

193,

and

194

dec uple

pins

14,

13,

and

12,

respectively,

right

at

the

terminal

c nnecti ns

t

the

circuit

b ard.

L199

and

C199

suppress

p wer

supply

n ise

and

dec uple

the

Vcc

input,

14.

4

f

U190

pr duces

ne

utput

cycle,

a

level

change

f

ab ut

0.5

V,

f r

every

ten

input

events

t

10.

The

base

f

Q195

swings

appr ximately

between

3.4

V

and

3.9

V.

The

emitter-f ll wer

acti n

f

Q195

pr vides

a

healthy

current

drive

t

the

base

f

Q198,

which

w uld

saturate

in

n -signal

c nditi ns

except

f r

CR196.

The

c llect r

f

Q198

can,

theref re,

resp nd

immediately

t

signal

changes,

pr ducing

a

TTL-c mpatible

utput

t

drive

9

f

U160B

in

the

gating

l gic

t

the

Decade

C unting

Units.

2-1

Theory

of

Operation

—

DC

502

TIME

BASE

AND

CONTROL

CIRCUIT

1

MHz

Clock

A

precise

ne

megahertz

cl ck

pr vides

the

reference

f r

perati n

f

the

gate-generating

circuits.

The

utput

f

crystal

scillat r

Y200

is

adjustable

by

C201

t

exactly

ne

megahertz.

The

f ur

parts

f

U200

f rm

a

shaper-buffer

stage

t

pr duce

square-wave

cl ck

pulses

and

t

is late

the

scillat r

fr m

the

1-MHz

utput

line.

Optional

Clock

An

pti nal

1

MHz

cl ck

is

available,

using

a

very

stable

5

MHz

crystal

scillat r

and

a

divide-by-five

c unter.

This

c mbinati n

is

sh wn

n

the

schematic

as

Y201

and

U201.

Decade

Divider

Units

(DDU's)

The

DDU's

c nsist

f

seven

cascaded

divided-by-ten

c unters,

U209

thr ugh

U215.

They

pr duce

f ur

gate

times,

0.01

sec,

0.1

sec,

1

sec

and

10

sec,

which

are

made

available

via

the

MEASUREMENT

INTERVAL

switch

t

the

gate

generat r

t

establish

the

precise

time

interval

the

GATE

is

pen.

The

1-MHz

cl ck

signal

is

applied

t

14

f

U209,

wh se

utput

is

c nnected

t

the

input

f

the

subsequent

decade.

Each

decade

is

cl cked

with

a

negative



g ing

transiti n.

The

DDU's

are

reset

by

a

CLEAR

pulse,

which

places

a

0

c unt

in

U209

and

a

9

c unt

in

each

subsequent

decade.

Gate

Generator

The

gate

generat r

pr

duces

t

he

GATE

c ntr l

signal

and

initiates

the

CLEAR,

and

LATCH

pulses.

The

generating

p rti n

c nsists

f

U220A,

U222A,

U220B,

and

U222B.

The

display

time

c ntr l

p rti n

c nsists

f

Q230,

Q238,

and

Q240.

The

circuit

will

be

described

first

in

the

n rmal

gate

m de

(MEASUREMENT

INTERVAL

switch

in

ne

f

the

f ur

gate

time

p siti ns).

Assume

that

the

T

c nditi ns

are

as

given

in

Fig.

2-1.

The

Q

utputs

f

U220A,

U222A,

U220B,

and

U222B

are

all

LO.

Q230

is

ff

and

the

emitter

f

Q238

rises

as

C235

charges.

At

T

v

Q238

reaches

its

firing

p tential

and

discharges

the

capacit r.

This

results

in

a

sh rt-durati n

LO

pulse

n

the

direct-set

input

(pin

2)

f

U220A,

f rcing

its

Q

utput

HI

and

its

Q

utput

LO.

With

tw

HI

inputs

n

NAND

gate

U230A,

its

utput

g es

LO

and

the

utput

f

®î

)

2-2

REV.

MAY

1974

Theory

of

Operation

—

DC

502

NOR

ga

te

U230C

g es

HI,

pr ducing

the

CLEAR

and

CLEAR

c ntr l

signals.

The

transiti n

fr m

the

1-MHz

cl ck

(

T

2

)

t ggles

U222A,

causing

its

Q

utput

t

g

HI

and

its

Q

t

g

LO.

With

a

LO

applied

t

ne

f

its

inputs,

U230A

rev

erts

t

it

s

riginal

c nditi n,

terminating

the

CLEAR

and

CLEAR

pulses.

The

DDU's

then

start

c unting

fr m

their

0999999

reset

c nditi n.

At

the

end

f

a

10-micr sec nd

delay

(time

f r

the

DDU's

t

c unt

the

first

digit,

plus

a

pr pagati n

delay),

a

negative

transiti n

fr m

the

DDU's

via

the

MEASURE



MENT

INTERVAL

switch

t ggles

U220B.

This

c rresp nds

t

T

3

in

Fig.

2-1.

U220B's

Q

utput

g es

HI

and

its

Q

utput

g es

LO.

The

transiti n

fr m

the

1-MHz

cl ck

(T

4

)

t ggles

U222B,

causing

its

Q

utput

t

g

HI

(GATE

pen)

and

its

Q

utput

t

g

LO

(supplying

current

t

the

fr nt-panel

GATE

indicat r

LED,

DS225).

The

GATE

signal

is

als

applied

t

the

base

f

Q230,

saturating

the

transist r

and

preventing

C235

fr m

charging.

The

GATE

remains

pen

(HI)

f r

the

time

durati n

selected

by

the

MEASUREMENT

INTERVAL

switch.

At

the

end

f

this

time,

which

c rresp nds

t

T

5

in

Fig.

2-1,

an ther

negative

transiti n

fr m

the_DDU's

t ggles

U220B.

U220B's

Q

utput

g es

LO

and

its

Q

utput

g es

HI.

The

transiti n

fr m

the

1-MHz

cl ck

(T

6

)

t ggles

U222B,

causing

its

Q_ utput

t

g

LO,

cl sing

the

GATE.

Simultane usly,

the

Q

utput

g es

HI,

rem ving

current

fr m

the

GATE

indicat r

LED.

When

the

GATE

utput

g es

LO,_the

negative

transiti n

t ggles

U220A,

switching

Q

LO

and

Q

HI.

N w

NAND

gate

U230D

has

tw

HI

inputs,

placing

a

LO

at

the

input

f

OR

gate

U230B

and

activating

the

LATCH

c ntr l

signal

(HI

state).

One

micr sec nd

later

(T

7

),

a

negative

edge

fr m

the

1-MHz

cl ck

t ggles

U222A,

switching

its

utputs

and

placing

a

LO

n

the

input

f

NAND

gate

U230D.

U230D

reverts

t

its

riginal

c nditi n,

terminating

the

LATCH

signal.

The

display

time

begins

when

the

GATE

signal

ends

(T

6

).

When

Q230

turns

ff,

C235

begins

t

charge

thr ugh

R232-R235

t ward

the

Vcc

supply.

R235,

DISPLAY

TIME,

pr vides

an

adjustable

time

c nstant

t

vary

the

display

time

fr m

ab ut

0.1

sec nd

t

ab ut

10

sec nds.

When

the

DISPLAY

TIME

c ntr l

is

fully

cl ckwise

(HOLD

detent

p siti n),

S235

pens,

and

C235

st ps

charging.

When

S235

is

cl sed

and

C235

charges

sufficiently

t

bring

Q238

t

its

firing

p tential

(T

1

,

the

display

time

ends

and

the

sequence

begins.

Manual

Gate

The

manual

m de

f

perati n

is

selected

by

placing

the

MEASUREMENT

INTERVAL

switch

in

the

MANUAL

p siti n.

The

switch

cl sure

t

gr und

(cam

5

f

the

switch)

places

a

LO

n

the

set

inputs

f

U220B

and

U222A,

and

a

LO

n

the

clear

input

f

U220A.

This

f rces

the

Q

utputs

f

U222A

and

U220B

HI,

and

the

Q

utput

f

U220A

LO.

With

b th

inputs

f

U230D

held

HI,

the

LATCH

utput

is

held

HI,

all wing

the

c unter

t

update

the

display

c ntinu usly.

The

GATE

is

pened

when

the

fr nt-panel

START

butt n

is

pushed

in,

pening

S210

and

applying

a

HI

t

the

clear

input

f

U222B.

As

bef re,

the

GATE- pen

c nditi n

is

HI

at

the

Q

utput

f

U222B.

The

GATE

is

then

cl sed

when

S210

is

set

t

STOP

(butt n

ut).

T

reset

the

c unters

in

the

manual

m de

,

the

RE

SET

butt n

must

be

pushed

t

activate

t

CLEAR,

CLEAR

and

RESET

c ntr l

signals.

COUNTER

Decade

Counter

Units

(DCU's)

The

10°

thr ugh

10

6

DCU's

are

seven

cascaded

divide-by-ten

c unters.

The

first

decade

c unter

is

made

up

f

f ur

individual

J-K

flip-fl ps

t

accept

the

high-speed

decade

input

(up

t

100

MHz),

and

each

subsequent

DCU

is

a

single

IC.

U165A,

U165B,

U167,

and

U169

c mprise

the

first

(10°)

decade

c unter,

and

U235

thr ugh

U240

make

up

the

remaining

six

DCU's.

When

the

J

and

K

inputs

f

U165B

are

HI

(GATE

pen),

the

c unter

is

enabled.

The

input

signal

is

applied

t

the

t ggle

input

f

U165B.

On

every

tenth

cl ck

input

c unted

by

the

first

decade

c unter,

the

utput

f

U169

g es

LO,

pr viding

a

carry

signal

which

bec mes

the

cl ck

input

f r

the

sec nd

decade

c unter.

Each

subsequent

decade

divides

CIRCUITS

by

ten

in

a

similar

manner.

F ur

BCD

utput

lines

are

c nnected

fr m

each

DCU

t

its

a

ss ciated

st rage-register

latch.

When

the

CLEAR

(HI)

and

CLEAR

(LO)

signals

are

activated,

all

f

the

decade

c unters

are

reset

t

the

zer -c unt

state.

Storage

Register

The

seven

IC

latches

(U250

thr ugh

U256)

c mprise

a

st rage

register

which

st res

the

c rresp nding

decade

c unter

BCD

utput.

The

BCD

utput

is

applied

t

the

data

inputs

at

pins

1,

5,

7,

and

3

(2°,

2

1

,

2

,

and

2

3

bits

respectively).

The

LATCH

pulse

is

applied

t

the

data-

str be

input

at

2

f

each

latch

immediately

up n

cl sure

f

the

GATE

r

when

the

MEASUREMENT

INTERVAL

switch

is

placed

in

the

MANUAL

p siti n,

as

2-3

Theory

of

Operation

—

DC

502

described

in

the

time

base

and

c ntr l

circuit.

When

the

LATCH

input

g es

HI,

the

l gic

levels

at

the

data

inputs

are

transferred

t

the

ass ciated

BCD

bit

utput

t

be

scanned

by

the

multiplexing

circuit.

Overflow

Register

When

the

decade

c unters

have

c unted

t

9,999,999,

the

c unters

are

full.

At

the

2

3

utput

f

U240

g es

LO,

pr viding

a

t ggle

input

t

U241B.

When

this

ccurs,

a

LO

is

transferred

fr m

10

t

8

f

U241B,

then

when

the

LATCH

pulse

ends

(g es

LO),

U241A

is

t ggled

and

the

LO

is

transferred

t

13.

When

13

f

U241A

g es

LO,

CR241

and

DS242

c nduct.

DS242

is

an

LED,

and

in

its

c nducti n

state

gives

a

fr nt-panel

OVERFLOW

indicati n.

In

the

Manual

c unting

m de,

OVERFLOW

indicati n

is

achieved

via

Q242

and

CR244.

The

emitter

f

Q242

is

gr unded

by

a

switch

cl sure,

then

when

9

f

U241B

g es

HI

n

the

first

verfl w

c unt,

Q242,

CR244,

and

DS242

turn

n.

U241

is

reset

by

the

CLEAR

pulse.

T

prevent

leading



zer

suppressi n

during

the

verfl w

c nditi n,

the

display



c ntr lling

circuits

are

n tified

via

U245A

that

the

c unt

is

in

excess

f

that

displayed

by

the

LED

read ut.

DECODE

AND

DISPLAY

MULTIPLEX

Scan

Clock

The

scan

rate

f

the

multiplexing

circuit

is

determined

by

the

scan

cl ck.

The

scan

cl ck

is

c mp sed

f

U260B

and

U260D,

which

perate

as

a

free-running

multivibrat r

at

an

appr ximate

2-kil hertz

rate.

The

scan-cl ck

utput

is

passed

thr ugh

NOR

gate

U260A,

which

can

als

accept

an

externally

applied

scan-cl ck

signal.

Other

input/ utput

lines

pr vide

internal

scan-cl ck

disable

and

internal

scan



cl ck

utput.

The

scan

cl ck

drives

an

eight-state

c unter

and

a

st rage

register

f r

zer

suppressi n.

÷

8

Counter

and

Time-Slot

Decoder

The

divide-by-eight

c unter

is

made

up

f

U262B,

U263A,

and

U262A,

which

are

three

halves

f

SN7474

type

D

flip-fl ps.

The

utput

f

this

c unter

drives

U265,

an

SN74145

BCD-t -decimal

dec der.

U265

pr vides

eight

utput

lines

(designated

TS

0

thr ugh

TS

7

in

the

schematics

and

in

Fig.

2-2)

t

simultane usly

enable

the

utput

f

each

c unter

latch

and

its

c rresp nding

display

LED

sequentially.

F r

example,

when

the

TS

1

line

g es

LO,

Q280

is

turned

n

t

supply

an de

v ltage

t

DS280

at

the

same

time

inverter

U267C

applies

a

HI

t

6

f

latch

U256,

enabling

its

utput.

Operati n

in

a

time

sequence

all ws

the

latches

t

share

a

c mm n

set

f

utput

lines.

Seven-Segment

Decoder

and

Display

LED's

U270

is

a

BCD-t -seven

dec der.

It

accepts

the

BCD

utput

f

the

latches,

then

supplies

current

t

the

appr priate

cath des

f

the

enabled

LED

t

display

the

c rrect

number.

The

display

LED's

are

DS280

thr ugh

DS286.

When

l king

at

the

fr nt

panel

f

the

DC

502,

DS280

c ntr ls

the

numerical

digit

displayed

at

the

far

left

(10

6

),

DS281

c ntr ls

the

sec nd

(10

5

),etc.

Each

LED

has

seven

segments,

arranged

s

that

a

c mbinati n

f

lighted

segments

f rms

a

number.

When

all

f

the

segments

are

lighted,

an

“

8"

is

f rmed.

Leading

Zero

Suppression

Dec der

driver

U270

als

has

a

zer -blanking

feature

which

all ws

suppressi n

f

the

zer es

leading

the

m st

significant

digit

(MSD)

in

the

display.

At

TS

0

,

a

LO

is

applied

t

the

direct-clear

input

f

U263B,

the

zer



suppressi n

st rage

register.

This

sets

U263B

t

the

zer -suppress

state

(HI

at

8),

all wing

the

Ripple-

Blanking

Input

(RBI,

5)

f

U270

t

be

LO.

When

the

utput

f

U265

advances

t

the

sl t

(TS

1

)

,

the

RBI

f

U270

remains

LO

f r

a

few

nan sec nds

due

t

pr pagati n

delays,

which

all ws

the

first

digit

t

arrive

fr m

the

latches

while

RBI

is

LO.

If

this

first

digit

being

dec ded

is

a

zer ,

the

utput

t

the

display

LED

will

be

inhibited

and

the

Ripple

Blanking

Output

(pin

4)

will

be

LO.

If

the

digit

is

n t

a

zer ,

the

utputs

are

enabled

and

RBO

g es

HI.

The.RBO

is

applied

t

the

D

input

(pin

12)

f

U263B

and

is

transferred

t

the

utput

when

the

HI-t -LO

transiti n

ccurs.

Thus,

if

the

first

digit

is

a

zer ,

5

f

U270

is

held

LO,

inhibiting

the

utput

until

the

first

n n-zer

digit

c mes

thr ugh

the

dec der.

When

the

first

n n-zer

digit

arrives,

the

utputs

f

U270

are

enabled

and

the

digit

is

displayed.

Als ,

the

RBO

utput

at

4

is

set

HI,

rem ving

the

RBI

fr m

5

and

all wing

all

succeeding

digits

t

be

displayed

thr ugh

the

TS

7

sequence.

When

the

scan

gets

past

the

decimal

p int

in

the

display,

r

if

the

display

verfl ws,

any

zer es

arriving

at

the

dec der

sh uld

be

displayed.

This

is

achieved

as

f ll ws:

TS

5

is

inverted

by

U267E

and

applied

thr ugh

OR

gate

U245B

as

a

LO

at

the

direct-set

input

f

U263B.

This

h lds

5

f

U270

HI,

preventing

zer -blanking

during

the

TS

5

,

TS

6

,

and

TS

7

time

sl ts.

The

l cati n

f

the

decimal

p int

in

the

display

is

determined

by

the

MEASUREMENT

INTERVAL

switch.

The

pr per

inf rmati n

is

applied

via

the

cl sed

c ntacts

f

the

switch

t

either

NAND

gate

U246A

r

U246B.

Then

either

TS

3

r

TS

4

is

enabled

t

the

2-4

Theory

of

Operation-DC

502

1

MHz

clock

RESET

Forced

by

RESET

RBI,

5

U270

Fig.

2-2.

Multiplexing

circuit

ladder

diagram

showing

timing

with

an

all-zero

display.

input

f

OR

gate

U245B

via

these

NAND

gates,

setting

U263B

t

the

n n-blank

state

at

the

appr priate

time.

In

the

case

where

the

c unter

verfl ws,

the

HI

utput

fr m

U245A

is

applied

t

U245B,

setting

U263B

t

the

n n-blank

state.

When

the

fr nt-panel

RESET

butt n

is

pushed,

RESET

g es

LO,

verriding

the

utput

f

U263B,

applying

the

n n-blank

and

lamp-test

functi ns

t

the

dec der.

This

causes

all

seven

segments

in

the

display

LED

t

be

turned

n.

POWER

SUPPLIES

AND

INPUT/OUTPUT

LINES

Regulated

Power

Supplies

The

DC

502

perating

p wer

is

btained

fr m

the

p wer

m dule

mainframe

and

then

electr nically

regulated

t

pr vide

stable

supplies

f

+15

v lts,

+5

v lts,

—

5.2

v lts,

and

—

10

v lts.

The

+15-v lt

supply,

wh se

active

device

is

U300,

pr vides

the

reference

f r

the

remaining

supplies.

Its

utput

is

set

t

+15

V

by

adjustment

f

R305.

Integrated

circuit

U320

regulates

the

+5-v lt

supply,

and

transist rs

Q330

and

Q340

regulate

the

—

5.2-v lt

and

—

10-v lt

supplies

respectively.

The

series-pass

transist rs

f r

these

supplies

are

l cated

in

the

mainframe,

where

they

can

pr vide

the

pr per

heat

dissipati n.

INT

SCAN

DISABLE:

A

LO

applied

t

this

line

disables

the

internal

scan

cl ck.

EXT

SCAN:

Pr vides

input

f r

an

external

scan

cl ck.

INT

SCAN

CLOCK

OUT:

Pr vides

utput

f r

the

internal

scan

cl ck.

TS

0

:

A

LO

is

present

n

this

utput

line

in

the

TS

q

state.

Input/Output

Lines

The

f ll wing

inputs

and

utputs

are

available

via

the

plug-in

c nnect r

t

external

equipment.

See

Fig.

1-3,

als .

DATA

GOOD:

A

HI

is

present

n

this

utput

line

when

a

new

reading

is

being

transferred

int

the

st rage-register

latches.

2-5

Theory

of

Operation

—

DC

502

OVERFLOW:

This

utput

is

HI

when

the

c unt

ver



fl ws.

RESET:

This

is

a

dual-functi n

input/ utput

line.

It

pr vides

a

LO

utput

during

reset,

r

can

be

used

as

an

external

reset

input.

Data

Lines:

1,

2,

4,

8

pr vide

BCD

utput,

serial

by

digit,

fr m

the

currently

enabled

st rage-register

latch.

Other

data

lines

include

a

LO

when

the

MHz

light

is

n,

a

LO

when

the

sec nd

decimal

p int

is

lit,

and

a

HI

when

the

left-side

digit

(MSD)

is

enabled.

DC

502

SERVICE

INFORMATION

DIAGRAMS,

PARTS

LISTS,

AND

ILLUSTRATIONS

Symbols

and

Reference

Designators

Electrical

c mp nents

sh wn

n

the

diagrams

are

in

the

f ll wing

units

unless

n ted

therwise:

Capacit rs

=

Values

ne

r

greater

are

in

pic farads

(pF).

Values

less

than

ne

are

in

micr farads

(µF).

Resist rs

=

Ohms

()

Symbols

used

on

the

diagrams

are

based

on

ANSI

Y

32.2

—

1970.

L gic

symb l gy

is

based

n

MIL-STD-806B

in

terms

f

p sitive

l gic.

L gic

symb ls

depict

the

l gic

functi n

perf rmed

and

may

differ

fr m

the

manufacturer's

data.

The

f ll wing

special

symb ls

are

used

n

the

diagrams:

External

Screwdriver

adjustment.

External

c ntr l

r

c nnect r.

Cl ckwise-c ntr l

r tati n

in

directi n

f

arr w.

Refer

t

diagram

number

indicated

in

diam nd.

Refer

t

wavef rm

number

indicated

in

hexag n.

—

•

—

Wv

C nnecti n

s ldered

t

circuit

b ard.

C nnecti n

made

t

circuit

b ard

with

interc nnecting

pin.

------

Blue

tint

encl ses

c mp nents

l cated

n

circuit

b ard.

F7O

circuit

b ard

3-1

I

DC

502

ELECTRICAL

PARTS

LIST

ABBREVIATIONS

AND

REFERENCE

DESIGNATORS

Replacement

parts

sh uld

be

rdered

fr m

the

Tektr nix

Field

Office

r

Representative

in

y ur

area.

Changes

t

Tektr nix

pr ducts

give

y u

the

benefit

f

impr ved

circuits

and

c mp nents.

Please

include

the

instrument

type

number

and

serial

number

with

each

rder

f r

parts

r

service.

A

Assembly,

separable

r

FL

Filter

PTM

paper

r

plastic,

tubular

repairable

H

Heat

dissipating

device

m lded

AT

Attenuat r,

fixed

r

variable

(heat

sink,

etc.)

R

Resist r,

fixed

r

variable

B

M t r

HR

Heater

RT

Thermist r

BT

Battery

J

C nnect r,

stati nary

p rti n

S

Switch

C

Capacit r,

fixed

r

variable

K

Relay

T

Transf rmer

Cer

Ceramic

L

Induct r,

fixed

r

variable

TP

Test

p int

CR

Di de,

signal

r

rectifier

LR

Induct r/resist r

c mbinati n

U

Assembly,

inseparable

r

CRT

cath de-ray

tube

M

Meter

n n-repairable

DL

Delay

line

Q

Transist r

r

silic n-

V

Electr n

tube

DS

Indicating

device

(lamp)

c ntr lled

rectifier

Var

Variable

Elect.

Electr lytic

P

C nnect r,

m vable

p rti n

VR

V ltage

regulat r

(zener

di de,

EMC

electr lytic,

metal

cased

PMC

Paper,

metal

cased

etc.)

EMT

electr lytic,

metal

tubular

PT

paper,

tubular

ww

wire-w und

F

Fuse

Y

Crystal

Tektronix

Serial/Model

No.

Ckt.

No.

Part

No.

Eff

Disc

Description

ASSEMBLIES

670-2102-00

B0

10100

B039999

MAIN

Circuit

Board

Assembl

A1

2

670-3409-00

B040000

MAIN

Circuit

Board

Assembl

Al

2

670-3410-00

MAIN

Circuit

Board

Assembl

A2

670-2103-00

DISPLAY

Circuit

Board

Assembl

A3

670-2438-00

÷

10

PRE-S

CALER

Circuit

Board

Assembl

A4

670-2708-00

PROTECTION

Circuit

Board

Assembl

A5

670-3300-00

XB040000

r

5

Circuit

Board

Assembl

CAPACITORS

C102

M5

281-0510-00

22

pF,

Cer,

500

V,

20%

C10

3

M4

281-0605-00

200

pF,

Cer,

500

V

C106

L4

281-0509-00

15

pF,

Cer,

500

V,

10%

C107

L5

281-0540-00

51

pF,

Cer,

500

V,

5%

C

110

*

L5

283-0068-00

B0

10100

B050499

0.01

µF,

Cer,

500

V,

+100%-0%

C110

L5

283-0267-00

B050500

0.01

µF,

Cer,

500

V,

20%

C110

2

L5

283-0068-00

B010100

B040502

0.01

µF,

Cer,

500

V,

+100%-0%

C110

z

L5

283-0267-00

B040503

0.01

µF,

Cer,

500

V,

20%

C112

L5

281-0571-00

82

pF,

Cer,

500

V,

20%

C113

L6

283-0003-00

0.01

µF,

Cer,

150

V,

+80%-20%

C122

K5

283-0000-00

0.001

µF,

Cer,

500

V,

+100%-0%

C127

K5

283-0000-00

0.001

µF,

Cer,

500

V,

+100%-0%

C139

M5

283-0003-00

0.01

µF,

Cer,

150

V,

+80%-20%

C140

L5

283-0177-00

1

µF,

Cer,

25

V,

+80%-20%

C141

M5

283-0000-00

0.001

µF,

Cer,

500

V,

+100%-0%

C152

J5

281-0589-00

170

pF,

Cer,

500

V,

5%

C181

R2

283-0219-00

1500

pF,

Cer,

50

V,

20%

C182

R3

283-0219-00

1500

pF,

Cer,

50

V,

20%

C184

R2

283-0219-00

1500

pF,

Cer,

50

V,

20%

C187

R3

283-0219-00

1500

pF,

Cer,

50

V,

20%

C188

Q3

283-0219-00

1500

pF,

Cer,

50

V,

20%

C189

Q3

283-0154-00

22

pF,

Cer,

50

V,

5%

C191

Q2

283-0204-00

0.01

µF,

Cer,

50

V,

20%

^Standard

onl .

Option

1

onl .

REV.

MAY

1974

3-2

DC

502

ELECTRICAL

PARTS

LIST

(cont)

DIODES

Ckt

No.

Grid

Loc

Tektronix

Part

No.

Serial/Model

No.

Eff

Disc

Description

CAPACITORS

(cont)

C192

Q3

283-0067-00

0.001

µF,

Cer,

200

V,

10%

C193

Q3

283-0204-00

0.01

µF,

Cer,

50

V,

20%

C194

Q2

283-0204-00

0.01

µF,

Cer,

50

V,

20%

C196

Q3

283-0167-00

0.001

µF,

Cer,

200

V,

10%

C199

R2

290-0532-00

150

µF,

Elect.

,

6

V,

20%

C200

G5

281-0504-00

10

pF,

Cer,

500

V,

10%

C201

G4

281-0166-00

1.9-15.7

pF,

Var,

Air

C202

G5

281-0739-00

18

pF,

Cer,

500

V

C235

L4

290-0526-00

10

µF,

Elect.

,

25

V,

20%

C252

281-0523-00

XB080000

100

pF,

Cer,

350

V,

20%

C254

281-0523-00

XB0

80000

100

pF,

Cer,

350

V,

20%

C256

281-0523-00

XB080000

100

pF,

Cer,

350

V,

20%

C258

281-0523-00

XB0

80000 100

pF,

Cer,

350

V,

20%

C260

L

1

283-0111-00

0.1

µF,

Cer,

50V

C265

L

1

283-0111-00

0.1

µF,

Cer,

50

V

C267

283-0000-00

XB010129

0.001

µF,

Cer,

500

V,

+100%-

0%

C302

D6

290-0529-00

47

µF,

Elect.

,

20

V,

20%

C305

D6

283-0060-00

100

pF,

Cer,

200

V,

5%

C322

B5

290-0531-00

100

µF,

Elect.,

10

V,

20%

C325

B6

283-0150-00

650

pF,

Cer,

200

V,

5%

C334

H6

283-0000-00

0.001

µF,

Cer,

500

V,

+100%-

0%

C335

H6

283-0177-00

1

µF,

Cer,

25

V,

+80%-20%

C340

D6

290-0529-00

57

µF,

Elect.,

20

V,

20%

CR115

K5

152-0141-02

Silicon,

replaceable

b

1N4152

CR122

K4

152-0141-02

Silicon,

replaceable

b

1N4152

CR124

J5

152-0141-02

Silicon,

replaceable

b

1N4152

CR125

J5

152-0141-02

Silicon,

replaceable

b

1N4152

CR127

J5

152-0141-02

Silicon,

replaceable

b

1N4152

CR128

J5

152-0141-02

Silicon,

replaceable

b

1N4152

CR165

H5

152-0141-02

Silicon,

replaceable

b

1N4152

CR181A,BP1

152-0442-01

Schottk

barrier,

matched

pair

CR185

Q

1

152-0322-00

Silicon,

replaceable

b

A1108

CR186

P

1

152-0322-00

Silicon,

replaceable

b

A110

8

CR187

Q

1

152-0322-00

Silicon,

replaceable

b

A110

8

CR188

Q

1

152-0322-00

Silicon,

replaceable

b

A1108

CR196

Q3

152-0322-00

Silicon,

replaceable

b

A110

8

CR240

K3

152-0141-02

Silicon,

replaceable

b

1N4152

CR241

I1

152-0141-02

Silicon,

replaceable

b

1N4152

CR244

I1

152-0141-02

Silicon,

replaceable

b

1N4152

VR230

Q5

152-0166-00

Zener,

selected

from

1N753A,

0.4

W,

6.2

V,

5

%

INDICATORS

DS225

06

150-1001-01

DS242

P6

160-1001-01

DS280

N5

150-1002-00

DS

281

Q5

150-1002-00

DS

282

Q5

150-1002-00

DS

283

Q5

150-1002-00

DS284

P5

150-1002-00

DS

285

P5

150-1002-00

DS286

P5

150-1002-00

DS290

150-1001-01

DS292

150-1001-01

FUSE

F320

R5

159-0021-00

Lamp,

light

emitting

diode,

2

V

Lamp,

light

emitting

diode,

2

V

Numeric

displa ,

Numeric

displa ,

Numeric

displa ,

Numeric

displa ,

Numeric

displa ,

Numeric displa ,

Numeric

displa ,

seven-segment,

seven-segment

,

seven-segment

,

seven-segment,

seven-segment

,

seven-segment

,

seven-segment

,

Lamp,

light

emitting

diode,

2

V

Lamp,

light

emitting

diode,

2

V

,

70

,

70

red

,

70

,

70

mA

Cartridge,

2A,

3AG,

fast-blo

3-3

REV.

MAY

1974

©

DC

502

ELECTRICAL

PARTS

LIST

(cont)

Ckt

Grid

Tektronix

Serial/Model

No.

Loc

Part

No.

Eff

Disc

Description

INTEGRATED

CIRCUITS

(cont)

U241

G2

156-0039-00

Dual

15

MHz

J-K

master-slave

flip-flop

replaceable

b

SN7473N

U245

J2

156-0165-00

Dual

4-input

positive

nor

gates,

replaceable,

CONNECTORS

b

SN7425N

J100

131-0955-00

Receptacle,

electrical,

BNC,

female

J180

131-0955-00

Receptacle,

electrical,

BNC,

female

INDUCTORS

L192

Q3

276-0569-00

Core,

toroid

ferrite

L199

Q2

120-0382-00

Toroid,

14

turns

single

TRANSISTORS

Q115

K5

151-1022-00

Silicon,

FET,

selected

from

2N4392

Q122

K4

151-0325-00

Silicon,

PNP,

replaceable

b

2N4258

Q128

J6

151-0259-00

Silicon,

NPN,

selected

from

2N3563

Q160

I

6

151-0190-00

Silicon,

NPN,

replaceable

b

2N3904

or

TE3904

Q162

I

6

151-0190-00

Silicon,

NPN,

replaceable

b

2N3904

or

TE3904

Q170

H6

151-0325-00

Silicon,

PNP,

replaceable

b

2N4258

Q190

Q3

151-0362-00

Silicon,

PNP,

replaceable

b

SMT1105

Q195

03

151-0190-00

Silicon,

NPN,

replaceable

b

2N3904

or

TE3904

Q198

N3

151-0259-00

Silicon,

NPN,

selected

from

2N3563

Q230

M4

151-0341-00

Silicon,

NPN,

replaceable

b

2N3565

Q238

L4

151-0504-00

Silicon,

unijunction,

replaceable

b

2N4851

Q240

L4

151-0341-00

Silicon,

NPN,

replaceable

b

2N3565

Q242

J

1

151-0341-00

Silicon,

NPN,

replaceable

b

2N3565

Q280

F2

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q281

F

1

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q282

G2

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q283

G1

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q284

G1

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q285

G1

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q286

G2

151-0301-00

Silicon,

PNP,

replaceable

b

2N3907

Q320

S5

151-0515-01

Th ristor,

50

V,

8A,

replaceable

bv

2N4441

Q330

D6

151-0342-00

Silicon,

PNP,

replaceable

b

2N4249

Q340

B4

151-0342-00

Silicon,

PNP,

replaceable

b

2N4249

RESISTORS

R102

M4

323-0611-00

900

kΩ,

1/2

W,

17.

R103

M4

321-0617-00

111

kΩ,

1/8

W,

1%

R106

L4

323-0620-00

800

kΩ,

1/2

W,

17.

R107

L5

321-0423-00

249

kΩ,

1/8

W,

17.

R112

L5

321-0356-00

49.9

kΩ,

1/8

W,

17.

R113

L6

315-0103-00

10

kΩ,

1/4

W,

5%

R115

K6

315-0470-00

47

Ω,

1/4

W,

57.

R117

15

315-0101-00

100

Ω,

1/4

W,

5%

R118

K5

315-0182-00

1.8

kΩ,

1/4

W,

57.

R120

K5

315-0101-00

100

Ω,

1/4

W,

5%

R121

K5

315-0561-00

560

Ω,

1/4

W,

57.

R122

J4

315-0332-00

3.3

kΩ,

1/4

W,

57.

R123

K5

315-0223-00

22

kΩ,

1/4

W,

5%

R126

J5

315-0470-00

47

Ω,

1/4

W,

57.

R127

J5

315-0202-00

2

kΩ,

1/4

W,

57.

R130

J6

315-0102-00

1

kΩ,

1/4

W,

5%

R132

J6

315-0103-00

10

kΩ,

1/4

W.

57.

R135

311-1220-00

20

kΩ.

Var

R137

M6

315-0513-00

B010100

B029999

51

kΩ,

1/4

W,

5%

R137

M6

315-0513-00

B030000

51

kΩ,

(nominal

value),

selected

R139

M6

315-0103-00

10

kΩ,

1/4

W.

5%

R140

L5

323-0612-00

950

kΩ.

1/2

W.

IX

REV.

MAY

1974

3-4

DC

502

ELECTRICAL

PARTS

LIST

(cont)

1

7

Option

1

onl .

“

Furnished

as

a

unit

with

S235.

Ckt.

No.

Tektronix

Part

No.

Serial/Model

No.

Eff

Disc

Description

RESISTORS

(cont)

R152

J

5

315-0101-00

100

Ω,

1/4

W,

5%

R153

J5

315-0101-00

100

Ω,

1/4

W,

57.

R155

I

5

315-0331-00

330

Ω,

1/4

W,

57.

R158

H5

315-0102-00

1

kΩ,

1/4

W,

5%

R159

I

5

315-0102-00

1

kΩ,

1/4

W,

5%

R162

I

5

315-0102-00

1

kΩ,

1/4

W,

5%

R163

I

5

315-0102-00

1

kΩ,

1/4

W,

5%

R165

I

5

315-0561-00

560

Ω,

1/4

W,

57.

R167

I

5

315-0621-00

620

Ω,

1/4

W,

5%

R169

I

5

315-0561-00

560

Ω,

1/4

W,

57.

R172

H5

315-0152-00

1.5

kΩ,

1/4

W,

5%

R173

H6

315-0470-00

47

Ω,

1/4

W,

57.

R175

H5

315-0562-00

5.6

kΩ,

1/4

W,

57.

R177

K6

315-0562-00

5.6

kΩ,

1/4

W,

57.

R181

R2

317-0240-00

24

Ω,

1/8

W,

5%

R184

R3

315-0101-00

100

Ω,

1/4

W,

57.

R185

R2

315-0152-00

1.5

kΩ,

/4

W,

57.

R187

R3

315-0102-00

1

kΩ,

1/4

W,

5%

R188

R3

315-0101-00

100

Ω,

1/4

W,

5%

R189

Q3

317-0240-00

24

Ω,

1/8

W,

57.

R190

Q3

315-0102-00

1

kΩ,

1/4

W,

57.

R191

Q2

315-0203-00

20

kΩ,

1/4

W,

57.

R192

Q3

315-0221-00

B010100

B059999

220

Ω,

1/4

W,

57.

R192

Q3

315-0561-00

B060000

560

Ω,

1/4

W,

5%

R192

Q3

315-0221-00

B

0

10100

B049999

220

Ω,

1/4

W,

5%

R192

Q3

315-0561-00

B050000

560

Ω,

1/4

W,

57.

R193 P3

315-0101-00

100

Ω,

1/4

W,

57.

R194

P3

315-0332-00

3.3

kΩ,

1/4

W,

57.

R196

03

315-0303-00

30

kΩ,

1/4

W,

57.

R198

N2

315-0122-00

1.2

kΩ,

1/4

W,

57.

R200

G5

315-0181-00

180

Ω,

1/4

W,

57.

R203

G5

315-0242-00

2.4

kΩ,

1/4

W,

57.

R205

G6

315-0271-00

270

Ω,

1/4

W,

57.

R209

G5

315-0301-00

300

Ω,

1/4

W,

57.

R220

L3

315-0562-00

5.6

kΩ,

1/4

W,

57.

R222

L2

315-0562-00

5.6

kΩ,

1/4

W,

57.

R224

L2

315-0562-00

5.6

kΩ,

1/4

W,

57.

R226

L3

315-0301-00

300

Ω,

1/4

W,

57.

R230

L3

315-0562-00

5.6

kΩ,

1/4

W,

57.

R232

L3

315-0202-00

2

kΩ,

1/4

W,

57.

R235

2

C3

311-1342-00

500

kΩ,

Var

R238

L3

315-0100-00

10

Ω,

1/4

W,

57.

R240

L3

315-0102-00

1

kΩ,

1/4

W,

57.

R242

I1

315-0562-00

5.6

kΩ,

1/4

W,

57.

R244

I

1

315-0301-00

300

Ω,

1/4

W,

57.

R260

M3

315-0562-00

5.6

kΩ,

1/4

W,

57.

R261

M2

315-0242-00

2.4

kΩ,

1/4

W,

57.

R264

M2

315-0562-00

5.6

kΩ,

1/4

W,

57.

R265

M2

315-0242-00

2.4

kΩ,

1/4

W,

57.

R267

M2

315-0102-00

1

kΩ,

1/4

W,

57.

R271

H

1

315-0750-00

75

Ω,

1/4

W,

57.

3-5

REV.

MAY

1974

DC

502

ELECTRICAL

PARTS

LIST

(cont)

Ckt

Grid

Tektronix

No.

Loc

Part

No.

Serial/Model

No.

Eff

Disc

Description

^Standard

onl .

«Option

1

onl .

Furnished

as

a

unit

with

R235.

®

RESISTORS

(cont)

R272

H2

315-0750-00

R273

H2

315-0750-00

R274

H2

315-0750-00

R275

H2

315-0750-00

R276

H2

315-0750-00

R277

H2

315-0750-00

R280A

R280B

R280C

R280D

R280E

R280F

R280G

R280H

F

1

307-0357-00

R280J

R280K

R280L

R280M

R280N

R280P

R282

I

2

315-0151-00

R283

I

2

315-0151-00

R284

I

2

315-0151-00

R290

M2

315-0301-00

R292

M2

315-0301-00

R302

C5

307-0107-00

R304

C5

315-0332-00

R305

D5

311-1408-00

R306

D5

315-0302-00

R307

1

305-0621-00

XB050000

R307

2

305-0621-00

XB040000

R308

C5

315-0152-00

R310

*

B5

306-0560-00

B010100

R3

10

B5

306-0121-00

B050000

R

310

B5

306-0560-00

B010100

R310

B5

306-0121-00

B040000

R320

R5

316-0102-00

R322

B5

308-0463-00

R325

B5

315-0162-00

R327

B5

321-0260-00

R328

B5

321-0231-00

R330

C5

315-0161-00

R334

D5

321-0256-00

R335

D5

321-0308-00

R340

B4

315-0202-00

R344

D5

321-0286-00

R345

C5

321-0308-00

R350

A5

305-0101-00

B010100

R350

A5

306-0560-00

B050000

R350

A5

305-0101-00

BO

10100

R350

A5

306-0560-00

B040000

SWITCHES

S100A

M4

S100B

M4

260-1353-01

S200

K3

105-0406-00

S210

M3

S220

M3

260-1425-00

S235

C4

B049999

B039999

B049999

B039999

75

Ω

,

1/4

w,

5%

75

Ω

,

1/4

w,

5%

75

Ω,

1/4

w,

5%

75

Ω,

1/4

w,

5%

75

Ω,

1/4

w,

5%

75

Ω,

1/4

w,

5%

300

Ω

1

kΩ

300

Ω

1

kΩ

300

Ω

1

kΩ

3°0

Ω

Thick

fil

?

sectlon

divider

1

kΩ

300

Ω

1

kΩ

300

Ω

1

kΩ

300

Ω

1

kΩ

150

Ω

,

1/4

w,

5%

150

Ω,

1/4

w,

5%

150

Ω,

1/4

W,

5%

300

Ω,

1/4

W,

5%

300

Ω

,

1/4

W,

5%

5.6

Ω

,

1/4

W,

5%

3.3

kΩ

,

1/4

W

,

5%

1

kΩ,

Var

3

kΩ,

1/4

W,

5%

620

Ω,

2

W,

5%

620

Ω,

2

W,

5%

1.5

kΩ,

1/4

W,

5%

56

Ω,

2

W,

10%

120

Ω,

2

W,

10%

56

Ω,

2

W,

10%

120

Ω,

2

W,

10%

1

kΩ,

1/4

W,

10%

0.3

Ω,

3

W,

WW,

1%

1.6

kΩ,

1/4

W,

5%

4.99

kΩ,

1/8

W,

1%

2.49

kΩ,

1/8

W,

1%

160

Ω,

1/4

W,

5%

4.53

kΩ,

1/8

W,

1%

15.8

kΩ,

1/8

W,

1%

2

kΩ,

1/4

W,

5%

9.31

kΩ,

1/8

W,

1%

15.8

kΩ,

1/8

W,

1%

100

Ω,

2

W,

5%

56

Ω,

2

W,

10%

100

Ω,

2

W,

5%

56

Ω,

2

W,

10%

X10

Pushbutton,

ATTENUATOR

X5

Actuator

assembl ,

MEASUREMENT

INTERVAL

Push,

START

RESET

REV.

MAY

1974

3-

Tektronix DC 502 User manual

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