
[
[
[
[
[
l
l
l
l
[
308 Service
LIST
OF
ILLUSTRATIONS
(cont)
Figure
No.
3-1
Page
E
xamp
le
of
block-structured
routines
in
the
308 . . . . . . . . . . . . . . . . . . . . . . . 3-2
3-2
Memory
allocat
ion
map
for
the
308
...
3-3
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3
-10
3-
11
3-12
3-13
3-14
3-15
3-16
3
-1
7
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
@
Si
mp
li
fied
diagram of
the
308 . . . . . . . 3-5
Simp
lifi
ed
diagram
of
the
parallel data
i
nput
circuit
......
..
...
.
.....
..
. 3-8
E
quivalent
circuit of one chann
el
of
the
P6451
data
acquis
iti
on
probe.
. . . . . . . 3-9
S
implifi
ed
diagram
for
one
channel
of
the
samp
l
e/
Iatch stage . . . . . . . . . . . . . . . 3-9
Simpl
if
iedtiming
di
agram
of
sample/
l
atch
stage
. . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Si
mp
lified diagram
of
the
word
recognizer
circu
it
.
.......................
3-12
Asy
nc
filter
timing
diagram
.....
.
...
3-14
Simpli
fied
diagram
of
the
parallel
acquisiti
on
me
mor
y and
trigger
delay
c
ir
cu
it
s
..
..
....
.
............
. . 3-16
Simp
li
fied
timing
diagram
for
data
acqu
isiti
on
sequence
.............
3-17
Si
mp
li
fied
diagram
ofthetime
base
circu
it 3-20
S
implifi
ed
diagram
of
the
serial
/s
ign
ature
input, si
gnature
ge
ner
ator, and seri
al
data
acqu
isiti
on
circuits
. . . . . . . . . . . . . . . 3-21
Simp
li
fied
diagram
of
the
vari
able
de
lay
c
ir
cuit and its
timing
..
.....
.......
3-23
Tim
ing
diagram
of
the
gating
logic
stage 3-24
Simp
li
fied
diagram
of
the
CRC
ge
ne
rator
stage.
. . . . . . . . . . . . . . . . . . . . . . . . 3-26
Asynchronous
mode
instruction
format
3-27
Sync
h
ronous
mode
instructi
on
format
3-27
Status
in
format
ion
format
. . . . . . . . . . 3-28
Typ
ical
data
bl
ock
f
or
a
USART.
. . . . . 3-28
USART
com
mand
instruction
format
..
3-29
Simpl
i
fied
diagram
of
the
MPU
and key
board
circuits.
. . . . . . . . . . . . . . . . . . 3-30
Simp
l
ified
diagram
of
the
disp
l
ay
contro
l
circuit
. . . . . . . . . . . . . . . . . . . . . . . . 3-32
Timin
g diagram of
the
display
timing
generator
stages . . . . . . . . . . . . . . . . 3-33
Simp
lified
diagram
of
the
CRT
ci
rcuit
..
3-35
Si
mp
l
ified
diagram
and
waveforms
of
the
hori
zonta
l sweep
generator
. . . . . . . . . 3-36
S
implifi
ed
diagram
of
the
power
supp
ly
circu
it
. . . . . . . . . . . . . . . . . . . . . . . . 3-38
Figure
No.
3-28
4
-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4
-1
2
4
-1
3
4
-1
4
4-15
4
-1
6
4
-1
7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
Page
Representation
of
inverter
stage
and
idealized
waveforms
. . . . . . . . . . . . . . 3-
40
Diagnostic
0
keyboard
code
. . . . . . . . 4-5
Diagnostic
test
setup
. . . . . . . . . . . . . 4-6
Test
setup
for
check
ing
minimum
external
clock
per
iod . . . . . . . . . . . . . . . . . . . . 4-8
Test
waveform
for
minimum
external
clock
period
. . . . . . . . . . . . . . . . . . . . 4-9
Test
waveforms
for
minimum
samp
le
interv
al
and mini
mum
data
pulse wi
dth.
4-11
Test
waveforms
for
word
recognizer
filter
4-13
Test
waveforms
for
minimum
word
r
ecogn
izer pul
se
wi
dth
............
4
-1
5
Test
setup
for
trigger
de
lay
counter
...
4-17
Adjusting
pul
se
generators
outputs
for
trigger
delay
counter
check
.........
4
-1
8
Adjust
ing pul
se
generator
ou
tput
s
for
si
gnature
acquisi
tio
n
check
.
.....
.
..
4-19
Test
setup
for
seri
al
acqu
isit
ion
ch
eck
4-22
Test
setup
for
adjusting
clock
delay
and
si
gnature
data
delay
. . . . . . . . . . . . . . 4-27
Test
waveforms
for
clock
de
l
ay
adj
ustment,
ext
erna
l
trigger,
and
signature
data
de
l
ay
. . . . . . . . . . . . . . 4-28
Test
setup
fo
r
adjust
in
g
externa
l
trigger
delay
. . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Test
setup
for
adjust
ing i
nput
capac
i
tance
4-33
Test
waveforms
f
or
adjust
in
g
inpu
t
capac
i
tance
. . . . . . . . . . . . . . . . . . . . 4-34
Test
setup
for
adjust
ing
sig
natur
e
data
de
lay . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Di
agnost
ic
5
reference
pattern
. . . . . . . 5-4
Circuit
board
locations
...
..
.......
5-5
Co
l
or
code
for
resistors
and
capacitors
5-7
Semiconductor
lead
configurat
i
ons
. . . 5-8
Multi
-co
nnector
holder
orientation
. . . . 5-9
Keyboard
remova
l
.....
.
..........
5-13
Side
panel and
circu
it
board
remova
l . . . 5-14
308
top
view . . . . . . . . . . . . . . . . . . . 5-15
Power
switch
actuation
linkage
......
5-16
CRT
c
ircuit
board
re
moval
details
. . . . 5-17
Pin
con
n
ector
repl
acement
.....
...
. 5-21
iii