Tektronix DC 501 User manual

IISI STFiUCTI OIM
IVIAIMUAL.
Tektronix, Inc. P.O. Box 500 Beaverton, Oregon 97005 Phone: [phone] Cables: Tektronix
672
070-1339-00

WARRANTY
All TEKTRONIX instruments are warranted against
defective materials and workmanship for one year. Any
questions with respect to the warranty should be taken up
with your TEKTRONIX Field Engineer or representative.
All requests for repairs and replacement parts should be
directed to the TEKTRONIX Field Office or representative
in your area. This will assure you the fastest possible
service. Please include the instrument Type Number or Part
Number and Serial Number with all requests for parts or
service.
Specifications and price change privileges reserved.
Copyright ©1972 by Tektronix, Inc., Beaverton, Oregon.
Printed in the United States of America. All rights reserved.
Contents of this publication may not be reproduced in any
form without permission of Tektronix, Inc.
U.S.A. and foreign TEKTRONIX products covered by U.S.
and foreign patents and/or patents pending.
TEKTRONIX is aregistered trademark of Tektronix, Inc.

DC 501
Circuit Description
SECTION 3SERVICING INFORMATION
Miustment qf Internal Controls
Electri^l Parts Llst
M^hanical ;.Patts' List

OVEmOW MH?
DISPLAY TIME
MEASUREMENT INTERVAL
•ISSC
START
otfr:STOPj
ATTEN
1MST-2t«>r
DC 501 roOMHi COUNTER
TEKTWONm#
DC 501 100 MHz Counter
DC 501

Section 1—DC 501
OPERATING INSTRUCTIONS
DC 501 General Description
The DC 501 100 MHz Counter measures frequency from
10 Hz to 100 MHz, and totalizes (counts number of events)
from 0to 10’ at amaximum rate of 100 MHz. Seven
7-segment light-emitting diodes (LED's) provide avisual
numerical display. The decimal point is automatically
positioned and leading zeros (to the left of the most
significant digit or decimal point) are blanked. Digit
overflow is indicated by afront-panel LED. Signals to be
counted can be applied via afront-panel BNC connector
into an impedance of 1MO and 20 pF or via the rear
connector into an impedance of about 50 Oand 20 pF.
The DC 501 is designed to operate in aTM 500-Series
Power Module only.
Preparation
The DC 501 is ready for use as it is received. To install,
align the upper and lower rails of the DC 501 with the
plug-in compartment tracks of the power module, and
insert it fully. To remove, pull the release latch to disengage
the DC 501 from the power module. Connect the power
module cord to asuitable line-voltage source.
Basic Operation NOTE
Refer to the Controls and Connectors pullout page.
Also, additional information is given later in this
section.
Display Check. Press the RESET button to check the 7
character segments of each digit; the numerical display
should be arow of eights. To check the decimal point
position and the units indicators, set the MEASU REM ENT
INTERVAL switch as follows:
Switch Position Numerical Display Units
.01 SEC .0000 MHz
.1 SEC .00000 MHz
1SEC .000 kHz
10SEC .0000 kHz
MANUAL 000
In the MANUAL position, no decimal point will be
displayed. Press the START button and check that the
GATE indicator lights, then release the button (STOP) and
check that the GATE light goes out. To check the
OVERFLOW indicator, set the MEASUREMENT INTER-
VAL switch to 10 s, the INPUT switch to EXT, and apply a
15- or 20-MHz signal to the INPUT connector. The length
of time adisplay can be held is determined by the
DISPLAY TIME control, and will be discussed in the next
few paragraphs.
Frequency Measurements.The DC 501 provides direct
measurement of the average frequency of signals from
about 10 Hz to 100 MHz. The input sensitivity is 300 mV
peak to peak, so select the proper attenuation (XI, X5,
X10, or X50) for the given signal. Other input character-
istics are given on page 1-3.
The input signal must not exceed 500 volts.
Set the INPUT switch to EXT and apply asignal to the
INPUT connector. Set the MEASUREMENT INTERVAL
switch to the .01 SEC position and observe the numerical
readout display. Adjust the TRIGGER LEVEL control for
astable reading. The zeroes leading the most significant
digit in the display should be blanked. Then turn the
MEASUREMENT INTERVAL switch to the position that
gives the desired reading. Generally, use the shorter
measurement intervals for high-frequency, low-resolution
measurements and longer intervals for measurements re-
quiring ahigh resolution. For instruments having the
Automatic Gate option, the measurement interval is selec-
ted automatically when the MEASUREMENT INTERVAL
switch is set to the AUTO position.
NOTE
The OVERFLOW indicator can be lit for high-
resolution measurements, allowing the frequency to
be indicated to 0. 1Hz. Refer to the Electrical
Characteristics at the end of this section for resolu-
tion and accuracy at each position of the MEASURE-
MENT IN TER VALswitch.
The display is updated at a rate determined by the
DISPLAY TIME control. Each time asample of the input
signal is taken, the GATE light will flash and the new

Operating Instructions—DC 501
reading will be displayed. To change the display time,
which is continuously variable from about 0.1 second to 10
seconds, or to hold adisplay indefinitely, turn the
DISPLAY TIME control.
Totalizing (Counting Number of Events). The DC 501
will display the accumulated number of pulses applied to
the External or Internal input circuit up to 9,999,999
pulses. Input signal rate should not exceed 100 MHz.
Before applying the signal, set the MEASUREMENT
INTERVAL switch to MANUAL. Apply the signal and
push the START button. The GATE indicator will light and
the progressing count will be displayed. Adjust the ATTEN
and TRIGGER LEVEL controls as necessary to obtain a
steady count. To stop the counting, release the START
button. The GATE light will go out and the displayed
count will be held. The displayed count will continue by
pressing the START button again. The counter can be reset
to zero at any time by pushing the RESET button.
Signal Connection
Coaxial cables and probes offer very convenient means
of connecting the signals to the front-panel INPUT BNC
connector. These devices are shielded to prevent pickup of
electrostatic interference. A10X attenuation probe not
only reduces the size of the input signal, but is also presents
ahigh input impedance to allow the circuit under test to
perform very close to normal operating conditions.
Input and output data access to the DC 501 is made
via the plug-in connector contacts at the rear of the main
circuit board. Fig. 1-1 identifies the contacts and their
associated input/output assignments. An optional multi-pin
connector, to which these data can be hard-wired to
provide external access, is available to install on the rear
panel of the power module.
Input Attenuation and Trigger Level Adjustment
Signals to be counted may have awide variety of shapes
and amplitudes, many of which are unsuitable to drive the
counting circuits. Because of this, the signal is first passed
through an attenuator, then applied to asignal-shaping
circuit which converts it to rectangular pulses of uniform
amplitude. This circuit includes areference level adjustable
between +and —2volts to which the incoming signal is
compared, allowing the 300-millivolt sensitivity window of
the signal-shaping circuit to be adjusted to aconvenient
amplitude on the incoming waveform (see Fig. 1-2).
Obtaining asteady, reliable reading is dependent upon the
proper selection of input attenuation and proper adjust-
ment of the TRIGGER LEVEL control.
Generally, the best point on awaveform for triggering
the counter is where the slope is steep and therefore usually
free 0^no'se O” as'ne-'vave signal, fo’' examp'e, the
steepest slope occurs at the zero-crossing point. Noise
pulses or other signal components of sufficient amplitude
to produce unwanted trigger pulses will cause an erratic or
incorrect count. Fig. 1-2 shows the TRIGGER LEVEL
control adjusted to avoid error. In critical measurement
applications, monitor the incoming signal with atest
oscilloscope.
Measurement Interval and Display Time Controls
The MEASUREMENT INTERVAL switch selects the
time interval (also called gate time) during which the DC
501 counts. The internal time-base circuit derives gate
times from an accurate 1-MHz reference signal to make
frequency measurements. These gate times are 0,01 s, 0.1 s,
1s, or 10 s. The measurement interval selected determines
the measurement range and resolution. Also, the displayed
decimal point is positioned correctly and the correct
measurement units (MHz or kHz) are indicated for the
corresponding switch position.
Contact Assignment
28B Second decimal point (D2) output.
27A Internal scan clock disable input.
27B MHz light output.
26A Reset input/output.
25A TS0(Time Slot Zero) output.
25B External scan clock input.
24B Internal scan clock (2 kHz) output.
23B Overflow output.
22B MSD (most significant digit)
20B 8
20A 4BCD output, serial by digit.
21B 2
19A 1
19B Data good output.
17A Signal input ground.
16A Signal input.
Fig. 1 1 .Input/Output assignments of p!ug-in connector contacts.
1-2

Operating Instructions—DC 501
Fig 1-2. Two examples of triggering circuit output showing how
proper adjustment of TRIGGERING LEVEL control can avoid an
erroneous count.
The DISPLAY TIME control sets the length of time a
measurement can be held in the counter and displayed. The
HOLD detent position allows ameasurement to be held
indefinitely, or until the counter is reset to zero by the
front-panel RESET button.
Count; Register capacity, 10’; totalizes events accumu-
lated between start/stop commands from front-panel
button.
INPUT
Frequency, 10 Hz to 100 MHz; sensitivity, 300 mV peak
to peak; triggering level, adjustable +2V; attenuator, XI,
X5, XIO, or X50; maximum input voltage, 500 V(DC -i-
peak AC, or peak to peak AC) at 1kHz or less; impedance,
(EXT input), approx 1MO paralleled by about 20 pF
(INT input) approx 5012 paralleled by about 20 pF;
coupling, AC.
INTERNAL TIME BASE
Standard Option 1
Crystal Frequency 1MHz 5MHz
Stability (0°C to
-i-50°C), after 1/2
hour warm-up
Within 1part in
10®
Within 5parts
in 10’.
Long-term Drift 1part or less in
10^ per month
1part or less in
10’ per month
Accuracy Adjustable to
within 1part in
10’
Adjustable to
within 5parts
in 109.
INTERNAL MEASUREMENT INTERVAL.
Selectable in decade steps.
Optional Features
Option 1-0.5 P/M 5MHz Crystal Oscillator. The DC
501 can be ordered with atemperature-compensated
crystal oscillator to provide ahighly stable and precise
internal time base TMHz clock. This option includes a
divide-by-five 1C counter to provide the proper output.
Option 2-Automatic Gate Control and Readout Scaling
Circuit. This circuit automatically selects the 0.1 -, 1-, or
10-second measurement interval to display the largest
number of digits without overflow, and provides the
appropriate scaling of decimal-point and units lights to
produce the correct display. If overflow indication occurs,
the input signal is >100 MHz and the overflow digit is a
"1".
Measurement
Interval Display Units Resolution
10 ms 000.0000 MHz 100 Hz
100 ms 00.00000 MHz 10 Hz
1s0000.000 kHz 1Hz
10s 000.0000 kHz 0.1 Hz
Manual 0000000 (adds to displayed number)
Accuracy, within ±;±time-base accuracy.
total count
DATA PRESENTATION
Visual numerical readout, seven 7-segment LED with
automatically positioned decimal point; units, LED indi-
cates kHz or MHz; overflow, LED indicates that readout is
exceeded; gate, LED indicates open gate.
Electrical Characteristics
MEASUREMENT RANGES AND ACCURACY
Frequency: 10 Hz to 100 MHz; 0.1-s to 10-s counting
gate time; displays kHz or MHz units with positioned
decimal point. Accuracy, ±1 count ±time-base accuracy.
DATA INPUTS and OUTPUTS
Available via plug-in connector to 50-pin connector at
rear of Power Module. Input lines are available for signal
input, and internal and external scan clock control. Output
lines are available for BCD output (serial-by-digit), and to
indicate status of timing, data good, reset, scale, decimal
point and overflow.
1-3

19B 27A25B 24B 19A, 20A, 20B, 21B
J100
IINPUT iATTEM-
16A>-
SIGNAL-SHAPING
0115
CIRCUIT
0160
U135
0122 U150A U1606
0128 U150B 0170
TRIGGER
LEVEL I'
DISPLAY
TIME.
IDISPLAY TIME |
CONTROL
0230 0238
0240
1-MHz CLOCK
Y200
U200A U200C
U200B U200D
OPTIONAL
1-MHz
CLOCK
Y201
U201
IJ
IJ
REGULATED
SUPPLIES
+20 V>-
-20 vV
1U300 1
>1
1
1
1
s1U320 4-f
^1
.1
*1
10330
'10340
+15 V|
REG
GATE GENERATOR
U220A U222A
U220B U222B
CONTROL SIGNALS
U230A
U230B
U230C
U230D
U246D
GATE
LATCH
CLEAR
CLEAR
RESET
DECADE
DIVIDER
UNITS
U209
U210
U211
U212
U213
U214
U215
.01 SEC
.1 SEC
1SEC
10 SEC
MEAS
INTER
SWITCH
S200
•+5 VREG
—5.2 VREG
-10 VREG
.1 S- -
1S—
IDS —-
MSD —
OPTIONAL
AUTO-GATE
&
READOUT SCALING
CIRCUIT
10” DCU STORAGE
U165A REGISTER
U1656 U250
U167 U251
U169 U252
U253
10' DCU U254
U235 U255
U256
10' DCU
U236
10^ DCU
U237
10" DCU
U238
10' DCU
U239
10" DCU
U240
OVERFLOW]
IREGISTER
U241A
U241B
0242
OVERFLOW
RESET
,U18
U181 U183 U185 U190
U19^
To Gate
’Generator
.To Display
Circuits
LEADING-ZERO
SUPPRESSION
&
IDECIMAL POINT
LOCATION
U245B
U246A
U246B
U260C
U263B
INVERTERS
U246C U267D
U267A U267E
U267B U267F
U267C
ANODE
VOLTAGE
ENABLE
0280 0283
0281 0284
0282 0285
0286
Fig. 2-1. DC 501 Block Diagram.
Theory
of
Operation—
DC
501

Theory of Operation—DC 501
THEORY OF OPERATION
Introduction
This section of the manual contains an electrical
description of the circuits in the DC 501 100 MHz
Counter. Ablock diagram is shown in Fig. 2-1, and
complete schematics are given on pullout pages in the
Servicing Information section.
BLOCK DIAGRAM DESCRIPTION
Signals to be counted are applied via the EXT INPUT
connector or via pin 16A at the rear interface, attenuators,
and acoupling capacitor to the signal-shaping circuit. This
circuit conditions the input signal and produces an output
suitable to drive the first decade counter.
The time-base circuit generates the signals which deter-
mine when the counter is allowed to count (GATE), when
the readout display is updated (LATCH), and when the
counter is cleared or reset (CLEAR, CLEAR, or RESET).
The generation and the time relationship between these
signals are determined by the front-panel MEASUREMENT
INTERVAL, DISPLAY TIME, Manual Gate START/STOP,
and RESET controls.
The decade counter units receive the shaped input signal
when the gate is "open”. Each DCU corresponds to one of
the display LED's. Immediately upon closure of the GATE,
the LATCH locks the sample taken into the storage register.
If the sample taken exceeds the seven available display
digits, the excessive count spills over and is indicated by the
OVERFLOW LED on the front panel. Before anew sample
of the input signal is taken, the time-base circuit sends in a
CLEAR pulse to reset all the DCU's to zero.
The multiplexing circuit scans the latches of the storage
register at a2-kilohertz rate, enabling each latch and its
corresponding display LED sequentially on atime-shared
basis. The BCD output of the storage register is decoded
and the correct combination of LED segments is lightfed
to display any digit between 0and 9. Also, the decoder and
display-multiplexing circuit provides leading-zero suppres-
sion if the display is within the display-register capacity.
Decimal point location is afunction of the MEASURE-
MENT INTERVAL switch.
CIRCUIT DESCRIPTION
Input Circuit
Signals to be counted are applied via front-panel INPUT
connector J100, or via the internal input at pin 16A at the
rear interface, to the attenuators. The attenuators are
frequency-compensated voltage dividers consisting of resis-
tors R102-R107 and capacitors C102-C107. Switches
S100A and S100B allow front-panel selection of XI, X5,
X10, or X50 attenuation of the input signal. Cl 10 provides
AC coupling.
FET source follower Q115 and emitter follower Q122
present ahigh impedance to the input signal. The diodes in
the base circuit of E. F. Q128 form aseries-limiter and
clamping network, which reduces the input signal to limits
suitable for driving the shaping circuits. The clamping
diodes limit the voltage at the emitter of Q128 to a
dynamic range of about 1.2 volts.
U150B, an OR gate integrated circuit with push-pull
outputs, is connected as aSchmitt trigger. It shapes the
input signal into asquare wave. Its "hysteresis window" is a
width of about 200 mV. The output changes states when
the signal voltage passes through the upper threshold, then
reverts to its original state when the signal voltage passes
through the lower threshold. For this reason, an input
signal smaller in amplitude than the width of the hysteresis
window cannot activate the counting circuits.
The quiescent level at the input of U150B can be
adjusted to overcome some of the triggering difficulties
arising from various input-signal shapes and frequencies.
Integrated -circuit operational amplifier U135 and its associ-
ated discrete components are connected as avoltage
follower. TRIGGER LEVEL potentiometer R135 selects a
voltage between ground and about —2 volts and applies it
to pin 3of U135. This level is then established at pin 2, and
hence, the input of U150B, through the action of the
operational amplifier.
The output of U150B is applied to U150A, whose
push-pull outputs drive Q160 and Q162, which are con-
nected as adifferential pair. This circuit provides alevel
shift to TTL level, and further shapes the signal to be
counted. Awaveform with fast rising and falling edges is
produced at the collector of Q160. CR165 limits the
amplitude of the count signal to 5volts, clamping the
2-2

Theory of Operation—DC 501
negative-going portion of the signal to ground. The signal is
then passed through emitter follower Q170 to U160B,
where it receives afinal phase inversion (to correspond with
the input signal) and becomes the decade input.
Time Base and Control Circuit
General. The time base and control circuit generates the
following control signals:
1.
GATE. The GATE output determines when the
counter is allowed to count. When this output level is HI,
the gate is "open" and the counter counts the input signal.
While the gate is open, the front-panel GATE indicator is
lit. The time during which the gate is open is determined by
the MEASUREMENT INTERVAL switch setting.
2.
LATCH. This output determines when the meas-
urement made by the decade counter units is transferred to
the storage register latches, permitting the readout display
to be updated. In the normal gate mode (one of four
selectable gate intervals), or in the optional AUTO gate
mode, the LATCH goes HI for 1psec immediately upon
closure of the GATE. In the manual gate mode, the LATCH
is held HI to allowcontinuous updating. Also, the LATCH
is activated by the RESET signal.
3.
CLEAR and CLEAR. These outputs determine
when the counter is to bereset tozero. Just before the
GATE opens, CLEAR and CLEAR are activated for ashort
duration (less than 2psec), resetting the DCU's to zero
before anew count is taken. Also, CLEAR and CLEAR are
activated by the RESET signal.
4.
RESET. This output is used to reset all of the
counting and dividing circuits in the DC 501, and to
enable all of the LED-readout character segments for a
segment check. The active level is LO, produced by aswitch
closure to ground (front-panel RESET switch, or between
the detent positions of the MEASUREMENT INTERVAL
switch).
1MHz Clock. Aprecise one-megahertz clock provides
the reference for operation of the gate-generating circuits.
The output of crystal oscillator Y200 is adjustable by C201
to exactly one megahertz. The four parts of U200 form a
shaper-buffer stage to produce square-wave clock pulses and
to isolate the oscillator from the 1-MHz output line.
NOTE
An optional 1MHz dock is available, using avery
stable 5MHz crystal oscillator and adivide-by-five
counter. This combination is shown on the schematic
as Y201 and U201.
Time Base Decade Dividers (DDU's). The DDU's consist
of seven cascaded divide-by-ten counters, U209 through
U215. They produce four gate times, 0.01 sec, 0.1 sec,1 sec
and 10 sec, which are made available via the MEASURE-
MENT INTERVAL switch to the gate generator to establish
the precise time interval the GATE is open. The 1MHz
clock signal is applied to pin 14 of U209, whose output is
connected to the input of the subsequent decade. Each
decade is clocked with anegative-going transition. The
DDU's are reset by aCLEAR pulse, which places a0count
in U209 and a9count in each subsequent decade.
Gate Generator. The gate generator produces the GATE
control signal and initiates the CLEAR, CLEAR, and
LATCH pulses. The generating portion consists of U220A,
U222A, U220B, and U222B. The display time control
portion consists of Q230, Q238, and Q240. The circuit will
be described first in the normal gate mode (MEASURE-
MENT INTERVAL switch in one of the four gate time
positions).
Assume that the T^j conditions are as given in Fig. 2-2.
The Qoutputs of U220A, U222A, U220B, and U222B are
all LO. Q230 is off and the emitter of Q238 rises as C235
charges. At T^ ,Q238 reaches its firing potential and
discharges the capacitor. This results in ashort-duration LO
pulse on the direct s^ input (pin 2) of U220A, forcing its Q
output HI and its Qoutput LO. With two HI inputs on
NAND gate U230A, its output goes LO and the output of
NOR gate U230C goes HI, producing the CLEAR and
CLEAR control signals. The next HI-to-LO transition from
the 1-MHz clockJT^) toggles U222A, causing its Qoutput
to go HI and its Qto go LO. With aLO applied to one of its
inputs, U230A reverts to its original condition, terminating
the CLEAR and CLEAR pulses. The DDU's then start
counting from their 0999999 reset condition.
At the end of a10-microsecond delay (time for the
DDU's to count the first digit, plus apropagation delay), a
negative transition from the DDU's via the MEASURE-
MENT INTERVAL switch toggles U220B. This corresponds
to Tg in Fig. 2-2. U220B's Qoutput goes HI and its Q
output goes LO. The next negative transition from the
1-MHz clock (T^) toggles U222B, causing its Qoutput to
go Hi (GATE open) and its Qoutput to go LO (supplying
current to the front-panel GATE indicator LED, CR225).
The GATE signal is also applied to the base of 0230,
saturating the transistor and preventing C235 from'
charging.
The GATE remains open (HI) for the time duration
selected by the MEASUREMENT INTERVAL switch. At
the end of this time, which corresponds to Tg in Fig. 2-2,
another negative transition from the DDU's toggles U220B.
U220B's Qoutput goes LO and its Qoutput goes HI. The
next negative transition from the 1-MHz clock (T^) toggles

Theory of Operation—DC 501
Fig. 2-2. Time Base generator normal gating mode ladder diagram.
U222B, causing its Qoutput to go LO, closing the GATE.
Simultaneously, the Qoutput goes HI, removing current
from the GATE indicator LED.
When the GATE output goes LO, the negative transition
toggles U220A, switching QLO and QHI. Now NAND gate
U230D has two HI inputs, placing aLO at the input of OR
gate U230B and activating the LATCH control signal (HI
state). One microsecond later (T.^), anegative edge from
the 1-MHz clock toggles U222A, switching its outputs and
placing aLO on the input of NAND gate U230D. U230D
reverts to its original condition, terminating the LATCH
signal.
The display time begins when the GATE signal ends
(Tg). When 0230 turns off, C235 begins to charge through
R232-R235 toward the Vcc supply. R235, DISPLAY
TIME, provides an adjustable time constant to vary the
display time from about 0.1 second to about 10 seconds.
When the DISPLAY TIME control is fully clockwise
(HOLD detent position), S235 opens, and C235 stops
charging. When S235 is closed and C235 charges
sufficiently to bring Q238 to its firing potential (T.|), the
display time ends and the next GATE-opening sequence
begins.
Manual Gate. The manual mode of operation is selected
by placing the MEASUREMENT INTERVAL switch in the
MANUAL position. The switch closure to ground (cam 5of
the switch) places aLO on the set inputs of U220B and
U222A, and aLO on the clear input of U220A. This forces
the Qoutputs of U222A and U220B HI, and the Qoutput
of U220A LO. With both inputs of U230D held HI, the
LATCH output is held HI, allowing the counter to update
the display continuously. The GATE is opened when the
front-panel START button is pushed in, opening S210 and
applying aHI to the clear input of U222B. As before, the
GATE-open condition is HI at the Qoutput of U222B. The
GATE is then closed when S210 is set to STOP (button
out). To reset the counters in the manual mode, the RESET
button mustbe pushed to activate the CLEAR, CLEAR,
and RESET control signals.
Automatic Gate (For Instruments Having Option 2). The
automatic gate mode is selected by placing the MEASURE-
MENT INTERVAL switch in the AUTO position. The
output of the automatic time base circuit is connected to
the gate generator via contact 1of the switch. Contact 2
opens to enable the readout-scaling circuit. The automatic
gating cycle begins with the CLEAR pulse, which occurs
when Q238 reaches its firing potential, as discussed for the
©2-4

Theory of Operation—DC 501
normal gate mode (gate generator). The CLEAR pulse
resets the time-base DDU's and the counter circuit DCU's,
resulting in aLO applied to the toggle inputs of U180A,
U180B, U181A, and U181B. This establishes the following
initial conditions: LO at both inputs of U183A, LO at both
inputs of U183D, HI at both inputs of U185C, aLO and a
HI at the inputs of U185B, and HI at both inputs of
U185A. The resulting LO at the output of U185A is
applied to the toggle input of U220B in the gate generator.
The next HI-to-LO transition from the l-MHz clock will
toggle U222B and open the GATE. Just before the GATE
opens, however, U183B has two HI inputs, producing aLO
to clear U180A, U180B, U181A, and U181B. The U183B
output then returns to the HI state less than amicrosecond
later when the GATE opens.
The GATE closes at the end of a0.1 -second or a
1-second interval if the display register is approaching its
capacity, or at the end of a10-second interval. The toggle
input to U181A is also the toggle input to the 10® DCU,
which corresponds to the most significant digit of the
display. The gate-closure sequence is as follows:
After about 80 milliseconds, aHI is applied from the
.1-sec DDU to U183A, which results in aHI applied via
U185C to NAND gate U185B for about 20 milliseconds. If
during that period LI181A is toggled by the MSD (most
significant digit), its Qoutput goes HI, causing U185A
output to go HI. At the end of precisely .1 second, a
HI-to-LO transition is input from the .1-sec DDU, which
results in the U185A output going LO, toggling U220B in
the gate generator. Then on the next HI-to-LO transition
from the 1-MHz clock, U222B is toggled, ending the GATE
interval.
If no MSD input is received during the .1 -second
interval, the process is repeated through the 1-second
interval, with U180B and U183D the active devices. The
.1-second logic cannot interfere with this process because of
the LO input at pin 1of U183A, which was established
when U180A was toggled at the end of .1 second. If no
MSD input is received during the 1-second interval, then the
negative transition received by U183C at the end of
precisely 10 seconds causes the U185A output to go LO,
initiating GATE closure.
When the GATE closes, the LATCH pulse toggles storage
registers U190A and U190B, transferring the 1-second and
10-second timing logic to the inputs of NAND-gate de-
coders U191A, U191B, and U191C. These devices provide
the proper readout scaling. If the GATE time was 0.1
second, CR192 andCR193 are turned on; 1second, CR191
and CR 195: 10 seconds, CR 190 and CR 194.
Counter Circuit
Decade Counter Units (DCU's). The 10° through 10°
DCU's are seven cascaded divide-by-ten counters. The first
decade counter is made up of four individual J-K flip-flops
to accept the high-speed decade input (up to 100 MHz),
and each subsequent DCU is asingle 1C. U165A, U165B,
U167, and U169 comprise the first (10°) decade counter,
and U235 through U240 make up the remaining six DCU's.
When the Jand Kinputs of U165B are HI (GATE open),
the counter is enabled. The input signal is applied to the
toggle input of U165B. On every tenth clock input counted
by the first decade counter, the output of U169 goes LO,
providing acarry signal which becomes the clock input for
the second decade counter. Each subsequent decade divides
by ten in asimilar manner. Four BCD output lines are
connected from each DCU to its associated storage-register
latch. When the CLEAR (HI) and CLEAR (LO) signals are
activated, all of the decade counters are reset to the
zero -count state.
Storage Register. The seven 1C latches (U250 through
U256) comprise astorage register which stores the corre-
sponding decade counter BCD output. The BCD output is
applied to the data inputs at pins 1, 5, 7, and 3(2°, 2\ 2^,
and 2^ bits respectively). The LATCH pulse is applied to
the data-strobe input at pin 2of each latch immediately
upon closure of the GATE or when the MEASUREMENT
INTERVAL switch is placed in the MANUAL position, as
described in the time base and control circuit. While the
LATCH input is HI, the logic levels at the data Inputs are
transferred to the associated BCD bit output to be scanned
by the multiplexing circuit.
Overflow Register. When the decade counters have
counted to 9,999,999, the counters are full. At the next
count, the 2^ output of U240 goes LO, providing atoggle
input to U241B. When this occurs, aLO is transferred from
pin 10 to pin 8of U241B, then when the LATCH pulse
ends (goes LO), U241A is toggled and the LO is transferred
to pin 13. When pin 13 of U241A goes LO, CR241 and
CR242 conduct. CR242 is an LED, and in its conduction
state gives afront-panel OVERFLOW indication.
In the Manual counting mode, OVERFLOW indication is
achieved via Q242 and CR244. The emitter of Q242 is
grounded by aswitch closure, then when pin 9of U241B
goes HI on the first overflow count, Q242, CR244, and
CR242 turn on.
U241 is reset by the CLEAR pulse. To prevent leading-
zero suppression during the overflow condition, the display-
controlling circuits are notified via U245A that the count is
in excess of that displayed by the LED readout.

Theory of Operation—DC 501
Decode and Display Multiplex
Scan Clock. The scan rate of the multiplexing circuit is
determined by the scan clock. The scan clock is composed
of U260B and U260D, which operate as afree-running
multivibrator at an approximate 2-kilohertz rate. The
scan-clock output is passed through NOR gate U260A,
which can also accept an externally applied scan clock
signal. Other input/output lines provide internal scan-clock
disable and internal scan clock output. The scan clock
drives an eight-state counter and astorage register for zero
suppression.
8Counter and Time-Slot Decoder. The divide-by eight
counter is made up of U262B, U263A, and U262A, which
are three halves of SN7474 type Dflip-flops. The output of
this counter drives U265, and SN74145 BCD-to-decimal
decoder. U265 provides eight output lines (designated TS^
through TS.^ in the schematics and in Fig. 2-3) to
simultaneously enable the output of each counter latch and
its corresponding display LED sequentially. For example,
when the TS.^ line goes LO, Q280 is turned on to supply
anode voltage to CR280 at the same time inverter U267C
applies aFll to pin 6of latch U256, enabling its output.
Operation in atime sequence allows the latches to share a
common set of output lines.
Seven-Segment Decoder and Display LED's. U270 is a
BCD-to-seven-segment decoder. It accepts the BCD output
of the latches, then supplies current to the appropriate
cathodes of the enabled LED to display the correct
number. The display LED's are CR280 through CR286.
When looking at the front panel of the DC 501, CR280
controls the numerical digit displayed at the far left (10®),
CR281 controls the second (10®), etc. Each LED has seven
segments, arranged so that acombination of lighted
segments forms anumber. When all of the segments are
lighted, an "8" is formed.
Leading Zero Suppression. Decoder driver U270 also has
azero-blanking feature which allows suppression of the
zeroes leading the most significant digit (MSD) in the
display. At TS^, aLO is applied to the direct-clear input of
U263B, the zero-suppression storage register. This sets
U263B to the zero-suppress state (Fll at pin 8), allowing the
Ripple-Blanking Input (RBI, pin 5) of U270 to be LO.
When the output of U265 advances to the next time slot
(TS.i ), the RBI of U270 remains LO for afew nanoseconds
due to propagation delays, which allows the first digit to
arrive from the latches while RBI is LO. If this first digit
being decoded is azero, the output to the display LED will
be inhibited and the Ripple Blanking Output (pin 4) will be
LO. If the digit is not azero, the outputs are enabled and
2-6

Theory of Operation-DC 501
RBO goes HI. The RBO is applied to the Dinput (pin 12)
of U263B and is transferred to the output when the next
scan-clock HI-to-LO transition occurs. Thus if the first digit
is azero, pin 5of U270 is held LO, inhibiting the output
until the first non-zero digit comes through the decoder.
When the first non-zero digit arrives, the outputs of U270
are enabled and the digit is displayed. Also, the RBO
output at pin 4is set HI, removing the RBI from pin 5 and
allowing all succeeding digits to be displayed through the
TS.^ sequence.
When the scan gets past the decimal point in the display,
or if the display overflows, any zeroes arriving at the
decoder should be displayed. This is achieved as follows;
TSg is inverted by U267E and applied through OR gate
U245B as aLO at the direct-set input of U263B. This holds
pin 5of U270 HI, preventing zero-blanking during theTS^,
TSg, and TS.^ time slots. The location of the decimal point
in the display is determined by the MEASUREMENT
INTERVAL switch. The proper information is applied via
the closed contacts of the switch to either NAND gate
U246A or U246B. Then either TS^ or TS^ is enabled to the
input of OR gate U245B via these NAND gates, setting
U263B to the non-blank state at the appropriate time. In
the case where the counter overflows, the HI output from
U245A is applied to U245B, setting U263B to the
non-blank state.
When the front-panel RESET button is pushed, RESET
goes LO, overriding the output of U263B, applying the
non-blank and lamp-test functions to the decoder. This
causes all seven segments in the display LED to be turned
on.
Input and Output Data. The following inputs and
outputs are available via the plug-in connector to external
equipment. See Fig. 1-1.
INT SCAN DISABLE: ALO applied to this line disables
the internal scan clock.
EXT SCAN: Provides input for an external scan clock.
INT SCAN CLOCK OUT; Provides output for the
internal scan clock.
TSj^: ALO is present on this output line in the TS^^ state
DATA GOOD: AHI is present on this output line when
anew reading is being transferred into the storage-register
latches.
OVERFLOW: This output is HI when the count
overflows.
RESET: This is adual-function input/output line. It
provides aLO output during reset, or can be used as an
external reset input.
Data Lines; 1, 2, 4, 8provide BCD output, serial by
digit, from the currently enabled storage-register latch.
Other data lines include aLO when the MHz light is on, and
aLO when the second decimal point is lit.
Regulated Power Supplies
The DC 501 operating power is obtained from the
power module mainframe and then electronically regulated
to provide stable supplies of +15 volts, +5 volts, -5.2 volts,
and —10 volts. The +15-volt supply, whose active device is
U300, provides the reference for the remaining supplies. Its
output is set to exactly +15 Vby adjustment of R305.
Integrated circuit U320 regulates the +5-volt supply, and
transistors Q330 and Q340 regulate the -5.2-volt and
-10-volt supplies respectively. The series-pass transistors
for these supplies are located in the mainframe, where they
can provide the proper heat dissipation.
2-7 @i

Section 3—DC 501
SERVICING INFORMATION
Symbols and Reference Designators
Electrical components shown on the diagrams are in the following units unless noted otherwise:
Capacitors =Values one or greater are in picofarads (pF).
Values less than one are in microfarads (/tF).
Resistors =Ohms (J2)
Symbols used on the diagrams are based on ANSI-Y32.2-1970-
Logic symbology is based on MIL-STD-806B in terms of positive logic. Logic symbols depict the logic function performed
and may differ from the manufacturer's data.
The following special symbols are used on the diagrams:
External Screwdriver adjustment.
External control or connector.
Clockwise control rotation in direction of arrow.
F’O circuit board
Refer to diagram number indicated in diamond.
Refer to waveform number indicated in hexagon.
Connection soldered to circuit board.
Connection made to circuit board with interconnecting pin.
Blue tint encloses components located on circuit board.
The following prefix letters are used as reference designators to identify components or assemblies on the diagrams.
AAssembly, separable or repairable (circuit board, etc.) LR Inductor/resistor combination
AT Attenuator, fixed or variable MMeter
BMotor QTransistor or silicon-controlled rectifier
BT Battery PConnector, movable portion
CCapacitor, fixed or variable RResistor, fixed or variable
CR Diode, signal or rectifier RT Thermistor
DL Delay line SSwitch
DS Indicating device (lamp) TTransformer
FFuse TP Test point
FL Filter UAssembly, inseparable or non-repairable (integrated
HHeat dissipating device (heat sink, heat radiator, etc.) circuit, etc.)
HR Heater VElectron tube
JConnector, stationary portion VR Voltage regulator (zener diode, etc.)
KRelay YCrystal
LInductor, fixed or variable
®3-1

ADJUSTMENT OF INTERNAL CONTROLS
Services Available
Tektronix, Inc. provides complete instrument repair and
adjustment at local Field Service Centers and at the Factory
Service Center. Contact your local TEKTRONIX Field
Office or representative for further information.
Test Equipment
For measurement of the power supply voltages, a20,000
ohms/volt VOM will give satisfactory measurements. For
example, Triplett 630 NA multimeter.
For 1-MHz frequency measurement, asecondary
frequency standard or other frequency source having a
stability of at least 5parts on 10^ (5 parts in 10^ if
measuring optional 5MHz crystal output) is recommended
for accuracy. Also recommended is atest oscilloscope with
abandwidth of at least 1MHz and astable triggering circuit
for frequency-comparison measurement.
Procedure
NOTE
The performance of this instrument can be check at
any temperature within the 0° Cto +50°Crange.
Make any adjustment at atemperature between
+20°C and +30°C (+68°Fand +86°F).
The DC 501 can be operated either fully installed in a
TM 500 Series Power Module or connected to aplug-in
extender (TEKTRONIX Part No. 067-0645-01).
Power Supply Checks and Adjustment. Connect the
voltmeter between the -M5-volt test point and ground.
Adjust R305 for areading of -M5 volts. Then check the
-i-5-volt, —5.2-volt, and -10-volt supplies to be within 5%.
NOTE
If the instrument is operated on the piug-in extender,
the +5-VOIt supply may not regulate.
Time-Base Frequency Check and Adjustment. Connect
the DC 501 1-MHz time base reference and the secondary
standard to the oscilloscope as shown. Adjust the oscillo-
scope to display several complete cycles.
To determine oscillator error, observe the rate of
horizontal drift of the displayed waveform. Waveform
moving to the right indicates that the time-base frequency
is <1 MHz; to the left, >1MHz. The period in seconds for
the waveform to move the width of one cycle is equal to
the frequency difference in parts in 10®. For example, if
the waveform drifts to the right at arate of one cycle's
width every 10 seconds, the time-base frequency is 0.1 part
in 10® low. Maximum allowable frequency difference is 1
part in 10® (5 parts in 10^ for the optional 5MHz crystal).
Adjust C201 for no drift.
Dispk
LEO rear
segment d
maticafly
point. Th<
are suppn
overflow is
Overfl
LED indie
leading dig
attempts:
:
than seven
1-MHz test point
-5.2 VR3«5 C201
DtSPLA'
Variable c
with MEP
TERVAL
length of
will be;di
count is
dte next
taken. DU
varied fr
(MIN) tc
onds. t
(ctockwisE
tinuous d
by press!
button,
3-2

ADJUSTMENT OF INTERNAL CONTROLS
NOTE Time-Base Frequency Check and Adjustment. Connect
the DC 501 1-MHz time base reference and the secondary
iqTE instrument is operated on the plug-in extender, standard to the oscilloscope as shown. Adjust the oscillo-
the -i-5-volt supply may not regulate. scope to display several complete cycles.
:instrument can be check at
•the 0°C to +50°C range,
at atemperature between
"F and -f-86°F).
)erated either fully installed in a
)dule or connected to aplug-in
rtNo. 067-0645-01).
and Adjustment. Connect the
15-volt test point and ground.
Iof -1-15 volts. Then check the
D-volt supplies to be within 5%.
To determine oscillator error, observe the rate of
horizontal drift of the displayed waveform. Waveform
moving to the right indicates that the time-base frequency
is <1 MHz; to the left, >1MHz. The period in seconds for
the waveform to move the width of one cycle is equal to
the frequency difference in parts in 10®. For example, if
the waveform drifts to the right at arate of one cycle's
width every 10 seconds, the time-base frequency is 0.1 part
in 10® low. Maximum allowable frequency difference is 1
part in 10® (5 parts in 10^ for the optional 5MHz crystal).
Adjust C201 for no drift.
1-MHz test Roint
C201
DC 501
3-3

DC 51
NOTE.
3-4
i
U181
COMPONENTS SHOWN WITH DASHED LINES ARE LOCATED ON BACK SIDE OF BOARD,

DC 501
ELECTRICAL PARTS LIST
Replacement parts should be ordered from the Tektronix Field Office or Representative in your area.
Changes to Tektronix products give you the benefit of improved circuits and components. Please include
the instrument type number and serial number with each order for parts or service.
ABBREVIATIONS AND REFERENCE DESIGNATORS
AAssembly, separable or FL Filter PTM paper or plastic, tubular
repairable HHeat dissipating device molded
AT Attenuator, fixed or variable (heat sink, etc.) RResistor, fixed or variable
BMotor HR Heater RT Thermistor
BT Battery JConnector, stationary portion SSwitch
CCapacitor, fixed or variable KRelay TTransformer
Cer Ceramic LInductor, fixed or variable TP Test point
CR Diode, signal or rectifier LR Inductor/resistor combination UAssembly, inseparable or
CRT cathode-ray tube MMeter non-repairable
DL Delay line QTransistor or silicon- VElectron tube
DS Indicating device (lamp) controlled rectifier Var Variable
Elect. Electrolytic PConnector, movable portion VR Voltage regulator (zener diode.
EMC electrolytic, metal cased PMC Paper, metal cased etc.)
EMT electrolytic, metal tubular PT paper, tubular WW wire-wound
FFuse YCrystal
COUNTER TIME BASE AND CONTROL <!>
Ckt Grid Tektronix Serial/Model No.
No. Loc Port No. Eff Disc Description
ASSEMBLY
A1
A2
A3
CAPACITORS
670-2102-00
670-2103-00
670-2249-00
MAIN Circuit Board Assembly (part of)
DISPLAY Circuit Board Assembly (part of)
AUTO-GATE Circuit Board Assembly (Option 2)
C102 M5 281-0510-00 22 pF, Cer, 500 V, 20%
C103 M4 281-0605-00 200 pF, Cer, 500 V,
C106 L4 281-0509-00 15 pF, Cer, 500 V, 10%
C107 L5 281-0540-00 51 pF, Cer, 500 V, 5%
Clio L5 283-0068-00 0.01 pF, Cer, 500 V, +100%-0%
C112 L5 281-0571-00 82 pF, Cer, 500 V, 20%
C113 L6 283-0003-00 0.01 pF, Cer, 150 V, +80%-20%
C122 K5 283-0000-00 0.001 pF, Cer, 500 V, +100%-0%
C127 K5 283-0000-00 0.001 pF, Cer, 500 V, +100%-0%
C139 M5 283-0003-00 0.01 pF, Cer, 150 V, +80%-20%
C140 M5 283-0177-00 1pF, Cer, 25 V, +80%-20%
C141 M5 283-0000-00 0.001 pF, Cer, 500 V, +100%-0%
C152 J6 281-0589-00 170 pF, Cer, 500 V, 5%
C200 G5 281-0504-00 10 pF, Cer, 500 V, 10%
C201 G5 281-0166-00 1.9-15.7 pF, Var, Air
C202 G5 281-0739-00 18 pF, Cer, 500 V
C235 M4 290-0536-00 10 pF, Elect., 25 V, 20%
DIODES
CR115 K5 152-0141-02 Silicon, replaceable by 1N4152
CR122 K5 152-0141-02 Silicon, replaceable by 1N4152
CR124 J5 152-0141-02 Silicon, replaceable by 1N4152
CR125 J5 152-0141-02 Silicon, replaceable by 1N4152
CR127 J5 152-0141-02 Silicon, replaceable by 1N4152
CR128 J5 152-0141-02 Silicon, replaceable by 1N4152
CR165 H6 152-0141-02 Silicon, replaceable by 1N4152
3-5