Theory of Operation—DC 501
negative-going portion of the signal to ground. The signal is
then passed through emitter follower Q170 to U160B,
where it receives afinal phase inversion (to correspond with
the input signal) and becomes the decade input.
Time Base and Control Circuit
General. The time base and control circuit generates the
following control signals:
1.
GATE. The GATE output determines when the
counter is allowed to count. When this output level is HI,
the gate is "open" and the counter counts the input signal.
While the gate is open, the front-panel GATE indicator is
lit. The time during which the gate is open is determined by
the MEASUREMENT INTERVAL switch setting.
2.
LATCH. This output determines when the meas-
urement made by the decade counter units is transferred to
the storage register latches, permitting the readout display
to be updated. In the normal gate mode (one of four
selectable gate intervals), or in the optional AUTO gate
mode, the LATCH goes HI for 1psec immediately upon
closure of the GATE. In the manual gate mode, the LATCH
is held HI to allowcontinuous updating. Also, the LATCH
is activated by the RESET signal.
3.
CLEAR and CLEAR. These outputs determine
when the counter is to bereset tozero. Just before the
GATE opens, CLEAR and CLEAR are activated for ashort
duration (less than 2psec), resetting the DCU's to zero
before anew count is taken. Also, CLEAR and CLEAR are
activated by the RESET signal.
4.
RESET. This output is used to reset all of the
counting and dividing circuits in the DC 501, and to
enable all of the LED-readout character segments for a
segment check. The active level is LO, produced by aswitch
closure to ground (front-panel RESET switch, or between
the detent positions of the MEASUREMENT INTERVAL
switch).
1MHz Clock. Aprecise one-megahertz clock provides
the reference for operation of the gate-generating circuits.
The output of crystal oscillator Y200 is adjustable by C201
to exactly one megahertz. The four parts of U200 form a
shaper-buffer stage to produce square-wave clock pulses and
to isolate the oscillator from the 1-MHz output line.
NOTE
An optional 1MHz dock is available, using avery
stable 5MHz crystal oscillator and adivide-by-five
counter. This combination is shown on the schematic
as Y201 and U201.
Time Base Decade Dividers (DDU's). The DDU's consist
of seven cascaded divide-by-ten counters, U209 through
U215. They produce four gate times, 0.01 sec, 0.1 sec,1 sec
and 10 sec, which are made available via the MEASURE-
MENT INTERVAL switch to the gate generator to establish
the precise time interval the GATE is open. The 1MHz
clock signal is applied to pin 14 of U209, whose output is
connected to the input of the subsequent decade. Each
decade is clocked with anegative-going transition. The
DDU's are reset by aCLEAR pulse, which places a0count
in U209 and a9count in each subsequent decade.
Gate Generator. The gate generator produces the GATE
control signal and initiates the CLEAR, CLEAR, and
LATCH pulses. The generating portion consists of U220A,
U222A, U220B, and U222B. The display time control
portion consists of Q230, Q238, and Q240. The circuit will
be described first in the normal gate mode (MEASURE-
MENT INTERVAL switch in one of the four gate time
positions).
Assume that the T^j conditions are as given in Fig. 2-2.
The Qoutputs of U220A, U222A, U220B, and U222B are
all LO. Q230 is off and the emitter of Q238 rises as C235
charges. At T^ ,Q238 reaches its firing potential and
discharges the capacitor. This results in ashort-duration LO
pulse on the direct s^ input (pin 2) of U220A, forcing its Q
output HI and its Qoutput LO. With two HI inputs on
NAND gate U230A, its output goes LO and the output of
NOR gate U230C goes HI, producing the CLEAR and
CLEAR control signals. The next HI-to-LO transition from
the 1-MHz clockJT^) toggles U222A, causing its Qoutput
to go HI and its Qto go LO. With aLO applied to one of its
inputs, U230A reverts to its original condition, terminating
the CLEAR and CLEAR pulses. The DDU's then start
counting from their 0999999 reset condition.
At the end of a10-microsecond delay (time for the
DDU's to count the first digit, plus apropagation delay), a
negative transition from the DDU's via the MEASURE-
MENT INTERVAL switch toggles U220B. This corresponds
to Tg in Fig. 2-2. U220B's Qoutput goes HI and its Q
output goes LO. The next negative transition from the
1-MHz clock (T^) toggles U222B, causing its Qoutput to
go Hi (GATE open) and its Qoutput to go LO (supplying
current to the front-panel GATE indicator LED, CR225).
The GATE signal is also applied to the base of 0230,
saturating the transistor and preventing C235 from'
charging.
The GATE remains open (HI) for the time duration
selected by the MEASUREMENT INTERVAL switch. At
the end of this time, which corresponds to Tg in Fig. 2-2,
another negative transition from the DDU's toggles U220B.
U220B's Qoutput goes LO and its Qoutput goes HI. The
next negative transition from the 1-MHz clock (T^) toggles
