Tektronix 7D01 User manual

Tektrone<
COMMITTED TO EXCELLENCE
PLEASE CHECK FOR CHANGE INFORMATION
AT THE REAR OF THIS MANUAL.
7D01
LOGIC ANALYZER
(Serial No. BO20000 and up)
WITH OPTIONS
INSTRUCTION MANUAL
Tektronix, Inc.
P.O. Box 500
Beaverton, Oregon 97077 Serial Number SE
070-2206-02 First Printing OCT 1976
Product Group 57 Revised OCT 1982

Copyright © 1976, 1977, 1979 Tektronix, Inc. All rights
reserved. Contents of this publication may not be
reproduced in any form without the written permission of
Tektronix, Inc.
Products of Tektronix, Inc. and its subsidiaries are
covered by U.S. and foreign patents and/or pending
patents.
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TEKTRONIX, TEK, SCOPE-MOBILE, and W'% are
registered trademarks of Tektronix, Inc. TELEQUIP-
MENT is a registered trademark of Tektronix U.K.
Limited.
Printed in U.S.A. Specification and price change
privileges are reserved.

7D01 Instruction (SN BO20000 & up)
TABLE OF CONTENTS
PAGE
LIST'OF ILLUSTRATIONS, sscice ccs awmmats ts amma s ii
LISTIOP TABLES oew cst wo mG wea EF RRM ETT wai A ii
SAFETY SUMMARY .. 0.0... eee eee ee ee es iii
SECTION 1 GENERAL INFORMATION
INTRODUCTION. .. 0... cee cee ee eee we 1-1
GLOSSARY sc ec ce mee ee me ee 1-1
INSTALLATION... . ww ese mee eee EBS 1-1
PACKAGING FOR SHIPMENT. ..........50005 1-2
SPECIFICATION.«.:0:0 ses smmee eee MMO a ETS RBH 1-3
STANDARD ACCESSORIES... .... 00. eee eee 1-9
SECTION 2 OPERATING INSTRUCTIONS
FRONT PANEL CONTROLS,
CONNECTORS AND INDICATORS............ 2-1
DETAILED OPERATING INFORMATION.......... 2-1
AUXILIARY FUNCTIONS .............200- 2-1
INTERNAL STRAP SELECTIONS. ............ 2-4
SIGNAL CONNECTIONS ..........02000005 2-6
DISPLAYING DATA... 2... 2.2 eee ee ee eee 2-7
TRIGGERING... 2... 2. ee ee ee eee 2-7
CLOCK QUALIFIER OPERATION ............ 2-8
ASYNCHRONOUS AND SYNCHRONOUS
DATA SAMPLING)... www ees mimi bea we 2-9
OPERATIONAL ANALYSIS ............00484 2-10
APPLICATIONS «0:66 6 se mimm ce eb WHS EE SB 12-13
INTRODUCTION... 63 sees isswisme cis wad 2-13
FAULT IDENTIFICATION ..............2.24 2-13
DELAY BY WORDS .......... 0.0004 eee 2-13
DELAY BY EVENTS... 1... ee eee ee ee es 2-14
STATE TABLE AND MAPPING DISPLAYS ..... . 2-14
MICROPROCESSOR ANALYSIS............5-. 2-16
STORAGE BUFFER ANALYSIS.............-. 2-17
FUNCTIONAL CHECK . wwcccw cs nmeee esas 2-17
THE REMAINING PORTION OF THIS TABLE OF CON-
TENTS LISTS THE SERVICING INSTRUCTIONS. THESE
SERVICING INSTRUCTIONS ARE FOR USE BY QUALI-
FIED PERSONNEL ONLY. TO AVOID ELECTRICAL
SHOCK, DO NOT PERFORM ANY SERVICING OTHER
THAN THAT CALLED OUT IN THE OPERATING IN-
STRUCTIONS UNLESS QUALIFIED TO DO SO.
REV C JUN 1980
PAGE
SECTION 3 THEORY OF OPERATION
BLOCK DIAGRAM DESCRIPTION. ...........000.% 3-1
DETAILED CIRCUIT DESCRIPTION. ............. 3-3
FRONT PANEL WIRING .. seme css samme eee 3-3
WORD RECOGNIZER. «sss amew cis BRB we 3-3
MEMORY . 6 c3 5 WR EER RHR DAT TD WHAM et 3-4
TRIGGER. ¢ bs pK MOER TLE RRA Ee emma es 3-7
TIME: BASE s 44 5 SHH ET 6 HE Hdisi ne ew mmarew as 3-9
VERTICAL OUTPUT ........ eee ee eee 3-9
HORIZONTAL OUTPUT... .... eee eee 3-10
CURSOR, ok. oe ee cna meme hae WES 3-10
POWER SUPPLIES. «iw ey ewe me eg oe Rw 3-12
SECTION 4 MAINTENANCE
PREVENTIVE MAINTENANCE. ............000, 4-1
CLEANING . 0... ce ee ee 4-1
VISUAL INSPECTION. ... 0... 0000s 4-1
LUBRICATION. ... cw ee swe awe sy BHR M eS 4-1
SEMICONDUCTOR CHECKS, ............00058 4-2
TROUBLESHOOTING: «swiss css HTS TR wee 4-3
TROUBLESHOOTING EQUIPMENT ............ 4-3
TROUBLESHOOTING TECHNIQUES ........... 4-3
CORRECTIVE MAINTENANCE. ...........2000. 4-7
OBTAINING REPLACEMENT PARTS ........... 47
SOLDERING TECHNIQUES. ............000, 4-7
COMPONENT REMOVAL AND REPLACEMENT..... 4-8
ADJUSTMENT AFTER REPAIR. ............4.4 4-14
SECTION 5 PERFORMANCE CHECK AND ADJUSTMENT
PRELIMINARY INFORMATION ............4. 5-1
TEST EQUIPMENT REQUIRED..............4. 5-1
PRELIMINARY PROCEDURE...............4. 5-3
PERFORMANCE CHECK AND ADJUSTMENT
PROCEDURE... ....... eee eee 5-5
SECTION 6 REPLACEABLE ELECTRICAL PARTS
SECTION 7 INSTRUMENT OPTIONS
SECTION 8 DIAGRAMS AND CIRCUIT BOARD
ILLUSTRATIONS
SECTION 9 REPLACEABLE MECHANICAL PARTS
CHANGE INFORMATION

7D01 Instruction (SN BO20000 & up)
FIGURE
Frontis-
NO.
piece
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-2
3-3
LIST OF ILLUSTRATIONS
PAGE
7DO1 Logic Analyzer. . 2... ee iv
7D01 Dimensional Drawing... ........0005% 1-8
Front-panel controls, connectors, and
indicatOlsS: ssa wee we eee ee ee 2-2
Internal Display Clock Source and
Full Display/First Trigger Selectors... ......0.% 2-4
Internal Signal Selector... ... 2... 0. eee ueee 2-5
Pin assignments for Data Out
connector J120. 0.0... ee ee 2-6
Suggested methods for terminating
data outputs from Data Out connector
S120 2 2-7
Suggested method for assembling a
remote Manual Reset button ............4.% 2-7
Typical channel 0 to 15 pretrigger
data display’: sass ss & wim ees RRR ees 2-8
Equipment setup and displays for
finding a data fault and examining it
onananalogdisplay ..........0 05 ee eee 2-14
Equipment setup and data display
window that has been positioned after
a preselected word has occurred 25 times...... 2-15
Equipment setup and display window
that has been positioned after 10,500
clock pulses have occurred. .........-.206. 2-15
Typical setup for troubleshooting a
microprocessor system... 2... 0.002 ee eee 2-16
Typical setup and display for trouble-
shooting a storage buffer... .......00000% 2-17
7001 Block'Diagram: «ss wae ces Www EE 3-2
Equivalent circuit for one channel of
P6451 Data Acquisition Probe .........0055 3-3
Truth Table for Store/Display Clock
Gate 2. ee 3-5
PAGE
Electrical Characteristics. . . wae ees eee eee 1-3
Environmental Characteristics... ........000.4 1-8
Physical Characteristics. «si saws 6s aia male as 1-8
Format Output Levels: i sic swe eet ww Rw ee 2-1
Minimum Clock Pulses Required to Display
Data (After the MANUAL, RESET Button is
Pressed) 2... ee 2-9
FIGURE
NO.
3-4
3-5
3-6
3-7
3-8
41
4-2
4-3
44
4-5
4-6
4-7
48
49
4-10
4-11
PAGE
Latch Clock timing for 4-channel
Operations «aa. cc aR TS DRM ES HR 3-5
Latch Clock timing for 8-channel
Operation. . 2. 3-6
Memory Selector timing for 4-channel
operation (display time only).............. 3-6
Memory Selector timing for 8-channel
operation
(display time only). ..........005 3-6
Binary output of U628 versus channel
displayed. . 2... ee ee ee es 3-9
Lubrication procedure for a typical cam
SWItCH) cme ge Rew EE ER MSH Ea eR 4-2
Circuit board locations... .. 2.0.00. ee eee 4-5
Power supply +5 volt test point location. ....... 4-6
Location of securing screws on the
Memory circuit board ...........04 00 eee 4-8
Multi-pin connector and P number
orientation for the Memory circuit board ....... 4-9
Location of securing screws on the
Interface circuit board... .... 2... 0.2 000 e 4-10
Locations of securing screws on the
Output circuit board... 2... ee eee 4-10
Locations of securing screws and shield
on the Power Supply board .............. 4-11
Locations of securing screws on the
Cursor circuit board a: 5.:0% & & sw sw we ee oe w 9 4-11
Locations of hex nuts and screws on front
sub panel which secure the Word Recog-
nizer circuit board! « saw eis es emw ee 8 4-12
Exploded view of circuit-board pin
ana Terrules ¢ cis seam ees se wiwawe ds wae 4-14
The illustrations in Section 8 are located near their associated
Diagrams on the foldout pages.
TABLE
PAGE
Operational Analysis... 1.0.0... 0 ee eee 2-10
Power Supply Tolerances ........00 0000 e ue 4-6
Test Equipments «iis waeee eae BRE ETT 5-1
Option Information Locator. ..........0.0.005 7-1
REV. A, MAR 1977
—~
_

7D01 Instruction (SN BO20000 & up)
SAFETY SUMMARY
The following safety information is provided to ensure safe operation of this instrument. WARNING information is intended
to protect the operator; CAUTION information is intended to protect the instrument. The following are general safety pre-
cautions that must be observed during all phases of operation and maintenance.
To reduce electrical-shock hazard, the mainframe (oscilloscope) chassis must be properly grounded. Refer to the mainframe
manual for grounding information.
Ground the Instrument
Do Not Operate in Explosive Atmosphere
Do not operate this instrument in an area where flammable gases or fumes are present. Such operation could cause an
explosion.
Avoid Live Circuits
Electrical-shock hazards are present in this instrument. The protective instrument covers must not be removed by operating
personnel. Component replacement and internal adjustments must be referred to qualified service personnel,
Do Not Service or Adjust Alone
Do not service or make internal adjustments to this instrument unless another person, capable of giving first aid and resusci-
tation, is present.

7D01 (SN B020000 & up)
7D01 FEATURES
The 7D01 Logic Analyzer will store and display up to 16 channels of digital data when installed in a 7000-series mainframe.
The cursor function provides an intensified zone on the data display, and a corresponding numerical readout display shows
the logic state (1 or 0) for each displayed channel of data. The position of the cursor, relative to the trigger, is also displayed
on the crt readout. Cursor readout is displayed in either 3-bit or 4-bit bytes.
Digital data can be stored in 3 formats: 4 channels at 1016 bits/channel, 8 channels at 508 bits/channel, or 16 channels at
254 bits/channel. The sample rate is selectable from 10 nanoseconds to 5 milliseconds/sample (in a 5-2-1 sequence) when
using the internal time base, or can be used with an external clock signal (up to 50 megahertz).
The 7D01 can be triggered from 4 sources: channel O data, an external signal, a built-in 16-channel word recognizer, or man-
ually. The triggered data can be produced following the trigger (POST TRIG), centered around the trigger (CENTER), or pre-
ceeding the trigger (PRE TRIG). The input threshold can be varied from minus 12 volts to plus 12 volts, or set to plus 1.4
volts for TTL logic levels.
The Word Recognizer produces an output when the logic states of the 16 input data channels match the states of the corres-
ponding Word Recognizer switches. Two qualifier inputs are also provided to enable the Word Recognizer output. The Word
Recognizer operates in either the synchronous or asynchronous mode. A variable filter (to at least 300 nanoseconds)-allows
rejection of brief false-trigger signals.
iv REV B, JAN 1979
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Section
1—-7D01
(SN
B020000
&
up)
GENERAL INFORMATION
INTRODUCTION
7D01 Operator’s Manual
The Operator’s manual contains the information necessary
to operate the 7D01 Logic Analyzer. The manual is divided
into three sections, each covering a specific topic of the
instrument.
Section 1 provides a basic description of the
7D01, a glossary of logic terms, installation instructions,
and specifications. Section 2 contains operating information
for the instrument. Information concerning available op-
tions for the 7D01 is on a tabbed page in Section 3.
7D01 Instruction Manual
The Instruction manual provides operating and servicing
information for the 7D01 Logic Analyzer. The manual is
divided into ten sections. Operating information is covered
in the first two sections; servicing information is contained
in the remaining eight sections of the manual. Schematics
are located at the rear of the manual and can be unfolded
and used for reference while reading other parts of the
manual. The reference designators and symbols used on the
schematics are defined on the first page of the Diagrams
section. Abbreviations used in the manuals, except in the
parts list and schematics, comply with the American
National Standards Institute Y1.1-1972 publication. The
parts lists are computer printouts and use computer-
supplied abbreviations.
GLOSSARY
The terms listed in this glossary are used throughout this
manual.
Asynchronous—Multiple digital information transferred at
non-common clock rates.
Bit—The smallest increment of digital information.
CPU—Central Processing Unit.
ECL—Emitter-Coupled Logic.
Jitter—A form of distortion in asynchronous systems that
is due to timing variations of the received data.
Multiplexing—The combining of multiple inputs into a
single output.
Parallel-to-Serial Conversion—The technique of storing a
digital pattern from a parallel bus, then transferring that
pattern out to a serial bus.
REV OCT 1982
Parity Bits—Bits added to the data stream which enable the
receiver to verify whether the data is correctly or incor-
rectly received.
PROM—Programmable Read Only Memory.
RAM—Random Access Memory.
Serial Data—Data transferred on a single line. Serial data
logic is derived in a sequential mode.
Store Clock—The clock used to store information into the
7D01 memory.
Synchronous—Digital information transferred with the
same clock reference.
Threshold Voltage—The comparator input voltage on the
inverting input, which is used as a reference. Thus, if the
signal on the non-inverting input is above the threshold
voltage, the output is HI; if the signal is below the threshold
voltage, the output is LO.
TTL—Transistor-Transistor Logic.
“Wired-OR"—ECL gate outputs that are connected together
to yield the equivalent output of an OR gate.
INSTALLATION
The 7D01 is calibrated and ready to use when received. It is
designed to occupy a vertical and horizontal plug-in com-
partment in all 7000-series mainframes with readout except
the 7104, which may suffer crt damage that will not be cov-
ered by the instrument warranty, and the Digital Processing
Oscilloscope (DPO), which will not digitize the 7D01 out-
puts. There are some operating modes, however, that will
not provide proper operation. These modes are discussed
under Displaying Data in Section 2. Install the 7D01 in the
two compartments on the right side of a three-compartment
mainframe, or in the right vertical and A horizontal compart-
ments in the center of a four-compartment mainframe.
NOTE
Some rackmounted mainframes have vertically
mounted rods in front of the plug-in compart-
ments that interfere with the installation of the
7D01, Detach these rods by removing the mount-
ing screws at each end before installing the 7D01.
1-1

General Information—7D01 (SN B020000 & up)
To install the 7D01 in the mainframe, align the 7D01 tracks
with the rails of a vertical and horizontal plug-in compart-
ment. Gently slide the 7D01 into the mainframe and push
firmly to lock the 7D01 front panel flush with the
mainframe.
To remove the 7D01, grasp the release latch in the lower
left corner and pull the 7D01 out of the mainframe.
PACKAGING FOR SHIPMENT
If this instrument is to be shipped for long distances by
commercial transportation, it is recommended that the
instrument be packaged in the original manner for maxi-
mum protection. The carton and packing material in which
your instrument was shipped should be saved and used for
this purpose.
If the original packaging is unfit for use or not available,
package the instrument as follows:
1. Obtain a carton of corrugated cardboard with at least a
200 pound test strength and inside dimensions of no less
than six inches more than the instrument dimensions; this
will allow for cushioning.
1-2
2. Surround the instrument with polyethylene sheeting to
protect the finish of the instrument.
3. Cushion the instrument on all sides by tightly packing
dunnage or urethane foam between the carton and the
instrument, allowing three inches on all sides.
4. Seal the carton with shipping tape or an industrial
stapler.
Also, if this instrument is to be shipped to a Tektronix
Service Center for service or repair, attach a tag to the
instrument showing the following: Owner of the instru-
ment (with address), the name of an individual at your firm
that can be contacted, complete instrument type and serial
number, and a description of the service required. Mark the
address
of the Tektronix Service Center, and your return
address, on the carton in one or more prominent locations.
REV. A, MAR 1977

General Information—7D01 (SN B020000 & up)
SPECIFICATION
The electrical specifications listed in Table 1-1 apply when the following conditions are met: (1) The instrument must have
been adjusted at an ambient temperature between +20° and +30° C (+68° and +86° F), (2) the instrument must be operating
in an ambient temperature between 0° and +40° C (+32° and +104° F), and (3) the instrument must have been operating for
at least 20 minutes.
TABLE 1-1
Electrical Characteristics
Characteristic |
CLOCK AND DATA INPUTS
Performance Requirement
Probe Inputs (Clock, Qualifier, and Data)
Input R and C 1 MQ within 5%, paralleled by approx. 5 pF.
Threshold Voltage
VAR (at Monitor Jack) —12 V or less, to at least +12 V.
TTL +1.4 V within 0.2 V.
Minimum Logic Swing 500 mV plus 2% of threshold voltage p-p or less, centered
on threshold voltage.
Maximum Logic Swing —60 V or less, to at least threshold voltage plus 10 V.
Maximum Non-Destructive Input Voltage —60 V or less, to at least +60 V.
External Clock
Minimum Clock Period
CH 0-3 20 ns or less.
CH 0-7 20 ns or less.
CH 0-15 40 ns or less.
Minimum Clock Pulse Width
HI Level LO Level
CH 0-3 10 ns or less 10 ns or less
CH 0-7 10 ns or less 10 ns or less
CH 0-15 20 ns or less 20 ns or less
Minimum Data Setup Time
CH 0-3 20 ns or less.
CH 0-7 20 ns or less.
CH 0-15 23 ns or less.
Minimum Data Hold Time Ons or less.
Clock Qualifier
Setup Time Hold Time
P6451 Probe 20 ns Ons
External Input (measured at external
input connector) 11 ns 7 ns
REV OCT 1982

General Information—7D01 (SN B020000 & up)
TABLE 1-1 (CONT.)
Electrical Characteristics
Characteristic
Performance Requirement
CLOCK AND DATA INPUTS (CONT.)
Internal Clock
Minimum Sample Interval
CH 0-3 10 ns or less.
CH 0-7 20 ns or less.
CH 0-15 50 ns or less.
Minimum Data Pulse Width (to Ensure Recording)
1 sample interval plus 5 ns or less.
INTERNAL CLOCK
Crystal Oscillator Frequency
100 MHz within 0.005 MHz.
Sample Intervals
10 ns to 5 ms/sample in 1-2-5 sequence.
TRIGGER
Trigger Sources
CHO
Triggers on rising edge of CH O data.
External Trig/Qualifier Input
Threshold
+1.4 V within 0.2 V (TTL Level).
Minimum Pulse Width
15 ns or less.
Max Safe Input Voltage —5 V or less, to at least +10 V.
Word Recognizer
16 Data inputs, Probe Qualifier, and External Qualifier.
Output is true when input conditions match switch settings
(HI, X, LO).
Minimum Input Pulse Width (Asynchronous Mode)
Any Single Channel 10 ns or less.
Channels 0-3 15 ns or less.
Any Other Combination 20 ns or less.
Filter
Continuously variable to at least 300 ns.
Synchronous Mode Coincidence of matching combination and an external clock
edge must occur for recognition.
Minimum Setup Time 12.5 ns or less.
Minimum Hold Time 8.5 ns or less.
1-4 REV OCT 1982