Tektronix 7D01 User manual

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Tektronix, Inc.
P.O. Box 500
Beaverton, Oregon 97077
070-2205-02
Tektronix.
COMMITTED TO EXCELLENCE
INSTRUCTION MANUAL |
Serial Number
Bivas Duindin.. AAS 3A

WARRANTY
Tektronix warrants that this product is free from defects in materials
and workmanship. The warranty period is one (1) year from the date
of shipment. Tektronix will, at its option, repair or replace the
product if Tektronix determines it is defective within the warranty
period and if it is returned, freight prepaid, to a service center
designated by Tektronix.
Tektronix is not obligated to furnish service under this warranty
a. to repair damage resulting from attempts by personnel other
than Tektronix representatives to install, repair, or service the
product;
b. to repair damage resulting from improper use or from
connecting the product to incompatible equipment;
c. if personnel other than Tektronix representatives modify the
hardware or software.
There is no implied warranty of fitness for a particular purpose.
Tektronix is not liable for consequential damages.
Copyright © 1976, 1977, 1980 Tektronix, Inc. All rights
reserved. Contents of this publication may not be
reproduced in any form without the written permission of
Tektronix, Inc.
Products of Tektronix, Inc. and its subsidiaries are covered
by U.S. and foreign patents and/or pending patents.
TEKTRONIX, TEK, SCOPE-MOBILE, and Gay are regis-
tered trademarks of Tektronix, Inc.
Printed in U.S.A. Specification and price change privileges
are reserved.

TABLE OF CONTENTS
7D01 Operators (SN BO20000 & up)
PAGE
LIST OF ILLUSTRATIONS ...........0 0.00000. ii
LIST,OF TABLES: & scae ec seem v5 ete fe ii
SAFETY SUMMARY, wan: es came eos waders a iii
SECTION 1 GENERAL INFORMATION
INTRODUCTION a6 csc i a wie ee ees 1-1
GLOSSARY... seeks cs dsm ees me ee 1-1
INSTALLATION wn 6+ see ce es ee w es 1-1
PACKAGING FOR SHIPMENT............ 1-2
SPECIFICATION 4 sauce is wae cs stn 1-3
STANDARD ACCESSORIES .............04. 1-9
SECTION 2 OPERATING INSTRUCTIONS
FRONT PANEL CONTROLS,
CONNECTORS AND INDICATORS........ 2-1
DETAILED OPERATING INFORMATION..... 2-1
AUXILIARY FUNCTIONS.............. 2-1
INTERNAL STRAP SELECTIONS ........ 2-4
SIGNAL CONNECTIONS............... 2-6
DISPLAYING DATA...............000. 2-7
TRIGGERING® 2752s sks Peat d Shaw eee 2-7
CLOCK QUALIFIER OPERATION ........ 2-8
ASYNCHRONOUS AND SYNCHRONOUS
DATA SAMPLING ..............00004 2-9
OPERATIONAL ANALYSIS............. 2-10
APPLICATIONS .... 0... 0.0.0 e eee eee 2-13
INTRODUCTION sae ccs naine wees eee ee 2-13
FAULT IDENTIFICATION ............. 2-13
DELAY BY WORDS..............0205- 2-13
DELAY BY EVENTS «2 s+ entaecis wns 2-14
STATE TABLE AND MAPPING DISPLAYS . 2-14
MICROPROCESSOR ANALYSIS.......... 2-16
STORAGE BUFFER ANALYSIS.......... 2-17
FUNCTIONAL CHECK .............0.. 2-17
SECTION 3 INSTRUMENT OPTIONS
REV B, APR 1979

7D01 Operators (SN BO20000 & up)
LIST OF ILLUSTRATIONS
FIGURE FIGURE
NO. PAGE NO. PAGE
Frontis- 2-7 Typical channel 0 to 15 pretrigger
piece 7DO1 Logic Analyzer... ... . ee ee iv Gata display cv. ces bss ww 8 a Pee 2-8
1-1 7D01 Dimensional Drawing. ..........205. 1-8 2-8 Equipment setup and displays for
2-1 Front-panel controls, connectors, and finding a data fault and examining it
WICSTON® ck wee ec cb a dw eae www es 2-2 onan analog display a6 6 is ww ose ee 2-14
2-2 Internal Display Clock Source and 2-9 Equipment setup and data display
Full Display/First Trigger Selectors... ........ 2-4 window that has been positioned after
2-3 Internal Signal Selector... .......-. 20. e eee 2-5 a preselected word has occurred 25 times ...... 2-15
24 Pin assignments for Data Out 2-10 Equipment setup and display window
connector J120 wx ess eee Hea we ¥ eo 2-6 that has been positioned after 10,500
2-5 Suggested methods for terminating clock pulses have occurred... ........0004 2-15
data outputs from Data Out connector 2-11 Typical setup for troubleshooting a
SAO ees ini Mete eel tcd cl neiiatee ited occa irer eMart cmt teal 2-7 microprocessor system... .......-.0804 0s 2-16
2-6 Suggested method for assembling a 2-12 Typical setup and display for trouble-
remote Manual Reset button ...........0005 2-7 shooting a storage buffer... ........-..2084 2-17
LIST OF TABLES
TABL TABLE
NO. PAGE NO. PAGE
1-1 Electrical Characteristics. «6.0.36... 00 086204 % 1-3 2-2 Minimum Clock Pulses Required to Display
1-2 Environmental Characteristics... .........0404 1-8 Data (After the MANUAL RESET Button is
1-3 Physical Characteristics. . 2... 0... eee eee 1-8 Pressed) 2... . ee ee ee 2-9
2-1 Format Output Levels... ... 2.0... pee eee ee 2-1 2-3 Operational Analysis... . 20... 0.0.00 00 eae 2-10
3-1 Option Information Locator.............204. 3-1
ii REV B, APR 1979

7D01 Operators (SN BO20000 & up)
SAFETY SUMMARY
The following safety information is provided to ensure safe operation of this instrument. WARNING information is intended
to protect the operator; CAUTION information is intended to protect the instrument. The following are general safety pre-
cautions that must be observed during all phases of operation and maintenance.
To reduce electrical-shock hazard, the mainframe (oscilloscope) chassis must be properly grounded. Refer to the mainframe
manual for grounding information.
Ground the Instrument
Do Not Operate in Explosive Atmosphere
Do not operate this instrument in an area where flammable gases or fumes are present. Such operation could cause an
explosion.
Avoid Live Circuits
Electrical-shock hazards are present in this instrument. The protective instrument covers must not be removed by operating
personnel. Component replacement and internal adjustments must be referred to qualified service personnel.
Do Not Service or Adjust Alone
Do not service or make internal adjustments to this instrument unless another person, capable of giving first aid and resusci-
tation, is present.

7D01 (SN BO20000 & up)
7D01 FEATURES
The 7D01 Logic Analyzer will store and display up to 16 channels of digital data when installed in a 7000-series mainframe.
The cursor function provides an intensified zone on the data display, and a corresponding numerical readout display shows
the logic state (1 or 0) for each displayed channel of data. The position of the cursor, relative to the trigger, is also displayed
on the crt readout. Cursor readout is displayed in either 3-bit or 4-bit bytes.
Digital data can be stored in 3 formats: 4 channels at 1016 bits/channel, 8 channels at 508 bits/channel, or 16 channels at
254 bits/channel. The sample rate is selectable from 10 nanoseconds to 5 milliseconds/sample (in a 5-2-1 sequence) when
using the internal time base, or can be used with an external clock signal (up to 50 megahertz).
The 7D01 can be triggered from 4 sources: channel O data, an external signal, a built-in 16-channel word recognizer, or man-
ually. The triggered data can be produced following the trigger (POST TRIG), centered around the trigger (CENTER), or pre-
ceeding the trigger (PRE TRIG). The input threshold can be varied from minus 12 volts to plus 12 volts, or set to plus 1.4
volts for TTL logic levels.
The Word Recognizer produces an output when the logic states of the 16 input data channels match the states of the corres-
ponding Word Recognizer switches. Two qualifier inputs are also provided to enable the Word Recognizer output. The Word
Recognizer operates in either the synchronous or asynchronous mode. A variable filter (to at least 300 nanoseconds) allows
rejection of brief false-trigger signals.
iv REV A, APR 1979
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Section 1—7D01 (SN B020000 & up)
GENERAL INFORMATION
INTRODUCTION
7D01 Operator’s Manual
The Operator’s manual contains the information necessary
to operate the 7D01 Logic Analyzer. The manual is divided
into three sections, each covering a specific topic of the
instrument. Section 1 provides a basic description of the
7D01, a glossary of logic terms, installation instructions,
and specifications. Section 2 contains operating information
for the instrument. Information concerning available op-
tions for the 7D01 is on a tabbed page in Section 3.
7D01 Instruction Manual
The Instruction manual provides operating and servicing
information for the 7D01 Logic Analyzer. The manual is
divided into ten sections. Operating information is covered
in the first two sections; servicing information is contained
in the remaining eight sections of the manual. Schematics
are located at the rear of the manual and can be unfolded
and used for reference while reading other parts of the
manual. The reference designators and symbols used on the
schematics are defined on the first page of the Diagrams
section. Abbreviations used in the manuals, except in the
parts list and schematics, comply with the American
National Standards Institute Y1.1-1972 publication. The
parts lists are computer printouts and use computer-
supplied abbreviations.
GLOSSARY
The terms listed in this glossary are used throughout this
manual.
Asynchronous—Multiple digital information transferred at
non-common clock rates.
Bit—The smallest increment of digital information.
CPU—Central Processing Unit.
ECL—Emitter-Coupled Logic.
Jitter—A form of distortion in asynchronous systems that
is due to timing variations of the received data.
Multiplexing—The combining of multiple inputs into a
single output.
REV B, APR 1979
Parallel-to-Serial Conversion—The technique of storing a
digital pattern from a parallel bus, then transferring that
pattern out to a serial bus.
Parity Bits—Bits added to the data stream which enable the
receiver to verify whether the data is correctly or incor-
rectly
received.
PROM-—Programmable Read Only Memory.
RAM-—Random Access Memory.
Serial Data—Data transferred on a single line. Serial data
logic is derived in a sequential mode.
Store Clock—The clock used to store information into the
7D01 memory.
Synchronous—Digital information transferred with the
same clock reference.
Threshold Voltage—The comparator input voltage on the
inverting input, which is used as a reference. Thus, if the
signal on the non-inverting input is above the threshold
voltage, the output is HI; if the signal is below the threshold
voltage, the output is LO.
TTL—Transistor-Transistor Logic.
“Wired-OR”’—ECL gate outputs that are connected together
to yield the equivalent output of an OR gate.
INSTALLATION
The 7D01 is calibrated and ready to use when received. It is
designed to occupy a vertical and horizontal plug-in compart-
ment in all 7000-series mainframes with readout except the
Digital Processing Oscilloscope (DPO), which will not digi-
tize the 7D01 outputs. There are some operating modes,
however, that will not provide proper operation. These
modes are discussed under Displaying Data in section 2.
Install the 7D01 in the two compartments on the right
side of a three-compartment mainframe, or in the right
vertical and A horizontal compartments in the center of
a four-compartment mainframe.
NOTE
Some rackmounted mainframes have vertically
mounted rods in front of the plug-in compart-
ments that interfere with the installation of the
7D01. Detach these rods by removing the mount-
ing screws at each end before installing the 7D07.

General Information—7D01 (SN B020000 & up)
To install the 7D01 in the mainframe, align the 7D01 tracks
with the rails of a vertical and horizontal plug-in compart-
ment. Gently slide the 7D01 into the mainframe and push
firmly to lock the 7D01 front panel flush with the
mainframe.
To remove the 7D01, grasp the release latch in the lower
left corner and pull the 7D01 out of the mainframe.
PACKAGING FOR SHIPMENT
If this instrument is to be shipped for long distances by
commercial transportation, it is recommended that the
instrument be packaged in the original manner for maxi-
mum protection. The carton and packing material in which
your instrument was shipped should be saved and used for
this purpose.
If the original packaging is unfit for use or not available,
package the instrument as follows:
1. Obtain a carton of corrugated cardboard with at least a
200 pound test strength and inside dimensions of no less
than six inches more than the instrument dimensions; this
will allow for cushioning.
1-2
2. Surround the instrument with polyethylene sheeting to
protect the finish of the instrument.
3. Cushion the instrument on all sides by tightly packing
dunnage or urethane foam between the carton and the
instrument, allowing three inches on all sides.
4. Seal the carton with shipping tape or an industrial
stapler.
Also, if this instrument is to be shipped to a Tektronix
Service Center for service or repair, attach a tag to the
instrument showing the following: Owner of the instru-
ment (with address), the name of an individual at your firm
that can be contacted, complete instrument type and serial
number, and a description of the service required. Mark the
address of the Tektronix Service Center, and your return
address, on the carton in one or more prominent locations.
REV. A, MAR 1977

General Information—7D01 (SN BO20000 & up)
SPECIFICATION
The electrical specifications listed in Table 1-1 apply when the following conditions are met: (1) The instrument must have
been adjusted at an ambient temperature between +20° and +30° C (+68° and +86° F), (2) the instrument must be operating
in an ambient temperature between 0° and +40° C (+32° and +104° F), and (3) the instrument must have been operating for
at least 20 minutes.
TABLE 1-1
Electrical Characteristics
Characteristic
CLOCK AND DATA INPUTS
Performance Requirement
Probe Inputs (Clock, Qualifier, and Data)
Input R and C
1 MQ within 5%, paralleled by approx. 5 pF.
Threshold Voltage
VAR (at Monitor Jack)
—12 V or less, to at least +12 V.
TTL
+1.4 V within 0.2 V.
Minimum Logic Swing
on threshold voltage.
500 mV plus 2% of threshold voltage p-p or less, centered
Maximum Logic Swing
—60 V or less, to at least threshold voltage plus 10 V.
Maximum Non-Destructive Input Voltage
—60 V or less, to at least +60 V.
External Clock
Minimum Clock Period
CH 0-3 20 ns or less.
CH 0-7 20 ns or less.
CH 0-15 40 ns or less.
Minimum Clock Pulse Width
HI Level LO Level
CH 0-3 10 ns or less 10 ns or less
CH 0-7 10 ns or less 10 ns or less
CH 0-15 20 ns or less 20 ns or less
Minimum Data Setup Time
CH 0-3 20 ns or less.
CH 0-7 20 ns or less.
CH 0-15 23 ns or less.
Minimum Data Hold Time Ons or less.
REV. A, MAR 1977
1-3

General Information—7D01 (SN BO20000 & up)
TABLE 1-1 (CONT.)
Electrical Characteristics
Characteristic Performance Requirement
CLOCK AND DATA INPUTS (CONT.)
Internal Clock
Minimum Sample Interval
CH 0-3 10 ns or less.
CH 0-7 20 ns or less.
CH 0-15 50 ns or less.
Minimum Data Pulse Width (to Ensure Recording)
1 sample interval plus 5 ns.
INTERNAL CLOCK
Crystal Oscillator Frequency
100 MHz within 0.005 MHz.
Sample Intervals
10 ns to 5 ms/sample in 1-2-5 sequence.
TRIGGER
Trigger Sources
CH O
Triggers on rising edge of CH O data.
External Trig/Qualifier Input
Threshold
+1.4 V within 0.2 V (TTL Level).
Minimum Pulse Width
15 ns or less.
Max Safe Input Voltage
—5 V or less, to at least +10 V.
Word Recognizer 16
Data inputs, Probe Qualifier, and External Qualifier.
Output is true when input conditions match switch settings
(HI, X, LO).
Minimum Input Pulse Width (Asynchronous Mode)
Any Single Channel
10 ns or less.
Channels 0-3
15 ns or less.
Any Other Combination
20 ns or less.
Filter
Continuously variable to at least 300 ns.
Synchronous Mode
Coincidence of matching combination and an external clock
edge must occur for recognition.
Minimum Setup Time
12.5 ns or less.
Minimum Hold Time
8.5 ns or less.
1-4
REV. A, MAR 1977

General Information—7D01 (SN B020000 & up)
TABLE 1-1 (CONT.)
Electrical Characteristics
Characteristic
Performance Requirement
TRIGGER (CONT.)
Word Recognizer Output
Voltage
HI At least +1.9 V (0.95 V into 50-Q load).
LO +0.1 V or less (50 mV into 50-Q load).
Output Impedance (Rising Edge)
50 &2, within 10%.
Full Display/First Trigger Mode Selection
Selectable by internal jumper, P617.
Full Display Mode
Produces a full horizontal display.
First Trigger Mode
Accepts the first trigger after reset.
DISPLAY
Vertical
Magnify X1 to at least X5.
Position Positions magnified display within graticule area.
Horizontal
Magnify X1 to at least X9.
Position Positions magnified display within graticule area.
Display Length in X1 Mag (With Full Data)
7.5 div to 10 div.
Raster Shift With Format Change
1 div or less at X1 mag.
Display Time Range
Approximately 1 sec to 10 sec, followed by reset; or
infinite hold.
Manual Reset
Resets to store mode when button is pushed.
Display Format
Selectable by DATA CHANNELS switch:
Ch 0-3 x 1016 Bits/Ch
1 group of 4 traces.
Ch 0-7 x 508 Bits/Ch
2 groups of 4 traces each.
Ch 0-15 x 254 Bits/Ch
4 groups of 4 traces each.
Blanking Time
Ch 0-3 8 bits.
Ch 0-7 4 bits.
Ch 0-15 2 bits.
REV. A, MAR 1977
1-5

General Information—7D01 (SN B020000 & up)
TABLE 1-1 (CONT.)
Electrical Characteristics
Characteristic Performance Requirement
DISPLAY (CONT.)
Cursor
Cursor Position Control Positions intensified zone to any displayed bit, in incre-
ments of 1 bit or 16 bits.
Readout
Cursor Position Top right-hand readout shows cursor position (in sample
intervals) relative to trigger (e.g., TRIG + xxx).
Data Bottom readout shows the logic state of each displayed
channel at the cursor (Hi = 1; Lo = 0).
Byte Switch Breaks data readout into 3-bit or 4-bit bytes. In 16 channels
and 3-bit bytes, the left hand group remains 4 bits.
Trigger Intensified Zone Intensifies trigger point selected by data position switch.
Position (Relative to Displayed Trigger Event)
10 ns/Sample Typically 0 to 4 bits.
20 ns/Sample Typically 0 to 3 bits.
50 ns to 5 ms/Sample Within 1 bit.
DATA OUT
Data Out Connector J120*
Parallel Data Out Parallel data from Memory, non-inverted.
Channel Pin Channel Pin
0 13 8 9
1 25 9 21
2 12 10 8
3
24 11 20
4 11 12 7
5 23 13 19
6 10 14 6
7 22 15 18
Serial Data Out Pin 4—Serial data from memory, non-inverted.
Channel Sequence:
CH 0-3 2-3-0-1-2, etc.
CH 0-7 2-3-4-5-6-7-0-1-2, etc.
CH 0-15 2-3-12-13-14-15-8-9-10-11-4-5-6-7-0-1-2, etc.
*All logic levels are ECL levels unless otherwise specified.
1-6 REV B, APR 1979

General Information—7D01 (SN B020000 & up)
/ TABLE 1-1 (CONT.)
Electrical Characteristics
Characteristic Performance Requirement
DATA OUT (CONT.)
Data Out Connector J120* (Cont.)
Frame Output Pin 16—Falling edge indicates end of Ch 2; rising edge
indicates end of Ch 3. Frame occurs every 16th sweep
(independent of format).
Flag Output Pin 14—Falling edge indicates beginning of channel; rising
edge indicates end of channel.
Record Enable Pin 15 Hi input forces reset. Hi output occurs when
MANUAL RESET is pressed.
External Display Clock Input Pin 3, terminated with 100 2 to —2 V.
Frequency Range Less than 1 Hz to at least 2 MHz.
Ground Pin 17.
Signal Select Jumper P300 Pins 1,2, and 5 of J120 are connected to pins 7, 8, and 6,
respectively of the Signal Select Jumper. There are 5 signals
available to the Signal Select Jumper.
Format Output Pins 1 and 2 of Signal Select Jumper:
Pin 1 Pin 2
Ch
0-3
Hi
Hi
Ch 0-7 Hi Lo
Ch 0-15 Lo Lo
Display/Store Output Pin 3 of the Signal Select Jumper:
Store Hi
Display Lo
Trigger Intensify Output Pin 4 of Signal Select Jumper, LO = intensified trigger point
on display.
Master Reset Output Pin 5 of Signal Select Jumper, HI during reset.
POWER SUPPLY
Line Voltage Ranges Refer to 7000-series oscilloscope performance requirements.
Internal Power Supplies
—4.8 Volt
Accuracy (+20° to +30° C) Within —4.80 V to —4.925 V.
—2.0 Volt
Accuracy (+20° to +30° C) Within 0.2 V.
*All logic levels are ECL levels unless otherwise specified.
REV.
A,
MAR
1977
1-7

General Information—7D01 (SN BO20000 & up)
TABLE 1-2
Environmental Characteristics
Characteristic
Performance Requirement
Temperature
Operating 0° to +40° C.
Storage —55° to+75° C.
Altitude
Operating To 15,000 feet.
Storage To 50,000 feet.
Transportation
Procedure 1A, Category II.
Qualified under National Safe Transit Committee Test
TABLE 1-3
Physical Characteristics
Characteristic Description
Weight (Without Accessories)
Approximately 4.4 Ibs (2.0 kg).
Dimensions See Figure 1-1.
0 0 0 O = -
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(12.7) =
| eo000000000 s=
| e000000000 =
NY 0° ’ =
5.5 7 14.4 ral
[~~ (14.0) 7 (36.6)
NOTE
DIMENSIONS ARE GIVEN WITH TOP
FIGURE IN INCHES AND BOTTOM
FIGURE IN CENTIMETERS.
2206-2
Figure 1-1. 7D01 Dimensional Drawing.
1-8
REV. A, MAR 1977

General Information—7D01 (SN BO20000 & up)
STANDARD ACCESSORIES
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Ca Kv aeaw sce Haw ees eee ee P6451 Probe Package
For more information, refer to the tabbed Accessories page
in the back of this manual.
1-9

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Section 2—7D01 (SN B020000 & up)
OPERATING INSTRUCTIONS
This section includes a description of the 7D01 front-panel controls, connectors, and indicators. Also included is detailed
operating information, some basic application procedures and a functional check procedure. Refer to Section 1, General
Information, for a glossary of terms and installation instructions.
FRONT-PANEL CONTROLS,
CONNECTORS, AND INDICATORS
The location and function of the front-panel controls,
connectors, and indicators are illustrated in Figure 2-1.
Refer to Detailed Operating Information for a discussion of
the auxiliary functions available with the internal selectors,
and the input and output signals available through the Data
Out connector.
DETAILED OPERATING INFORMATION
AUXILIARY FUNCTIONS
Several auxiliary functions can be selected by connectors
and jumpers located inside the 7D01. A 25-pin Data Out
connector is also located inside the 7D01 to provide various
input and output signals for use with external equipment.
The following information describes the auxiliary functions
with procedures for making the appropriate internal
connections.
Display Clock Source Selector (P835)
Two-pin jumper which determines whether the 7D01 is to
be used for display only, or for display and data output
(serial and parallel data at the Data Out connector).
When the 7D01 is used for data displays, P835 must be set
to Internal Display Clock (see Fig. 2-2). When the 7D01 is
to be used for display and data output (serial and parallel),
P835 must be set to External Display Clock (see Fig. 2-2)
and an external display clock signal must be applied to pin
3 of Data Out connector J120 to synchronize the data out-
put. The rate per bit of the serial and parallel output data is
determined by the rate of the external display clock signal
applied to pin 3 of Data Out connector J120. If a display is
desired, as well as serial and parallel data, the external dis-
play clock signal repetition rate must be approximately
2 microseconds. The internal display clock signal is not
available as an output.
Full Display/First Trigger Selector (P617)
Two-pin jumper which determines whether data is displayed
at the first acceptable trigger after the memory has addres-
sed one full block of data, or whether data is displayed
after the first acceptable trigger.
REV B, APR 1979
When P617 is set to Full Display (see Fig. 2-2), the memory
stores one complete block of data and then accepts the
next trigger. The Full Display position is recommended for
most repetitive signal applications. If a trigger is expected
soon after a reset pulse, or if the wait between displays at
slow sample rates is objectionable, P617 can be set to the
First Trigger position (see Fig. 2-2). Refer to Synchronous
and Asynchronous Data Sampling for more information.
Signal Selector (P300)
Internal multi-pin connector P300 provides 5 signals for
connection to 3 outputs on Data Out connector J120. Any
3 of the 5 signals can be used for external use. Figure 2-3
shows the location of P300, and identifies the pin assign-
ments as they are connected when shipped from the factory.
To change signal outputs at J120, move the jumper connec-
tions at P300 (refer to Fig’s. 2-3 and 2-4).
FORMAT OUTPUT. Two outputs (P300 pins 1 and 2)
provide ECL-level outputs which indicate the channel
selected by the front-panel DATA CHANNELS switch.
Table 2-1 shows the ECL levels at pins 1 and 2 of P300 for
each position of the DATA CHANNELS switch.
TABLE 2-1
Format Output Levels
P300
DATA CHANNELS Pin 1 Pin 2
0-3 HI HI
0-7 HI LO
0-15 LO LO
2-1

Operating Instructions—7D01 (SN B020000 & up)
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VOLTAGE
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MONITOR
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VAR( +12v) POLARITY
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CURSOR
FINE POS <}- COARSE
CLOCK
QUALIFIER HORIZ
POS > MAG
HI
OFF
Lo
EXT TRIG/
QUALIFIER
INPUT
DATA OUT
LOGIC ANALYZER
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EXT CLOCK POLARITY Switch—Selects the active edge of the external clock signal applied to the C (clock) input of the Channel
0-7 Data Input connector.
SAMPLE INTERVAL Switch—Selects the data input sample rate. Sample rates from 5 milliseconds to 10 nanoseconds are provided
in a 5-2-1 sequence. A lamp behind the knob skirt blinks when the sample rate is too fast for 8-channel operation (10 nanosecond)
or 16-channel (10 or 20 nanosecond) sample intervals. When set to the EXT position, the C (clock) input is selected. The SAMPLE
INTERVAL lamp does not blink when operating in the EXT position.
Figure 2-1. Front panel controls, connectors, and indicators.
2206-3A
REV B, APR 1979

Operating Instructions—7D01 (SN B020000 & up)
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DISPLAY TIME Control—Sets the time that the stored data is displayed before a new store cycle begins. The display time is con-
tinuously variable from approximately 1 to 10 seconds, or can be held indefinitely by turning the control fully clockwise into the
co detent position.
MANUAL RESET Pushbutton (concentric with DISPLAY TIME control)—Overrides the DISPLAY TIME control and starts anew
store cycle.
DATA CHANNELS and BITS/CH Switch—Selects data from channels 0 through 3 with 1016 bits of memory per channel (0-3/
1016). Selects data from channels 0 through 7 with 508 bits of memory per channel (0-7/508). Selects data from channels 0
through 15 with 254 bits of memory per channel (0-15/254).
FINE POS/COARSE Controls—Positions the cursor intensified zone to any bit on the data display in one-bit (FINE POS) or 16-
bit increments (COARSE).
CLOCK QUALIFIER—The Clock Qualifier allows you to selectively store data into the 7D01 memory, by inhibiting or enabling
the Store Clock. The Clock Qualifier became a part of the 7D01 Logic Analyzer beginning with serial number BO86085. The
CLOCK QUALIFIER switch replaces the BYTE switch found on 7D01 units prior to BO86085; byte selection is now accomplished
through the use of an internal jumper.
HORIZ POS/MAG Controls—Horizontally positions the display with the graticule area (POS) and provides continuously variable
horizontal magnification (X1 to X10) of the display (MAG).
MANUAL TRIGGER Switch—Activates the trigger circuit.
TRIG’D Indicator—Lights on the first accepted trigger (after reset) and remains on until the store cycle is reset.
DATA POSITION Switch—Three-position switch selects data for storage in the memory after the trigger (POST TRIG), before and
after the trigger (CENTER), or before the trigger (PRE TRIG).
TRIGGER SOURCE Switch—Three-position switch derives the trigger signal from the rising edge of the channel 0 data (CH 0),
from an external signal applied to the EXT TRIG/QUALIFIER INPUT Connector (EXT), or from the Word Recognizer (W.R.).
EXT TRIG POLARITY Switch—Selects either the rising or the falling slope as the active edge of the external triggering signal.
EXT TRIG/QUALIFIER INPUT Connector—Provides input for an external signal (TTL level) to be used as an external trigger sig-
nal or as an external qualifier signal for the Word Recognizer.
Channel Switches—Sixteen three-position switches (channels 0 through 15) select the active state for each channel of data input.
The active state for each channel can be selected to be a high level (HI), a low level (LO), or to disregard the data level (X). The
amplitude of the HI and LO states is determined by the THRESHOLD VOLTAGE controls.
EXTERNAL QUALIFIER Switch—Three-position switch selects active state of the signal applied to the EXT TRIG/QUALIFIER
INPUT connector. The active state can be selected to be a high level (HI), a low level (LO), or to disregard the data level (X).
PROBE QUALIFIER Switch—Three-position switch selects the active state of the signal applied to pin Q of the channel 0-15 Data
Input connector. The active state can be selected to be a high level (HI), a low level (LO), or to disregard the data level (X). The
amplitude of the HI and LO states is determined by the THRESHOLD VOLTAGE controls.
W.R. MODE Switch—Two-position switch determines the operating mode of the Word Recognizer system. In the SYNC position,
the signal at the W.R. OUT connector goes HI on the active edge of the clock signal after all WORD RECOGNIZER conditions are
met (Channels 0 through 15, EXTERNAL QUALIFIER, and PROBE QUALIFIER). The clock input is applied to the C (clock) in-
put of the Digital Acquisition Probe connected to the Channel 0-7 and External Clock Data Input connector. In the ASYNC posi-
tion, the signal at the W.R. OUT connector goes HI after all WORD RECOGNIZER conditions are met (Channels 0 through 15,
EXTERNAL QUALIFIER, and PROBE QUALIFIER).
FILTER Control—Inhibits the HI output at the W.R. OUT connector for about 300 nanoseconds. The FILTER control is func-
tional only when operating in the ASYNC W.R. MODE and is used to prevent triggering from noise or bits that have no meaning
at that time.
W.R. OUT Connector—Provides a HI output level for external use when all WORD RECOGNIZER conditions have been satisfied.
STORE CLOCK OUT Connector—Provides ECL level store-clock signal for use with external equipment. This output will drive an
unterminated 50-ohm cable. (Do NOT terminate cable with 50-ohm load to ground.)
DATA OUT Access—Provides access to the Data Output connector (J120) inside the instrument.
Channel 8-15 and Probe Qualifier Data Input Connector—Provides probe inputs to Channels 8 through 15 and the Probe Qualifier.
Channel 0-7 and External Clock Data Input Connector—Provides probe inputs for Channels 0 through 7 and the External Clock.
THRESHOLD VOLTAGE MONITOR Pin Jack—Provides an output to monitor the dc threshold voltage of the data inputs.
THRESHOLD VOLTAGE Selector Switch—Three-position switch selects a preset threshold voltage for TTL logic levels (TTL), or
a+ to — 12-volt variable threshold voltage (VAR) as determined by the screwdriver adjustment. Also selects in TTL-VAR position
the variable threshold voltage (+ to — 12-volts) for the Channel 0-7 and External Clock Data Input connector and the preset
TTL threshold voltage for the Channel 8-15 and Probe Qualifier Data Input connector.
THRESHOLD VOLTAGE Adjustment—Provides variable threshold voltage (plus or minus 12 volts) when the THRESHOLD
VOLTAGE selector is set to VAR.
VERT POS/MAG-—Vertically positions the display within the graticule area (POS). Provides continuously variable vertical magnifi-
cation (X1 to X5) of the display (MAG).
Figure 2-1 (Continued). Front panel controls, connectors, and indicators.
REV B, APR 1979 2-3

Operating Instructions—7D01 (SN B020000 & up)
any
€
P835
DISPLAY CLOCK
SOURCE SELECTOR
SET TO
EXTERNAL
DISPLAY
CLOCK
SET TO
INTERNAL
DISPLAY
CLOCK
® SQUARE PAD DENOTES PIN 1
P617
FULL DISPLAY/
FIRST TRIGGER
SELECTOR
SET TO
FULL DISPLAY
SET TO
FIRST TRIGGER
2206-4
Figure 2-2. Internal Display Clock Source and Full Display/First Trigger Selectors.
DISPLAY-STORE OUTPUT (P300, pin 3). This output
indicates whether the 7D01 memory is in the display or
store mode. An ECL LO level indicates the memory is in
the display mode. An ECL HI level indicates that the mem-
ory is in the store mode.
TRIGGER INTENSIFY OUTPUT (P300, pin 4). During
the bit when the trigger point on the data display is inten-
sified, an ECL LO level is present at pin 4 of P300.
MASTER RESET OUTPUT (P300, pin 5). This output
indicates whether the 7D01 is in the store and display or
reset mode. An ECL HI level indicates that the memory is
in a reset mode. An ECL LO level indicates that the mem-
ory is in either the store or display mode.
INTERNAL STRAP SELECTIONS
CLOCK QUALIFIER. Equipped 7D01 Logic Analyzers
contain two additional internal strap selections. These are
2-4
the Input Select jumper for the probe qualifier, and the
Byte Select jumper that replaces the BYTE switch found
on earlier 7D01 models. Set them as follows:
INPUT SELECT. This strap selects which input (External
or Probe) will be used for the Clock Qualifier. There are
three pins, allowing two possible settings (Fig. 2-3). Place
the jumper between the center pin and the PRB pin for
Probe Qualifier use. Place the jumper between the center
pin and the EXT pin to use the External Qualifier input.
The 7D01 is factory-set for Probe Qualifier.
BYTE SELECT. This strap is located near the top center of
the 7D01; it is labeled P1493 (Fig. 2-3). It sets the display
format of the cursor readout (displayed on the crt of the
mainframe) for either 3-bit bytes (0 100 101 010 001 100)
or 4-bit bytes (0100 1010 1000 1100). Placing the strap
between the top and center pins selects 4-bit bytes; placing
the strap between the bottom and center pins selects 3-bit
bytes. The 7D01 is factory-set at the 4-bit position.
REV B, APR 1979