Section 2—7LS Service
CIRCUIT DESCRIPTION
Introduction
The 7L5 is aswept tront-end spectrum analyzer with
selectable front*end plug-in modules that permit the user
to obtain acalibrated display for anumber of different
Impedance (i.e., 50 ohm, 600 ohm. etc.). The plug-in
module contains: selectable attenuation, the first mixer,
input low-pass filter, and an input buffer selector that
trades noise figure for IM performance. Signal attenuation
In the plug-ln and gain of the IF processing chain are
controlled by areference level logic circuit in the 7L5
which provides calibrated settings in 1dB or 10 dS steps
over arange of 149 dB.
Functional Block Diagram
The input signal to the 7LS is mixed with the frequency
of the main oscillator and fed to the IF at 10.7 MMz and
amplified by the 10.7 MHz IF amplifier. Since the 7L5 input
frequency range Is 0to 5MHz, the main oscillator is tuned
and swept from 10.7 to 15.7 MHz. The frequency of the
main oscillator is controlled by two secondary (A and 6)
oscillators that use asynthesizer technique to tune and
phase lock their frequencies. The sweep frequency con-
trol circuit drives the oscillators according to the settings
of front panel DOT FREQUENCY and FREQUENCY
SPAN/DIV controls.
The signal at 10.7 MHz is processed through aband-
pass filter and amplifier, then mixed with the outputfrom a
10.450 oscillator to down-convert the 10.7 MHz to an IF of
250 kHz. Gain of the 250 kHz amplifier is controlled by the
reference level logic circuit which establishes the amount
of attenuation in the plug-in module and gain for the
250 kHz IF and Log amplifiers. The reference level is
selectable in 1dB and 10 dB steps.
The 250 kHz IFsignal is processed through the variable
resolution filter circuits for bandwidth selections of 10 Hz
to 30 kHz. The signal Is again amplified, detected, and the
video is sent through amplifier circuits that provide the
10 dB/dIv, 2dS/div. and linear gain characteristics.
The video signal is then fed to the display processing
circuits where the signal is either stored and displayed, or
if the storage mode Is not selected, the signal is passed
directly through the vertical output amplifier to the
mainframe circuit. If either or both the DISPLAY Aor
DISPLAY Blatches are enabled, the signal is converted to
digital data, stored in Aor Bmemory, then converted back
to analog data and processed through the output
amplifiers to the circuit. The vertical information Is
digitized and stored at 512 horizontal address locations
across the screen. Therefore, the horizontal sweep Infor-
mation is converted to digital data for storage, then
converted back to an analog signal for display. The
horizontal sweep ramp is processed the same as the
vertical signal. The vertical (video) information can be
averaged or peak detected.
IF Processing Chain
This block diagram shows more detail of the circuitry
involved with processing the IF signal from the 1st mixer.
Signal loss through the 1st mixer is about 9dB. The IF
output of 10.7 MHz passes through an input and 30 kHz
filter to improve flatness, then a30 kHz crystal filter
shapes the response to the bandpass characteristics of the
instrument. A-40 dBm signal is required at this point for
full screen deflection.
Signal level Is increased 20 dB by the 10.7 MHz IF
amplifier it is then fed through the 300 kHz bandpass filter
to the 2nd mixer. The 2nd LO frequency of 10.450 MHz
mixing with 10.7 MHz produces an IF of 250 kHz which Is
fed through a500 kHz lowpass filter to the 250 kHz
amplifier. The loss through the 350 kHz and 500 kHz filters
plus the 2nd mixer is about 10 dB; thus a-30 dBm signal
level is required at the input of the 250 kHz amplifier to
obtain full screen deflection.
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