Tektronix 7L5 User manual

Taktronix-
COMMnTQ} TO E}ODELLENCE
7L5
SPECTRUM
ANALYZER
SERVICE
INSTRUCTION MANUAL
Tektronix, Inc.
P.O. Box 500
Beaverton, Oregon 97077
070-31B4-01

WARRANTY
Tektronix warrants that this product is free from defects in materials
and workmanship. The warranty period is one (1) year from the date
of shipment. Tektronix will, at its option, repair or replace the
product if Tektronix determines it is defective within the warranty
period and if it is returned, freight prepaid, to aservice center
designated by Tektronix.
Tektronix is not obligated to furnish service under this warranty:
a. to repair damage resulting from attempts by personnel other
than Tektronix represent^ives to install, repair, or service the
product:
b. to repair damage resulting from Improper use or from
connecting the product to incompatible equipment;
c. if personnel other than Tektronix representatives modify the
hardware or software.
There is no implied warranty of fitness for aparticular purpose.
Tektronix is not liable for consequential damages.
Copyright ®1976. 1978 Tektronix. Inc. All rights reserved.
Contents of this publication may not be reproduced in any
form without the written permission of Tektronix. Inc.
Products of Tektronix. Inc. and its subsidiaries are
covered by U.S. and foreign patents and/or pending
patents.
TEKTRONIX, TEK. SCOPE-MOBILE, and are reg-
istered trademarks of Tektronix. Inc. TELEOUIPMENT is
aregistered trademark of Tektronix U.K. Limited.
Printed in U.S.A. Specification and price change
privileges are reserved.

7LS Service
TABLE OF CONTENTS
Psg«
SECTION 1GENERAL INFORMATION
Introduction and Description 1-1
Manual Organization 1-2
Electrical Characterlsilcs l-2
Frequency 1-2
Input 1-3
Amplitude 1-3
Sweep 1-4
Output Connectors 1-4
Environmental Cftaracteristics 1-5
Physical Characteristics 1-5
Accessories and Options 1-5
Installation 1-5
Repackaging for Shipntent 1-6
SECTION 2CIRCUIT DESCRIPTION
Block Diagrams 2-1
IF Processing Chain 2-1
Sweep Control and Frequency
Reference 2-2
Frequer>cy Control Circuits 2-3
Readout 2-5
Display Processing 2-E
Detailed Circuit Description 2-7
Sweep Control 2-7
Trigger Logic and Sweep
Control 2-11
Frequency Span and Readout 2-13
Tune Reference -^N Loops 2-13
A&B Oscillator and Control 2-14
1st LO/lst LO Lock 2-15
Reference Level. Readout, and
Timeslot 2-15
Readout and Timeslot Decode 2-18
IF Processing Chain 2-19
Variable Resolution 2-20
10 kHz &30 kHz Filters and
Post VR Amplifier 2-22
Log/Lin Amplifier 2-22
Detector and Video Amplifier 2-22
Display Processing 2-23
Horizontal and Vertical Display
Processing 2-23
Average Calculator (SN B069999
and below) 2-24
Digital Storage (SN B069999
and below) 2-25
Digital Storage and Averaging
(SN B070000 snd up) 2-30
SECTION 3PERFORMANCE CHECK
Introduction 3-1
Equipment Required or
Recommended 3-1
1. Sweep Triggering 3-2
2. Dot Frequency Range and
Accuracy 3-2
3. Display Flatness 3-3
4. Frequency Span Accuracy &
Linearity 3-4
5. Sweep Rate Accuracy 3-5
e. Intermodulation Distortion 3-6
7. Display Frequency Stability 3-7
Page
SECTION 4CALIBRATION PROCEDURE
Complete or Partial Calibration 4-1
History Information 4-1
Interaction 4-1
Equipment Required 4-1
Short Form Procedure and Record 4-2
Preliminary Procedure 4-3
1. Check/Mjuat the Reference
Oscillator Frequency 4-6
2. Check/Adjust the Calibrator
Output Level 4-6
3. Frequertcy Span/Div Calibration 4-7
4. Sweep Timing 4-9
5. 1st LO and 1st LO Phase Lock
Calibration 4-10
6. Function IF Calibration 4-11
7. Calibrate the 250 kHz. 2nd
Mixer, and 10.7 MHz Input Filter 4-12
8. Variable Resolution Calibration 4-i3
9. Digital Storage Calibration
(SN B069999 and below) 4-i6
9A Digital Storage Calibration
(SN 6070000 and up) 4.I8
SECTION 5MAINTENANCE
Introduction 5-1
Preventive Maintenance 5-1
Cleaning 5-1
Lubrication 5-2
Visual Inspection 5-2
Transistor and Integrated
Circuit Checks 5-2
Troubleshooting 5-2
Troubleshooting Aids 5-2
Finding Faulty Semiconductors 5-3
General Troubleshooting
Techniques 5-5
Corrective Maintenance 5-5
Disassembly of the 7L5 and
Replacing Assemblies 5-7
Removing the Front Panel 5-7
Removing the IF Module
Assembly 5-7
Removlr>g the Sweep Board 5-8
Removing the RF Module 5-9
Reassembling the 7L5 5-9
Internal Operational Adjustments 5-9
SECTION 6OPTION INFORMATION
SECTION 7REPLACEABLE ELECTRICAL
PARTS
SECTION 8DIAGRAMS AND CIRCUIT
BOARD ILLUSTRATIONS
SECTION 9REPLACEABLE MECHANICAL
PARTS AND EXPLODED
DRAWINGS
CHANGE INFORMATION
REV. AMAY 1978 I

7L5 Service
GENERAL INFORMATION
INTRODUCTION AND DESCRIPTION
To effectively use the 7L5 Spectrum Analyzer, the
operation and capabilities of the instrument must be
known. This instruction manual covers general service
information for the instrument. It contains the specifica-
tion. test and calibration procedure, circuit description,
and maintenance procedure for the 7L5.
The 7L5 is a5MHz spectrum analyzer with digital
storage. Frequency stability is within 5Hz/hr and center
frequency (dot) can be read with six digit accuracy
immediately after turn-on; therefore there is no need to
fine tune the display. Complex measurements and
analysis can be made with relative ease. Built-in
microprocessing circuits decode control settings, process
frequency and reference level information, and optimize
sweep time and resolution for the selected frequency
span. At turn-on, the 7L5 is preset to areference level of
-1-17 dBm (50 ninput) and center frequency of 00.0 kHz.
This provides input attenuation to protect the front-end
circuitry and amarker to verify correct operation.
The 7L5 with 80 dB or more of spurious free dynamic
range provides the ability to measure wide relative
amplitudes. Nanovolt sensitivity provides very low-level
signal and noise requirements.
The 7L5 display is fully calibrated in dBm, dBV, or
volts/div. The reference level can be accurately set in 1dB
increments.
Afront panel input buffer control increases front-end
immunity to intermodulation distortion while maintaining
aconstant reference level.
To accommodate awide variety of Impedance sources,
the 7L5 uses quick disconnect plug-in input impedance
modules of 50 Q, 75 O, 600 0, 1MO/28 pF and customiz-
ed units to meet special requirements.
When the 7L5's digital storage capability is employed,
one or two complete displays can be held in memory for
subsequent viewing, comparison, or graphic reproduc-
tion. This capability converts anonstorage, 7000-Series
oscilloscope display into astored display. The small dot
size (of the conventional oscilloscope) used with the 7L5
enhances the resolution of low amplitude signals and
other fine details that are often lost with a variable
persistence oscilloscope. In storage mode, the vertical
display may be bisected by an averaging threshold, above
which video peak detection occurs (prior to storage) and
below which video signal averaging occurs (prior to
storage). Denoted by acursor, the averaging threshold is
continuously adjustable with afront panel control. The
storage circuitry includes amaximum hold capability.
This feature allows monitoring of signals that may change
with time to provide agraphic record of amplitude/fre-
quency excursion.
The following service instructions are for personnel
qualified to service electronic circuits. Personnel not
familiar with electrical circuit operation should not
perform any service other than that contained In the
Operating Instuctlon manual.
1-1

General Information—7L5 Service
MANUAL ORGANIZATION AND
CONTENT
The abbreviations, graphic symbols, and logic sym-
bology used in the text and diagrams of this manual are in
accord with and based on ANSI Y1. 1-1972, ANSI Y 32.3-
1975, and ANSI Y32. 14-i 973 (American National Standard
Institute. 345 East 47 Street; New York. NY. 10017).
Change information is contained on insert pages at the
back of the manual. Original pages are identified by the
symbol @and revised pages are identifed by arevision
date in the lower inside corner of the page. If the serial
number of your instrument is lower than the one on the
title page, the manual contains revisions that may not
apply to your instrument. History information, applicable
to previous products, with the updated data, is integrated
when the page or diagram is revised. The following
describes the sections and information provided in this
manual.
Section 1—General Information: Contains the instru-
ment description and specification.
Section 2—Circuit Description: Provides basic and
general circuit theory. This information may be useful
when servicing or operating the instrument.
Section 3—Performance Check: Procedures to verify
that the instrument is performing within its specified
limits.
Section 4—Calibration Procedure: Test equipment
setup and adjustment procedures required to calibrate the
instrument.
Section 5—Maintenance: Describes routine and cor-
rective maintenance procedures with detailed instructions
for replacing assemblies, sub-assemblies, or individual
components. An exploded drawing is part of Section 9.
Troubleshooting procedures plus general information
that may aid in servicing the instrument are also provided.
Section 6—Options Information: Describes options to
the instrument or directs the reader to where the options
are documented.
Section 7—Replaceable Electrical Parts: Provides in-
formation necessary to order replaceable parts and
assemblies.
Section 6—Diagrams: Functional block diagrams and
detailed circuit schematics are provided. Located adja-
cent to the diagram (usually on the back of the preceding
diagram) are pictorial layout drawings that show sub-
assembly and component locations. Integrated circuit
diagrams, waveforms and voltage data for
troubleshooting or circuit analysis are also provided
adjacent to or on the diagram.
Section 9—Replaceable Mechanical Parts. Exploded
Drawings and Accessories: Provides information
necessary to order replaceable parts. The Replaceable
Parts list is cross-referenced to the Replaceable Electrical
Parts list. The exploded drawing identifies assemblies and
mechanical components.
Change Information: Provides updating information in
the form of inserts for the manual. These inserts are later
incorporated into the manual text and diagrams when the
manual is reprinted.
ELECTRICAL CHARACTERISTICS
The following electrical characterstics apply when the
7L5 Spectrum Analyzer, in combination with aPlug-In
Module, are normally installed in a7000-Series os-
cilloscope and after awarm-up of ten minutes or more.
Frequency Characteristics
Range
Input Frequency: 10 Hz through 5.0 MHz.
Dot Frequency: 0Hz through 4999.75 kHz.
Accuracy
20*C to 30»C; ±(5 Hz +2X10“ of dot readout).
0°C to 50*C: ±(20 Hz +10“ of dot readout).
Drift
5Hz/hour or less.
Residual (Incidental) FM
50 Hz/div to 2kHz/div: 1Hz (p-p) or less.
5kHz/div to 500 kHz/div: 40 Hz (p-p) or less.

General Information—7LS Service
Resolution Bandwidth
Accuracy
30 kHz—30 Hz: Within 20%of selected resolution
(6 dB down).
10 Hz: Within 100 Hz ±20 Hz (70 dB down).
The COUPLED setting electronically selects
the best resolution bandwidth foreach setting of
the FREQUENCY SPAN/DIV control.
Shape Factor
30 kHz—3kHz: 6:1 or better (60:6 dB ratio).
1kHz—10 Hz: 10:1 or better (60:6 dB ratio).
Amplitude Deviation
30 kHz—100 Hz: 0.5 dB or less.
30 kHz—10 Hz: 2.0 dB or less.
Input Characteristics
CAUTfOM I
The application of adc voltage to the INPUT of the
LI Of L2 Plug-In Modules may cause permanent
damage to the mixer circuit
Input Impedance (Nominal):
LI son
L2 75 n
L3 Selectable (50 Cl. 600 O. and 1Mn/26 pF).
Input Power (maximum input level for reference levels
of 0dBm or greater):
LI 21 dBm or 2.5 Vrms
L2 21 dBm or 3.07 Vrms
L3 21 dBm—input terminated 50 nor 6(X) O;
100 V(peak ac +dc) input 1Mn/28 pF.
Input Power (maximum input level for reference levels
below 0dBm):
LI +10 dBm
L2 +10 dBm
L3 +10 dBm—input terminated 50 fl or 600 Cl.
and 100 V(peak ac +dc) with input of 1Mn/28 pF.
Amplitude Characteristics
NOTE
If digital storage is used, an additional quantization
error of 0.5% of full screen should be added to the
amplitude characteristics.
Residual Response
Internally generated spurious signals are -130 dBm
or less referred to the input (harmonics of the calibrator
are -125 dBm) with LI or L2 plug-ln module and
143 dBV with the L3 plug-in module.
Sensitivity
The following tabulation of equivalent Input noise
for each resolution bandwidth is measured with; the
INPUT BUFFER off, the VIDEO PEAK/AVG at max cw.
and the TIME/DIV set to 10 seconds.
Resolution
Bandwidth
Equivalent Input Noise
(eoual to or better than)
LI L2 L3
10 Hz !-135 dBm -135 dBm
1
-148 dBV
30 Hz -133 dBm -133 dBm -146 dBV
100 Hz -130 dBm -130 dBm -143 dBV
300 Hz -125 dBm -125 dBm -138 dBV
1kHz -120 dBm -120 dBm -133 dBV
3kHz ,-115dBm -115 dBm -128 dBV
10 kHz -110 dBm ,-110 dBm -123 dBV
30 kHz -105 dBm '
1
-105 dBm -118 dBV
NOTE
Sensitivity is degraded an additional 8dB when the
INPUT BUFFER is on; e.g.. at 3 kHz. the equivalent
input noise would be -107 dBm instead of
-115 dBm. Noise level will increase by ap-
proximately 10 dB when operation is in video peak
mode.
Intermodulation Distortion
Inlermodulatlon products from two on-screen
signals, within any frequency span are ^75 dB down
for third order products and at least 72 dB down for
second order products.
Second and third order intermodulation products
from two on-screen -53 dBV or less signals within any
frequency span are at least 80 dB down.
@1-3

General Information—7L5 Service
With the INPUT BUFFER switch on. the third order
intermodulation products, for any two on-screen
signals, within any frequency span, are at least 80 dB
down.
Display Flatness
Peak to peak deviation, over any selected frequency
span; Quantization error must be added (see Note under
Amplitude Characteristics) if digital storage is used.
LI 0.5 dB;
L2 0.5 dB;
L3 0.6 dB;
Reference Level
Refers to top graticule line in Log mode. Calibrated in
1dB and 10 dB steps for the LI and L2 modules and
1dB/2 dB and 10 dB for L3 plug-in module.
Range L1 L2 L3
Log -128 dBm -128 dBm/ -128 dBm to
2dB/Div to +21 dBm 139 dBV to
+21 dBm/
+10 dBV
+21 dBm (50 Q).
-139 dBm to
+10dBm (600 0),
-141 dBV to
+8 dBV (Hi Z)
Log -70 dBm -70 dBm/ —70 dBm to
10 dB/Div to +21 dBm -81 dBV to
+21 dBm/
+10 dBV
+21 dBm (50 Q),
—81 dBm to
+10 dBm (600 Q),
-83 dBV to
+8 dBV (Hi Z)
Incremental Accuracy
When calibrated at -40 dBV in Log mode:
LI. L2 and L3:Within0.2dB/dB with cumulative error of
0.25 dB/IOdB.
Lin Mode Range: 20 mV/Divto200 mV/Divwithin5%in
1-2-5 sequence.
NOTE
A>sign is displayed adiacent to the reference level
readout when the reference level is not calibrated
due to an incompatible selection of controls.
Display Dynamic Range/Accuracy
Log 10 dB/Div Mode: Dynamic window is 60 dB.
Accuracy is within 0.05 dB/dB to 2dB maximum.
Log 2dB/Div Mode: Dynamic window is 16 dB. Ac-
curacy is within 0.1 dB/dB to 1dB maximum.
Sweep Characteristics
Frequency Span. Provides calibrated frequency spans
from 50 Hz/div to maximum 500 kHz/div, within 4%, in 1-2-
5sequence.
Horizontal linearity is within 4% over the entire 10 div
display.
A0-Hz/Div position is provided for time domain
operation.
Sweep Rate. Time per div Is selectable from 10 s/divto
0.1 ms/div in a1-2-5 sequence. An AUTO position permits
automatic selection of optimum time/div for the selected
resolution and span/div.
Sweep rate accuracy is within 5% of the rate selected.
Triggering. Provides two triggering sources. INT (inter-
nal) and LINE, in addition to aFREE-RUN position.
When INT is selected, ac coupled signal components
from the mainframe Trigger Source (left or right vertical
amplifiers) are used.
When LINE is selected, ac coupled sample of main-
frame line voltage is used.
Three triggering modes are; NORM (normal), SGL
SWP/READY (single sweep), and MNL SWEEP (manual
sweep).
Trigger level is ^1.0 div of Internal signal for both
NORM and SGL SWP modes over the approximate
frequency range of 30 Hz to 500 kHz.
Output Connectors
Video Out. Front-panel pin jack connector supplies the
video (vertical) output signal at an amplitude of 50 mV/div
±5% (about the crt vertical center) with source impedance
of 1kO.
Horiz Out. Afront-panel pin jack connector supplies
horizontal output signal (negative-going sawtooth that
varies from 0.0 Vdc to approximately —6Vdc) with a
source Impedance of 5 kQ.
14 REV. AMAY 1978

General Information—7LS Service
Calibrator. Front panel BNC connector supplies a
calibrated 500 kHz squarewave output signal (derived
from the analyzer's time base). Output amplitude is within
±0.15 dB of -40 dBV into the impedance of the plug-ln
module.
Environmental Characteristics
The 7L5 Spectrum Analyzer will meet the foregoing
electrical characteristics within the environmental limits
of a7000-Series oscilloscope. Complete details on en-
vironmental test procedures, including failure criteria etc.,
can be obtained from alocal Tektronix Field Office or
representative.
Physical Characteristics
Net weight (instrument only); 8pounds. 12 ounces.
ACCESSORIES AND OPTIONS
Refer to the Replaceable Mechanical Parts List for a
complete listing of the standard and optional accessories.
Options
7L5 Option 21—(Log Display)
7L5 Option 25—(Tracking Generator)
7L5 Option 28—(Readout)
7L5 Option 30—(Option 21 /25)
7L5 Option 31 —(Option 21 /28)
7L5 Option 32—(Option 25/28)
7L5 Option 33—(Options 21 /2S/28)
INSTALLATION
Initial Inspection
This instrument was inspected both mechanically and
electrically before shipment. It should be free of mars or
scratches and electrically meet or exceed the specifica-
tion. Inspect the instrument for physical damage and
check the electrical performance by the Operational
Check procedure provided within the Operators Instruc-
tion Manual. This procedure will verify that the Instrument
is operating correctly and it will satisfy most receiving or
incoming inspection requirements. If the instrument
specification is to be verified, refer to the Performance
Check procedure in this manual.
If there is physical damage or performance deficiency,
contact your local Tektronix Field Office or represen-
tative.
Installation
Install in a70(X)-Series mainframe and after a10 minute
or more warm-up. check performance. To calibrate or
service the 7L5. connect it to the 7000-Series mainframe
Interface through flexible plug-in extenders (see Equip-
ment Required; Calibration section).
REV- AMAY 1978 1-5

Section 2—7LS Service
CIRCUIT DESCRIPTION
Introduction
The 7L5 is aswept tront-end spectrum analyzer with
selectable front*end plug-in modules that permit the user
to obtain acalibrated display for anumber of different
Impedance (i.e., 50 ohm, 600 ohm. etc.). The plug-in
module contains: selectable attenuation, the first mixer,
input low-pass filter, and an input buffer selector that
trades noise figure for IM performance. Signal attenuation
In the plug-ln and gain of the IF processing chain are
controlled by areference level logic circuit in the 7L5
which provides calibrated settings in 1dB or 10 dS steps
over arange of 149 dB.
Functional Block Diagram
The input signal to the 7LS is mixed with the frequency
of the main oscillator and fed to the IF at 10.7 MMz and
amplified by the 10.7 MHz IF amplifier. Since the 7L5 input
frequency range Is 0to 5MHz, the main oscillator is tuned
and swept from 10.7 to 15.7 MHz. The frequency of the
main oscillator is controlled by two secondary (A and 6)
oscillators that use asynthesizer technique to tune and
phase lock their frequencies. The sweep frequency con-
trol circuit drives the oscillators according to the settings
of front panel DOT FREQUENCY and FREQUENCY
SPAN/DIV controls.
The signal at 10.7 MHz is processed through aband-
pass filter and amplifier, then mixed with the outputfrom a
10.450 oscillator to down-convert the 10.7 MHz to an IF of
250 kHz. Gain of the 250 kHz amplifier is controlled by the
reference level logic circuit which establishes the amount
of attenuation in the plug-in module and gain for the
250 kHz IF and Log amplifiers. The reference level is
selectable in 1dB and 10 dB steps.
The 250 kHz IFsignal is processed through the variable
resolution filter circuits for bandwidth selections of 10 Hz
to 30 kHz. The signal Is again amplified, detected, and the
video is sent through amplifier circuits that provide the
10 dB/dIv, 2dS/div. and linear gain characteristics.
The video signal is then fed to the display processing
circuits where the signal is either stored and displayed, or
if the storage mode Is not selected, the signal is passed
directly through the vertical output amplifier to the
mainframe circuit. If either or both the DISPLAY Aor
DISPLAY Blatches are enabled, the signal is converted to
digital data, stored in Aor Bmemory, then converted back
to analog data and processed through the output
amplifiers to the circuit. The vertical information Is
digitized and stored at 512 horizontal address locations
across the screen. Therefore, the horizontal sweep Infor-
mation is converted to digital data for storage, then
converted back to an analog signal for display. The
horizontal sweep ramp is processed the same as the
vertical signal. The vertical (video) information can be
averaged or peak detected.
IF Processing Chain
This block diagram shows more detail of the circuitry
involved with processing the IF signal from the 1st mixer.
Signal loss through the 1st mixer is about 9dB. The IF
output of 10.7 MHz passes through an input and 30 kHz
filter to improve flatness, then a30 kHz crystal filter
shapes the response to the bandpass characteristics of the
instrument. A-40 dBm signal is required at this point for
full screen deflection.
Signal level Is increased 20 dB by the 10.7 MHz IF
amplifier it is then fed through the 300 kHz bandpass filter
to the 2nd mixer. The 2nd LO frequency of 10.450 MHz
mixing with 10.7 MHz produces an IF of 250 kHz which Is
fed through a500 kHz lowpass filter to the 250 kHz
amplifier. The loss through the 350 kHz and 500 kHz filters
plus the 2nd mixer is about 10 dB; thus a-30 dBm signal
level is required at the input of the 250 kHz amplifier to
obtain full screen deflection.
2-1

Circuit Description—7L5 Service
The 2nd LO frequency is controlled by aphase lock
loop which uses 50 kHz and 100 kHz submultiples of a
master 10 MHz crystal controlled oscillator to drive
500 kHz and 100 kHz reference frequencies. The gain of
the 250 kHz IF amplifier is controlled by the decoded
output from the reference level counter. The reference
level counter in turn, is controlled by the front panel
REFERENCE LEVEL control. Gain of the amplifier is
adjustable in 1, 2, 4, 8, and two 16 dB steps. The
attenuators, in the plug-in module are 4dB, 8dB. and
32 dB. Combinations of attenuators and IF gain are
selected by the reference level counter and provide gain
changes of 1dBor 10 dBsteps, depending on the position
of the REFERENCE LEVEL control. The crossover point
(no attenuation and unity gain through the amplifier) is
-30 dBm.
The REFERENCE LEVEL control is aprinted circuit
switch that outputs atwo bit binary code that repeats every
four times. The code indicates the direction the control is
rotated and an IC determines whether the count is up or
down. The output code of the control, clocks acounter
which provides the reference level required to drive the
readout. Analog currents are provided by aROM which is
reading the output of the counter. When the REFERENCE
LEVEL control is pulled out. for 10 dB steps, the counter
counts in tens Instead of digits. When LIN mode is selected
or the dBm/dBV switch on the plug-in module is changed,
the readout changes the Reference Level Counter so the
crt reference level readout is In Volts/Div or dBV. Thevalue
of the constant to the counter depends on the input
impedance of the ptug-ln module. This establishes a
calibration reference level commensurate with the respec-
tive input impedance of the "L" piug-in module.
The inputs to the IF Gain and RF Attenuation Decoding
block ere the output from the Reference Level Counter
and the Log 10 or Log 2switch latches. The output
supplies four gain change lines to the IF amplifier and the
attenuator codes forthe plug-ln module. An Invalid code is
fed back to stop the counter when the reference level
reaches alower limit.
The output of the 250 kHz IF Is fed to the Variable
Resolution Filter. BandwIdths of 10 Hz to 3kHz are
selected by one filter block and 10 kHz and 30 kHz
bandwidths by asecond block. Signal routing through the
filters, is controlled by the resolution code which in turn
may be controlled by the RESOLUTION control. For
automatic or coupled operation, aROM selects the
appropriate resolution bandwidth so the bandwidth and
frequency span are compatible. If the operator selects a
resolution that is not appropriate for the FREQUENCY
SPAN selected, the ROM activates aCAL light to in-
validate the reference level reading and the readout
presents a< symbol in front of the reference level readout.
The output signal from the Resolution Filters is fed
through aPost VR Amplifier then aLog/Lln amplifier. The
response amplitude level is now either Log 10, Log 2, or
Linear depending on the setting of the log/lin latches.
These latches are activated by front panel momentary
contact pushbuttons. Log 10 control Is also fed to the IF
Gain and RF Attenuation Decoder.
The IF Is then detected and the output video signal fed
to another Log/Lin amplifier for gain adjustment between
the Log/Lin displays. Part of the output Is fed to U2005 to
provide push-pull trigger signals (+ and -) to the main-
frame and video signals to the VIDEO OUT jack on the
front panel. The main video signal is fed to the display
processing circuits where it Is processed either through
amplifiers to the mainframe for display, or, if the 7L5 Is
operating in the store mode, the signal is stored In
memory, and then displayed as the memory is refreshed or
updated.
Sweep Control and Frequency Reference
The Sweep Control circuit uses an IC that features;
sweep gating, bright baseline, holdoff timing, automatic
free run. lockout, single sweep and single sweep ready
light control. The gate signal drives the sweep generator
which in turn sends asweep through the Manual Sweep
switch to the Display Processing and circuitry related to
the sweep for the Aand Boscillators. Inputs to the sweep
control IC include triggering source and mode signals.
Trigger modes are set by latches that are actuated by front
panel momentary contact pushbutton switches.
When SGL SWP is selected, the sweep is locked out
until the SGL SWP button is pushed again. The circuit is
now armed and the sweep will run If the trigger source is
FREE RUNorwhena trigger signal arrives. Abuilt In delay
of approximately 10 seconds allows the sweep to run if no
trigger arrives (rtot In 0Hz span). This keeps the memory
capacitors for phase lock loop, of the Aand Boscillators,
refreshed.
When MNL SWP Is selected the Sweep Generator Is
used as a 100 second timer to refresh the memory
capacitors. The Sweep Control allows the Sweep
Generator to free run; however, the Manual Sweep switch
now selects the voltage output of the LEVEL/SLOPE
control for the Sweep Horizontal signal.
2-2

Circuit Description—7L5 Service
When the sweep mode is NORM, sweep operation is
conventional. The LEVEL/SLOPE control selects the
triggering level and slope unless the mode is MNL SWP. It
then becomes amanual sweep control.
The sweep generator contains an end of sweep com-
parator that outputs apulse which is fed back to the sweep
control 1C to terminate the output gate and inhibit the
sweep. The end of sweep pulse is OR'd with an output line
from the phase lock logic circuit, which goes high at the
end of the gate pulse period and holds this state until the
sweep control circuit has stabilized about (50 ms) then it
pulls the Ready line low The state of the Iand Sense lines,
from the dot frequency control and phase lock loop circuit
must also be correct before the phase lock logic circuit will
permit the sweep control and sweep generator to start
another sweep. Sweep lockout, by the dot frequency and
phase lock loop circuits, is Ignored when the Frequency
Span/Div is ZERO.
The sweep rate is controlled by the TIME/OIV selector
unless AUTO position is selected. When AUTO is
selected, sweep rate Is controlled by aROM which looks at
the FREQUENCY SPAN/DIV and RESOLUTION selec-
tions to determine the sweep rate. The RESOLUTION and
FREQUENCY SPAN/DIVselectorsare both printed circuit
switches that feed theiroutput into ROMs. The ROMs then
control the frequency span and resolution bandwidth of
the instrument and provide readoutdatato the circuit. The
RESOLUTION selector has aCOUPLED position where a
ROM determines the optimum resolution for the selected
FREQUENCY SPAN/DIV. In the manual positions of the
RESOLUTION and TIME/DIV selectors, the uncal com-
parator monitors the sweep rate versus resolution
bandwidth and Frequency Span/Div setting. It lights an
UNCAL indicator when the display is not calibrated. At the
same time a>symbol precedes the Reference Level
readout to indicate that the readout is not calibrated.
Frequency Reference
The center frequency of the span is programmed into
4^N counters which are part of afrequency and phase lock
synthesizer loop. Two of these -^N control loops set and
lock the frequency of two secondary (A &B) oscillators
which are part of athird loop that controls the 1st LO
frequency. The 1st LO center frequency, therefore, is
dependent on the programmed data in the -^N counters.
The frequency span of the 1st LO depends on the ramp
amplitude out of the sweep attenuator circuits. During
retrace time, the secondary oscillators are locked to the
center frequency. During lock the sweep reduces to a
voltage of zero. The time shared dot position is therefore,
derived from an equivalent sweep voltage of zero. Fre-
quency of the dot position is displayed by the crt readout.
Accurate frequency measurements can be performed by
tuning any desired segment of the display under the
frequency dot and read out on the crt. In most cases
readout accuracy Is <1% of the display span or within
±50 Hz.
In all frequency span positions except MAX span, the
frequency dot is at the center or start of the display. In
MAX span the center frequency of the span is 2.5 MHz.
The frequency dot moves across the display as the center
frequency is tuned. The frequency readout accuracy of
the dot remains constant.
Asimplified block diagram of the Frequency Reference
circuitry is shown in Fig. 2-1. The frequency to be
measured (fm). is fed to the 1st mixer in the plug-in
module, where it is mixed with the output from the 1st LO.
The output IF of 10.700 MHz is fed to the 2nd mixer where
it is mixed with 10.45 MHz from the 2nd LO and converted
down to a250 kHz IF. The 2nd LO frequency is referenced
to 500 kHz. asubmultiple of a10 MHz Master Oscillator.
Frequency Control Circuits
As previously described, two divide by "N" (Ni and N:)
control loops, with their oscillators, determine the fre-
quency of the 1st LO. A11.1 MHz to 16 MHz, "A" oscillator
mixes with the frequency of the 1st LO (10.7 to 15.7 MHz).
The difference is compared with the 40th sub-harmonic of
a 12 to 16 MHz "B" oscillator in aOf/A0 detector. Any
difference produces an error voltage that is fed back
though asumming amplifier to pull the 1st LO into a
locked mode with both Aand Boscillators.
The frequency of both secondary (A and B) oscillators
is controlled by -rN loops. The value Nis determined by
the DOT frequency control. This control tunes the A
oscillator in 100 kHz increments and the Boscillator in
10 kHz steps. (100 kHz and 10 kHz increments originate
from the 10 MHz master oscillator.) The frequency of the B
oscillator is divided down by 40 so the frequency Into the
comparator steps in 250 Hz increments. If the DOT
frequency is 0Hz, the frequencies of the Aand Boscillator
are 11.1 MHz and 16.0 MHz. The input to the phase lock
comparator (Af/A0 detector) from the -r40 source is
400 kHz (16 MHz -r 40). The difference frequency out of
the Aoscillator and the 1st LO mixer must also be 400 kHz
for the system to lock. Since the Aand Boscillators are

Circuit Description—7L5 Service
referenced to the same reference (10 MHz master os-
cillator) the 1st LO is locked to 10.7 MHz (11.1 MHz-
400 kHz). Frequency changes to either Aor Boscillators
require achange in the value of "N" that is loaded into
up/down counters for the respective control loops.
The DOT FREQUENCY will tune either the Boscillator
In 10 kHz steps or the Aoscillator in 100 kHz steps. The
frequency of the 1st LO (and the dot) can therefore be
tuned in 250 Hz or 100 kHz steps depending on which
latch is enabled.
Amore detailed block diagram of the Frequency
Reference circuit is provided by the Sweep Control and
Frequency Reference Block Diagram (la) In the Diagrams
section.
The 10 MHz of the crystal oscillator or Master
Oscillator frequency is divided down to 100 kHz and
SCO kHz by two counters. 100 kHz is fed to one input of a
phase comparator for the Aoscillator loop. It is also
divided down to 10 kHz for application to one input of a
phase comparator for the Boscillator loop. The output
voltages of the comparators are applied through logic
circuitry to memory capacitors in each oscillator loop. The
logic circuitry gates the comparator reference voltage to
this memory circuit during retrace or the Lock portion of
the sweep cycle. This charge or reference voltage on the
memory capacitor is summed with the sweep ramp from
the frequency span (Sweep Control) circuit. The resultant
voltage is applied through amplifiers to the Aor B
oscillator to control their frequencies.
The Aoscillator output is mixed with the 1st LO
frequency and the difference frequency applied to one
input of aphase comparator and loop filter. The other
input, to the phase comparator, is the 40 sub-frequency of
the Boscillator. Any difference between the two frequen-
cies produces an error voitage which is applied to the 1st
LO to correct and control the 1st LO frequency. The
oscillator frequencies can be expressed as;
fflKLO) ~f|A OKI ~f|Bjjc|.
•0
FREQUENCY REFERENCE BLOCK
RRST MIXER SECOND MIXER
21M-1
Fig. 2-1. Frequency relerci>ce block diagram.
2-4 REV. AMAY 1978

Circuit Description—7L5 Service
Output frequencies of the Aoscillator and Boscillator
are fed back to A-r Nand B-5- Ncircuits. The value "N"
assumes depends on the setting of the dot frequency
control circuit. For example, afrequency of 16 MHz out of
the Aoscillator requires an "N" factor of 160 to divide
16 MHz down to 100 kHz, so the frequency into the phase
comparator equals the 100 kHz at the other input to the
comparator. As the dot frequency is changed, the "N"
factor into either the A N or 6 N circuit changes to
increase or decrease the Aor Boscillator frequency. Since
the 1St LO is slaved to these oscillators, its frequency must
also change.
The Frequency Span/Div circuit determines the
amount the Aor Boscillator frequency is swept. The
sweep horizontal voltage is applied through an attenuator
and binary switch to asumming point, either in the A
memory or Bmemory reference voltage line. The FRE-
QUENCY SPAN/DIV selector sets the amount of sweep
attenuation and thus the frequency span. The output of
the SPAN/DIV selector is also fed to aROM which looks at
the selected span and chooses one of three sweep outputs
from the binary controlled switch. These ramps are used
for different span/div frequencies (50 Hz to 2kHz, for the
Boscillator frequency loop, 5kHz to 200 kHzandSOO kHz
or MAX span for the Aoscillator loop). Since the loop
sensitivity of the two oscillator loops differ by afactor of
100, the attenuator settings are used twice to cover the full
range (50 Hz to 500 kHz) of the FREQUENCY SPAN/DIV.
When the FREQUENCY SPAN/DIV is not in the MAX
span position, the MAX switch closes to allow adot marker
voltage to be summed in with the Aoscillator control loop
so the dot can be positioned along the left portion of the
5MHz display.
Aturn-on circuit (on the left side of the diagram) forces
afree run andnormalselectionof the trigger circuits, adot
frequency of 000. reference levelof-l-l7 dBm, and Display
A. Display Bstore modes when power is applied.
Readout
Ablock diagram of the Readout circuits is shown in Fig.
2-2. Along the left side are the front panel selectors. The
DOT FREQUENCY control drivesaTEKTRONIX IC which
provides the column data for the top horizontal readout
location on the crt. Current for the Hz and kHz readout is
supplied by aresistor matrix. Row data also comes from a
fixed resistor matrix.
FROM FIXED
A37 TOP
AHORIZONTAl
B37
A37
TOP
RIGHT VERTICAL
B37
A38 BOTTOM
AHORIZONTAL
B3B
A38 bottom
RIGHT VERTICAL
B3B
3164-7
Fig. 2-2. Function block of readout circuHs.
2-5

Circuit Description—7L5 Service
The REFERENCE LEVEL drives U2235 which provides
column data current for the top right vertical readout
position. The output of the U2235 Is influenced by the
setting of the dBm/dBV selector and the offset set by the
input impedance of the plug-in module and the reference
level selected. The LIN switch latch changes the row data
so the readout Is in nV.pV. and mV instead of dBm or dBV.
(The column data is also changed so the correct numbers
are read out.)
The FREQUENCY SPAN/DIV drives ROM U800 which
provides the column data for the bottom Ahorizontal
position. Row data is from afixed resistor matrix. If zero
span is selected, it reads in time/division.
The RESOLUTION selectordrives aresistor matrix that
provides both column and row data to the bottom right
vertical part of the display. The column data also gets the
10 dB, 2dB, or; if LIN mode is selected, that portion of the
display is aspace.
Display Processing Block Diagram
The video signal from the IF processing chain is fed
through switch U735B to an A/0 converter. The digital
data from the converter is then placed in memory. It is read
from memory and displayed at the command of Display A
and Display Bselectors. Before the vertical data is placed
in memory, it may be either averaged or peak detected.
Vertical data is placed at an address in memory derived
from the sweep horizontal waveform. How the address is
derived will be described later.
The address is derived from the horizontal sweep ramp.
This is a10 volt negative-going ramp centered around the
Dot frequency. The ramp is offset (op to plus or minus 10
volts) as the dot frequency is tuned so the sweep ramp
range can run from -10 Vto +10 V(—10 Vto 0Vat one
end and 0Vto +10 Vat the other). The sweep Is
converted, by the horizontal A/0 converter, to address
data for memory. Memory consists of a4096 (512 x6) bit
RAM and a1024 (1024 x1) bit overflow or offset RAM. The
4096 bit RAM has 512 horizontal access lines. Memory is
divided into an Aand Bsection with 256 lines assigned to
each. Address locations are determined by the LSB (least
significant bit) of the horizontal address word. Since the
LSB of this word alternates with any count, the Aand B
locations in memory are adjacent with the odd bit
assigned to Amemory and the even bit to Bmemory
sections.
The horizontal address is a10 bit word. The first 9bits
(2*) are derived from the sweep ramp and stored In the first
RAM. The tenth bit (MSB) is stored intheoverfloworoffset
RAM. This tenth bit signifies the offset (to the right or left
of center screen) of agiven address and since the offset
can be up to ±10 V. a20 volt ramp capability is provided.
At the slower sweep speeds, there are numerous words
of vertical data for each horizontal address location. These
numerous words of vertical data are averaged, by the
average calculator, so with a10 second sweep rate, up to
20,000 words are averaged at ahorizontal address. At the
2ms sweep rate, only four words would be averaged.
Referring to the lower left side of the diagram, the 1st
LO tune voltage ramp Is fed to an absolute value circuit,
which looks at the ramp excursion. If the ramp exceeds
certain limits, the output from the comparator is an
overspan signal which opens the video path through
switch U735B. Adc level is placed on the line to provide a
baseline for the display. Unless overspan is detected, the
video signal is fed to display switch U735C and the vertical
analog-to-digital (A/D) converter. The video information
Is converted to an 8bit data word that appears in serial
form on the Data Out line. The clock for this converter is
1MHz. derived from the 10 MHz master oscillator, so the
vertical data bits are 1ps apart. Since there are 8bits per
word plus async pulse, each word takes 9ps or the word
rate Is 111 kHz. The vertical data out, in serial form, then
goes to an average calculator where it is either averaged or
peak detected. The output (on the Math line) is then stored
at some address in memory.
At the end of an 8bit vertical word async pulse is sent
out on the EOC (end of conversion) line to the display
control timing block and through the synchronizer to the
average calculator. When the sweep horizontal signal has
traversed far enough to generate anew horizontal ad-
dress, the EOC starts athree cycle sequence that writes a
vertical word in memory at that address. This process
requires 27 /.is (3 x9/us). The rest of the time Is utilized in
the display mode to read from memory. At the beginning
of the three cycle process the first cycle generates Start
Divide to the average calculator. The average circuit
divides the accumulated vertical data by the number of
words during that period, and the resultant or quotient is
gated into memory on the Math line, when the second
cycle or Write Cycle arrives. Write Cycle signal Is
generated only when Valid is present. Valid is not present
during retrace or when the dot frequency Is changing.
2-6 REV, AMAY 1978

Circuit Description—7L5 Service
The output of the horizontal display generatorconsists
of readout addresses to memory and asynthesized
horizontal sweep ramp for the Store horizontal line.
Therefore, as the vertical data is read from memory, a
corresponding change occurs in the horizontal sweep
voltagesothevertical data written in memory is duplicated
and displayed appropriately when It Is read out. Data Is
stored in memory at the rate set by the Time/Olv selector;
however, it is read from memory at aconstant rate.
If Display Ais selected, the LSB for the address out of
the horizontal display generator remains at. The counter
counts In odd number sequence so only data in Asection
of memory Is read. If Display Bis selected, then the
counter counts in even number sequence and data in B
memory, is read out If Display Aand Display Bare
selected then the LSB for the address alternates and data
is read first from Athen from Bmemory. If Save Ais
selected, A memory Is not updated during Write Cycle If
Display AIs selected along with Save A. then the data
stored In A, when Save Awas pushed, is read out.
logic also provides blanking and unblanking to the Zaxis
by blanking just before the dot transition and unblanking
during dot presentation. It also blanks during the transi-
tion back to normal vertical andhorizontalpositioning.
Data into Zaxis and dot logic are Zero Span. Display Valid,
and the mainframe data such as Channel and Mode
information.
Peak/Average reference level originates with the
PEAK/AVERAGE front panel control- This reference is
compared with an analog signal out of the vertical analog-
to-digltal converter. If the vertical signal exceeds the
reference level set by the control, the average calculator
selects peak value. Signals below this reference are
averaged The control functions as aPeak/Average selec-
tor only in the Store mode. Division between average and
peak display is indicated by acursoron screen. In the non-
store mode the control operates as abaseline clipper.
Vertical information below the level set by the control is
blanked.
Vertical data out of memory goes to the vertical display
generator on the Memory Data line. It Is converted to
analog data then processed to the display circuits. A
timing signal, from the vertical analog to digital converter
block, controls when data Is read from memory. Data can
only be read during the Read Cycle. When either Display A
or Display BIs selected, the display control block sends a
Store signal to both the vertical and horizontal display
switches (U735A, U375C) Both switches then select only
data from the vertical display generator and the synthesiz-
ed sweep, from the horizontal display generator for the
vertical and horizontal output stages
The inverted sweep containing dot marker position is
summed with the "dot position" when Q735 is on. at the
Input to the horizontal output stage. The summation of
minus sweep with dot position plus "dot position" is minus
sweep. This is amplified by the output amplifier and
applied to the crt deflection plates. When Q735 is off. only
the "dot position" is applied to the output ampliflerand the
crt deflection plates. The dot Is therefore displayed
independent of sweep Sweep horizontal is also applied
through aseparate amplifier to the front panel HORIZ
OUT jack and pin A3 of the mainframe interface.
This completes the block diagram description for the
7L5 circuitry.
DETAILED CIRCUIT DESCRIPTION
Sweep Control ^^
This portion of the circuit description covers the Auto
Sweep. Frequency Span and its Readout, and Trigger
circuits. Diagrams 3through 6cover these circuits.
The Auto Sweep circuit sets the sweep rate according
to the TIME/DIV selections: or, if the TIME/DIV selector is
set to the AUTO position, the circuit automaticaily adjusts
the sweep rate asafunction of the FREQUENCY
SPAN/DIV and RESOLUTION selector settings. If the
RESOLUTION is at the COUPLED position, with the
TIME/DIV at AUTO, the sweep rate and resolution are
automatically computed asafunction of the selected
frequency span to keep the display calibrated. When the
sweep rate is not compatible to the resolution and
frequency span, the circuit activates afront panei UNCAL
Indicator.
The Zaxis and dot logic block determine when the dot
is to be displayed. An output called Dot is fed to
multiplexer switches in the vertical and horizontal lines.
This low disconnects the verticai and horizontal drive to
the mainframe and positions the dot appropriately. The
The TIME/DIV selector assembly outputs a5bit
address, as shown in the truth table. Four bits of this
address are fed to one side of four section multiplexer
U525. The Binputs to the multiplexer are selected when
the Select (pin 1] line is high, so the TIME/DIV assembly
output Is switched through to the sweep generator circuit
2-7

Circuit Description—7L5 Service
{Diagram 6). If the AUTO position Is selected, U530O is
enabled. This pulls pin 1of U525 low and switches the
multiplexer to its Ainputs. The sweep rate is now a
function of the address out of ROM U515.
The output address of ROM U515 Is a function of the
FREQUENCY SPAN/DIV and RESOLUTION control set-
tings. This address is also fed to the Binputs of com-
parator U540 where it is compared with the TIME/DIV
setting. If the code from the TIME/DIV selector is less than
the code out of ROM U515, the output of comparator US40
goes high and, when inverted by U520E, pulls the Uncal
line low to activate the UNCAL light and generate a(>)
symbol as a prefex to the reference level readout.
When the RESOLUTION selector is in the COUPLED
position, ROM U515 selects resolution that is compatible
for the frequency span selected. The CMOS outputs for
the FREQUENCY SPAN/DIV assembly are converted to
TTL by the buffers (U510A, B, D, E, and F) to accom-
modate ROM (U650) in the Frequency Span circuit.
The outputs of the TIME/DIV and FREQUENCY
SPAN/DIV selectors, are Darlington pairs which pulldown
to about 1.0 volt. The low state is offset two junctions
belowground, byCR64and CR66throughR512, to—15 V;
so alogic low at the output is about ground potential.
Logic high is pulled up through resistors in resistor pack
R60.
timing resistors as indicated by the address table within
the symbol for U695 Voltage reference for the selected
timing resistor is the output of operational amplifier
U690A. When 0660 is turned on. timing voltage is
Increased by afactor of two which increases the sweep
speed proportionately. Table 2-1 lists the Time/Div selec-
tions with the output addresses and the corresponding
addresses for U695. 0680 gate, and pin 9of U680C. For
example: 50 ms connects timing resistor R694, connects
timing capacitor C712B, and turns off 0680 to add R686as
part of Ri (input resistor) for operational amplifier U680A,
The Miller integrator Is gated on by the +Gate signal
into the base of 0705. This gate switches 0700 off and
allows the Miller Integrator output to ramp up. The output
of the sweep generator Is fed to one input of comparator
U575A whose output switches high when the input ramp
reaches the reference level, set by the divider network on
the other input of the comparator or about 8.9 volts. This
Sweep Inhibit signal is fed back to the sweep control 1C to
terminate the sweep gate. Unless Manual sweep has been
selected, the sweep ramp Is also fed through multiplexer
U680B to operational amplifier U685A. Gain of U685A Is
about 1,2 producing an output ramp of approximately 10.4
volt. This ramp is fed to the frequency span attenuator
circuit, containing R660-U665, and to the horizontal
sweep processing circuit.
TABLE 2-1
Truth Table for TIME/DIV Selections
The arm of the RESOLUTION switch is connected to
the collector of 070. With resistor pack R60A in thecircuit,
the transistor is saturated and ground return is furnished
to the switch. With the resistor pack removed the base of
the transistor is connected to the remote program line and
the output Is dependent on the external program. Diodes
CR74 through CR76 provide isolation.
There are five lines that determine the sweep speed:
four from multiplexer U52S and the fifth from the output of
NAND gate U535C. The sweep generator (Diagram 6)
consists of Miller Integrator U700 with timing capacitors
C712A and C712B. Capacitor C712B is switched into the
timing circuit when the input line to pin 9of multiplexer.
(U80C) is low. C712 is in the circuit for sweep rates of
10 ms or slower. When the level at pin 9is high, the switch
opens, and C712B is out of the timing circuit.
Timing resistors are selected by multiplexer U695.
Control lines A, 8. and C(pins 11, 10. and 9) select the
TIME/DIV SWEEP CONTROL
ST
5
ST
4
ST
3
ST
2
ST
1AU695 Bc0680
GATE U680C-9
ms
.1 0000000111
.2 00 0 0 10001
.5 0001 1 00001
10 0 10001 1
2 0 0 1010101
5 0 0 1110100
10 010 0 0 0 0110
20 0 10 0 100 0 0
50 0 1010 0 0 0 0
sec
,1 01 1 0 0 0 1110
.2 0110101100
.5 01 1 1 010 0 0
11000 0 101 1 0
2100 0 110100
3 0 0 110 0 0 0
10 0100111 1 0
AUTO 11011010
@2-8

Circuit Description—7L5 Service
Moldoff timing capacitors, for the sweep control 1C
(U580 on Diagram 5), are C728 and C726. When the logic
input (pin 11) to multiplexer U680A is low. C726 parallels
C728 to increase the time constant. The other output of
U680A (pin 13) drives the base of the transistor in U585C
to provide Intensity limiting to the mainframeat the slower
sweep speeds (below 10 ms/div). At faster speeds, the
input line is high and pin 13 is grounded, so U585C is
biased off to remove intensity limiting. In manual mode or.
when operating with spans other than 0Hz. the low state
into U595D turns U58SC on to provide Intensity limiting.
Intensity limiting is therefore provided for manual sweep
operation, sweep rates below 10 ms/div, and 0Hz span
operation.
Multiplexer U665 selects the attenuation ratio for the
10.4 volt sweep ramp through resistor pack R660. The
attenuation address (in at A. B, and Cof U665) determines
the attenuation. The sweep out of U665 is then fed through
multiplexer U670 to one of four output tines. Three of
these (1A, 1B, and #2) drive the Aand Boscillators which
establish the frequency span. The fourth line is for
optional use if desired, the address within the IC symbols
indicate the sweep ramp path through R660and U670. For
example: when the Input address to U665 is 110. pin 2of
U665 is connected to the output. The sweep is attenuated
through R660 by the combination of the 4.00 kand 1.33 k
resistors. Table 2-2 and 2-3 show the input and output data
for ROM U650and multiplexers U665and U670. Table 2-2
shows the Data Out of U650with (he corresponding sweep
output line. For example: with a FREQUENCY SPAN/DIV
of 50 kHz, input lines Aand Bto U670 are low. Address 00
(into U670) switches the sweep output of U665topin 12 of
U670 to drive the Boscillator. Table 2-4 lists the sweep for
each SPAN/DIV setting. The table bypasses ROMs U510
and U650.
The Max Span Dot Position adjustment (R655) offsets
the dc level of the memory voltage so avoltage of 0
corresponds to center screen (2.5 MHz). It also offsets the
dc level of the 1st LO tune voltage so acenter frequency of
2.5 MHz corresponds to 0Vat the output (pin 3) of U675B
for centering the overspan clipping.
The 1st LO tune voltage is apositive-going ramp,
centered around some dc level set by the DOT FRE-
QUENCY control. The amplitude of this sweep voltage
depends on the setting of the FREQUENCY SPAN/DIV
selector. U675A, U575C, and U575A limit the excursion of
the waveform. U675B. anon-inverting amplifier, drives the
negative input of operational amplifier U675A. As the
sweep ramp crosses Its center point, diode CR660 dis-
connects and the polarity of the Input signal to the
comparator U575C reverses. The input waveform to pin 7
of U575C is therefore Vshaped. This input is referenced
(by avoltage divider) to about 4.5 volts. If either excursion
of the Vshaped waveform exceeds this reference, a
positive output signal is produced which represents an
overspan. This overspan voltage is fed to amultiplexer
(U735B), in the video processing chain, and the output of
TABLE 2-2
Input and Output Data for U650 (8223 ROM)
FREQ
SPAN/DIV INPUT ADDRESS(BINARY) OCTAL
EOUIV DATA
OUTPUT(BINARY) OCTAL
EOUIV SWP
A. A. A} A, Ao 8, B. B, B: Bi Bo
MAX SPAN 1101 1 33 1 1 010101325 1A
200 kHz 11 1 1 37 001 1 0101065 IB
100 kHz 1 1 036 10 0 10101225 IB
50 kHz 110 0 131 101 1 0101265 1B
20 kHz 1110135 0 0 10101065 1B
10 kHz 110 0 34 10 0 10101225 IB
5kHz 10 0 123 1010101265 IB
2kHz 101127 0 101 1 0166 #2
1kHz 100 26 10 0 1 1 0 326 #2
.5 kHz 10 0 0 121 1 1 10110366 #2
2kHz 1010125 0 110110166 #2
.1 kHz 10 0 0 24 1010110 326 #2
50 Hz 010113 1 1 0110 366 «2
0Hz 0 0 10 0 04 101
B
Control
Line U670
0111
A
Control
Line U670
257 0
@2-9

Circuit Description—7L5 Service
the detector is disconnected from the vertical output
amplifier. The vertical display now becomes adc voltage
which produces atrace at the bottom of the screen. In non-
store mode the overspan portion is blanked.
The lower half of multiplexer U670 provides adc offset
to the sweep ramp. In the MAX span position, the DOT
FREQUENCY control moves the dot (readout) frequency
across the screen. In other SPAN/OIV positions, the dot is
at center screen unless it is moved by the DOT MKR
control. The dot always represents readout frequency.
The dc level, set by the DOT MKR control (R50) feeds
three of the inputs for the bottom half of U670. If the
control address to U670 (from ROM U650) is anything
except 10, thedc level of the DOT MKR control is switched
through U670 to the input of operational amplifier U6855.
Address code 10 occurs only when the FREQUENCY
SPAN/DIV selector is in MAX span position. The offset
voltage now comes from the synthesizer memory circuits.
The dc output of U665B sets the input dc level of the sweep
amplifier U685A to provide offset to the Sweep Horizontal
ramp.
TABLE 2-3
Input Data to the Frequency Span "ROMS"
FREQ SPAN/DIV FREQ SPAN/DIV SWITCH U51S INPUTS U650 INPUTS
TC TJ TB TK TD A8 A7 A6 A5 A4 A4 A3 A2 A1 AO
MAX 00 0 a111101 1 01 1
.2 MHz 0001011111 11111
.1 MHz 00011 1 1 1 01 11110
50 kHz 0010 0 0 11101 1 001
20 kHz 0011001111 11101
10 kHz 0 0 1 1 101101 1110 0
5kHz 01000 101 1 01001 1
2kHz 0101010111 10111
1kHz 0101 1 10101 1 01 1 0
.5 kHz 01 1 0 0 0 0 1 1 0100 0 1
.2 kHz 01110 0 0 1 1 1 1 0101
.1 kHz 01111 0 0 101 1 0100
50 Hz 1000 0 1 1 0100101 1
0Hz 11111 000010 0 10 0
TABLE 2-4
Input and Output Data for
FREQ SPAN Multiplexers, Bypassing U510 and U650
FREQ SPAN/DIV FREQ SPAN/DIV SWITCH U670 0665
TC
(FS5)
TJ
(FS4)
TB
(FS3)
TK
(FS2)
TD
(FS1) BmSWP CBA
MAX 0000 0 10H01
.2 MHz 0 0 10 0 0 000
.1 MHz 0001 1 0 0 001
50 kHz 0 0 00 0 1B 1 1 0
20 kHz 0 0 10 0 01B 10 0
10 kHz 001110 0 1B 101
5kHz 0 0 0 0 001B 010
2kHz 0 0 1011#2 00 0
1kHz 01011 1 #2 001
.5 kHz 01 1 0 0 11#2 1 1 0
.2 kHz 0101 1 #2 100
.1 kHz 011 1 #2 101
50 Hz 10 0 1 1 #2 010
0Hz 11111010100
@2-10

Circuit Description—7L5 Service
Trigger Logic and Sweep Control
Sweep and holdoff timing are controlled by 1C US80.
This 1C provides triggered, single sweep, and free run
operation. Trigger signals (+ Trigger In. -Trigger In. and
Line) from the mainframe, are processed through U600
(which contains acomparator and gate) to the trigger
input (pin 4) of U580. The triggering mode (Int. Line, and
Free Run) is selected when the respective line to the
trigger logic circuit is pulled low by the output of front
panel latches. These latches are activated by front panel
momentary contact switches. Sweep mode (Normal.
Manual, or Single Sweep) is also set when their respective
lines are pulled low. Other Inputs to this circuit include:
Zero Span logic line, which goes low only when FRE-
QUENCY SPAN/OIV is at the 0 Hz position. Sense Bus,
which clocks either at the 100 kHz or the 10 rate until
the synthesizer completes Its lock up, and Iline, which
goes low when the dot frequency is changed so that the
frequency loops must relock to the new center frequency.
Fig. 2-3 is atiming diagram illustrating the sequence of
events that start with the sweep inhibit pulse into pin 1of
U580. The sweep inhibit pulse terminates the gate output.
Aholdoff pulse is asserted out of inverter U565A to the
input of U575B. The output of U575B is inverted by U565E.
and gated through U570A to maintain sweep inhibit.
Holdoff timing (pin 11,U580) is set by circuitry on Diagram
6. At the time sweep Inhibit is generated,the output of
US60A goes low to generate Lock Pulse. Since the Zero
Span line at pin 5of U560B Is held low for frequency
domain displays. Lock Pulse Is gated through U560B to
trigger one-shot multivibrator U590B. The Qoutput of
U590B now provides Trigger Inhibit for sweep control 1C
U580. This output is also fed back through U560A to
maintain Lock Pulse.
When Lock Pulse is asserted, the Sense Bus begins to
clock pulses in (at 100 kHz or 10 kHz rate, depending on
the Span/Div setting) until the synthesizer locks. This
clock pulse keeps U5906 in an unstable state until the
synthesizer locks up. The time constant (R593 and C593)
for U560B maintains this state for an additional 50 ms.
Trigger Inhibit is then terminated and U580 is ready for a
trigger. The sweep, however. Is still held off by Sweep
Inhibit at pin 1.
U56SD and U565C use acommon pull-up resistor
(R840F) so the output of either affects the other. They
operate as a NOR gate. Therefore, alow is maintained at
pin 4of US60B when US906 is in its triggered state.
Fig. 2-3. Timing diagram ol trigger logic events.
Trigger Inhibit and Lock Cycleare initiated either when
the center frequency changes or at the end of sweep.
When Lock Pulse and Trigger Inhibit terminate, the
positive-going edge of Lock Pulse triggers one-shot
multivibrator U590A. The output from U590A is inverted
(U565B) and applied to "NAND" gate U570A. Since there
is no negative Gate at this time, the resultant high out of
U570A maintains Sweep Inhibit (at pin 1of U580) to keep
the sweep locked out. The duration of this period is either
500 ms or 40 ms depending on the state of Q591. QS91 is
switched off to increase the timeconstantwhenahlghout
of ROM U5356 (Diagram 3) is applied to the base. This
occurs for the 10 Hz or 30 Hz resolution selections. The
Sweep Inhibit period is therefore extended 500 ms or
50 ms (depending on the resolution) before the sweep
control 1C U580 will accept another trigger. This provides
time for pulses that may be generated in the variable
resolution filters to decay
Bright Baseline Automatic is Initiated about 10 s after
end of sweep if no trigger arrives to trigger U560. The 1C
switches to automatic or free run operation when the
BrightBaseline Timing input (pin 12, U580) charges high
after Lock Pulse terminates. Charge time Is set by R610
and C616.