Tektronix 7d12 Operating instructions

T

ektr

onix, Inc.

P.O. Box

500

Beav

e

rt

on, Oregon

97005

070

-1

470

-

00

TEKTRONI»

7D~2

AID

CDNVERTER

SERVICE

INSTRUCTION

MANUAL

Serial Number

Firs!

Printing

JUNE

197

4

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WARRANTY

All

TEKTRONIX

instruments

are

warranted

against

defective

materials and

workmanship

tor

one

year.

Any

questions

with

respect

to

the

warranty

should

be

laken

up

with

your

TEKTRONIX

Field

Engineeror

representative.

All

requests tor repairs

and

replacement

par'l

should

be

directed

to the

TEKTRONIX

Field

Office

or

representative

in

your

area.

This

will assure

you

the fastest possible

seniee

.

Please

Include

the

instrument

Type

Number

or

Part

Number

and

Serial

Number

with

all

requests

lor

part.

or

service.

Specifications

and

price

c.hange

privileges

reserved.

Copyright

~

1974

by

Tektronix

,

Inc

.,

Beaverton

,

Oregon

.

Printed

in

the

United

Slates

of

America

.

All

rights

reserved.

Contents

of

this

publication

may

not

be

reproduced

in

any

form

without

permission

01

Tektronix

,

Inc.

U.S.A.

and

foreign

TEKTRONIX

products

covered

by

U.S.and

foreign

patents

and/

or

patents

pending

.

TEKTRONIX

is a

registered

trademark

of

Tektronix

,

Inc

.

7012

Service

TABLE OF

CONTENTS

Page Page

T

ABLE

OF

CONTENTS

SECTION 3 MAINTENANCE

LIST

OF

ILLUSTRATIONS

ii PREVENTIVE

MAINTENANCE

3-1

LIST

OF

TABLES

iii

Introduction

3-1

Cleaning

3-1

SECTION 1 OPERATING

INFORMATION

Visual

Inspection

3-1

PRELIMINARY

INFORMATION

1-1

Recalibration

3-1

7012

Features

1-1

TROUBLESHOOTING

3-2

Display

Modes

1-2

Troubleshooting

Aids

3-2

7012

Installation

1-2

Troubleshooting

Equipment

3-2

Module

Installation

1-2

Troubleshooting

Procedure

3-2

CORRECTIVE

MAINTENANCE

3-4

SECTION 2 THEORY OF OPERATION General 3-4

Obtaining

Replacement

Parts 3-4

PRELIMINARY

INFORMATION

2-1

Soldering

Techniques

3-4

BLOCK

DIAGRAM

2-1

Component

Replacement

3-5

Block

Diagram

Description

2-1

Circuit

Board

Replacement

3-6

LOGIC

TRIGGERING

2-2

Switch

Replacement

3-7

4-1/2

DIGIT

A/D

CONVERTER

AND

LOGIC

2-3

SECTION

4 PERFORMANCE CHECK/CALIBRATION

READOUT

LOGIC

2-5

THE

TEKTRONIX

READOUT

PRELIMINARY

INFORMATION

4-1

SYSTEM 2-8

Calibration

Interval

4-1

INVERTER POWER SUPPLY 2-10

Tektronix

Field Service

4-1

DUAL-TRACE

VERTICAL

Using

This

Procedure

4-1

AMPLIFIER 2-11

Test

Equipment

Required

4-1

CIRCUIT

OPERATION

2-11 PART

1-PERFORMANCE

CHECK

4-5

~-

VERTICAL AMPLIFIER

0 2-12

Index

to Part

1-Performance

4-1/2

DIGIT

A/D

CONVERTER~

2-13

Check

4-5

LOGIC

<V

2-13

Preliminary

Procedure

for

POWER

AND

CONNECTORS

0 2-14

Performance

Check

4-5

7012

Service

TABLE OF

CONTENTS

(cont)

Page

SECTION 4 PERFORMANCE CHECK/CALIBRATION

(cont)

VERTICAL

DISPLAY

4-6

VOL

TAGE

READOUT

DISPLAY

AND

TRIGGERING

4-7

GATE

DISPLAY

4-8

PART

II-CALIBRATION

PROCEDURE

4-9

Index

to

Calibration

Procedure

4-9

Preliminary

Procedure

For

Calibration

4-9

FLOATING

POWER SUPPLY 4-10

VERTICAL

DISPLAY

4-12

BANDWIDTH

4-14

ANALOG

TO

DIGITAL

CONVERTER

4-16

SECTION 5 ELECTRICAL PARTS LIST

SECTION

6 DIAGRAMS AND

CIRCUIT

BOARD

ILLUSTRATIONS

SECTION

7 MECHANICAL PARTS LIST

CHANGE INFORMATION

LISTOF ILLUSTRATIONS

Figure Page Figure Page

Number Number

2-4B

Block

diagram

of

the

1-1

Frontispiece.

4-1/2

Digit

AID

Converter

(cont.)

2-7

1-2

7012

Front-panel

control

2-5

Block

diagram

of

the

and

connector

functions.

1-1

Readout

Logic

section.

2-9

1-3

Display

mode

switch

2-6

Block

diagram

of

the

location

and

functions.

1-2

Inverter

Power

Supply.

2-10

1-4

7012

and

module

installation.

1-2 2-7

Block

diagram

of

the

Dual-Trace

2-1

Block

diagram

of

module

and

Vertical

Amplifiersection.

2-11

7012

A/D

Converter.

2-1

4-1

7012

Calibration

Fixture

installed. 4-5

2-2

Block

diagram

of

the

Logic

4-2

Typical

Inverter

pulse

waveform

Triggering

section.

2-2

properly

neutralized.

4-11

2-3

Timing

diagram

of

the 4-3

Typical

time-slot

pulses

with

4-1/2

Digit

AID

Converter.

2-4

relation

to

the

readout

display

4-17

2-4A

Block

diagram

of

the

4-4

Typical

example

of

gate

4-1/2

Digit

A/D

Converter.

2-6

pulse

neutralization.

4-19

ii

®

LIST

OF

ILLUSTRATIONS

(cont.)

Figure

Number

6-1

Semiconductor

lead

configurations

Block

Diagram.

Figure

Number

6-5 (A3)

Triggering

switch

board

component

locations.

~

Logic.

7012

Service

6-2 (A1)

Mainboard

component

locations.

o Vertical

Amplifier.

6-6 (A2) Floating board

component

locations.

o

Power

and

Connectors.

6-3 A2) Floating board

component

locations. 6-7 (A1) Main

circuit

board

o 4-1/2

Digit

A/D

Converter.

adjustment

locations.

6-4 (A1)

Mainboard

component

locations. 6-8 (A2) Floating

circuit

board

adjustment

locations.

MECHANICAL

PARTS

LIST

ILLUSTRATIONS

Figure

Number

Exploded view.

2,3 Accessories and Repackaging.

4 Dimensions.

LIST

OF

TABLES

Table Page

Number

2-1

7012

Readout Format 2-8

2-2 U148

Input/Output

Table

for

CH 1 and CH 2

Display

Modes 2-12

3-1 Fuse Ratings 3-7

4-1

Test

Equipment

4-2

4-2 Vertical Display

Amplitude

and

Lower

Numerical

Readout 4-6

4-3 Floating Power

Supply

Limits

4-10

4-4 Vertical Display

Amplitude

and

Lower

Numerical

Readout 4-13

iii

WI

_

_.

•

-

--

M1

,,"'''''

UNCTION

..

OOU~(

M3

--

_.

•

m.

E~

IG::

-

•••

]470.1

Fig. 1-1. 7

012

A/ O

Converter

with

M1

Mult

i-

funct

ion MOdule

part

ia

lly Installed, M2

Sample

/Ho

ld

M

odule

,

and

M3 AMS Volts

Mo

dul

e.

7012

Service

Section

1-

7012

Service

OPERATING

INFORMATION

PRELIMINARY

INFORMATION

7012

FEATURES

The

7012

is an analog to

digital

converterfor use with

any 7000-series OSCilloscope mainframe that contains

readout. Several

plug-in

modules are available

for

use

with the 701

2.

Depending

upon

the

plug-in

module

used,

th

e

7012

can supply

up

to a 4-1 /2

digit

dis

play with a full

scale

re

a

ding

of

20000

on

the mainframe cr

t.

When

not

used,the mostsignif

icant

digit

of

the

display

issuppresed

.

Automat

ic

polarity

and

ove

rflow

indicato

rs are also

contained in the 7012. The AID Converter can be

triggered internally by the

plug-in

module

, manually

by

a

fronl

-panel switch,

or

externally from a

trigger

source

s

uch

as

the

7015

Period

Timer

.The

7012

also

containsa

ve

rtical display amplifier that displays the signal applied

to the module, and a gate dis

play

amplifier

that displays a

representation of the

7012

internal gate signal.

Since the

7012

function

is

dictated

by

the

module

installed, Instructions

for

operating the

7012

are located

in the Operating

Instructions

for each

module

(i.e.,

Ml,

M2

or M3). A

brief

description

of

the

7012

Front-Panel

Co

nt

rols and

Connectors

is

shown

in Fig. 1-2.

T

RIG

' O I

ndica

t

or

VER

TI CAL D

ISPLAY

POS

ITION

ContrOl

Positions

'he

SIgnal

displav

verti-

cally

on

the

cr

t

.......

en

u$ed in

the

vertical

plug-in

com

p

artment

of

VERTICAL DISPLAY

ATTEH--@-

~

A

TTENUA

TOR

Switch

S,gMI a

mpl

i

tude,

th

e first signifI

cant

readOut

l--

. '

GATE

POS

ITI

ON

Control

dilijllay vert

;-

GATE

ON

-

OFF

PUYlbutto

n

the

dig

ital

gale

to

be

dis-

on

the

mainframe

crt

in

l

ocked

in

position

(see Iijleci-

1-""::"'"

-n.=

m

od

ule

instr

ucti

o

ns

7D12

.,.

CONVERTER

Fig

. 1

-2_

7012

Fr

o

nl

-

pan

e l c

onlrol

a

nd

c

onn

ec

1or

fun

clio n

s.

AUTO

Mode

Pu$hbutlon

Co

nnecl5

in

te

rnal trigg

ering

signal.

Automatic

recycl

ing

is

nominally

to

4

measuremenu

per

J;OCond

.

EXT

Mode

Pus

hb

utton

Accepts

triggering signal

con

nec-

ted

10

the

EXT

IN

connector

or

I

operation.

EX T IN

Connector

a

mea

ns

connecting

an

external

tr

igger signal

to

the

trigger

am

plifier ......

ile

in

the

EXT

mode.

MAN

Mode

Pushbutton

ma

nu

al

triggering

by

MAN OOtlon.

)

470.

2

1-1

Op

e

rating

Intormatlon

-7D12 Service

DISPLAY MODES

The

vertical displayand the

in

ternalgate disp

la

ycan be

operated in either alternate or

cho

p mode. depending

up

on the internal Display Modeswitch setting; see Fig.

1-

3.

DISPLAY

MO

DE

SW

ITCH

1470-3

Fig. 1-3. O

l'p

l.

y m

od

e .wllcn L

oce

Uon end function

•.

All

ernate Mode

The

An

position

(toward fr

ont

panel) of Ihe Display

Mode

switc

h

pr

oduc

es

a display th

at

alternates between

the vertic

al

display and the gate display with each sweep

on the crt.

Although

the

Alt

modecan be used

atall

sweep

rates, the Chop modeprovidesamore satisfactor

ydisplay

at

sweep ratesbelowabOut 0.2millisecond perdivis

io

n.

At

slow sweep rates. alternate mo

de

swit

ching

becomes

visually perceptible.

Cho

p Mode

The

Chop

position (toward rear) of the Display Mode

switch produces a display th

at

is electro

ni

ca

lly

switched

between the

in

put

display

and the trigger gale display

at

app

roxima

tely a 500 kilohertz rate (controlled

by

main-

frame). In general. the

Chop

mode provides the best

display at sweep rates slow

er

than about 0.2 millisecond

per division.

701

2

INSTALLATION

' -2

r

~~~;;;;

~~

"'

''

.'

''J'';;

.,

,..~

Extreme

car

e

should

be

exercised when handling

t

he

7012

to prevent

touching

any

part

of

the

circuit

boards.

ThiS

unit con

ta

ins

s

e~era

l

hi

gh

impedance

circuits

w

hich

can

de~e/op

Imer-I

ea

kage if

con·

laminated

by

body salts

or

acids. Refer to the

Ma

in

te

nance

Section

of

th

is

manua

l for

recom

mended cleani

ng

methods

and

sol~ents.

The

70

12 is calibrated and ready

for

use with a

module

as

re

ceived. It can be installed

In

any compartment

of

Tektronix 7000-series oscilloscopes, but is i

nt

ended prin-

cipally for use in vertical ptug-incompartments.

To

install,

align the upper

an

d l

ower

rails

of

the

7012

with the

oscilloscope tracks and fully insert it.

The

fro

nt

is flush

with the front of the oscilloscope when the

7012

is fully

inserted, and the latch at the botto

m-

left

corner

of

the

7012

will

be

in place against the

fr

ont panel. See Fig. 1-4.

Set the oscilloscope

for

a

ve

rtical mode to correspond

with the vertical compa

rt

mentused when an analog signal

is to be displayed. The digital reado

ut

will

be disp

la

yed

regardless

of

the vertical mode selected.

To remove the

7012

, pull on the latch (which is

inscribed with the

unit

identification

"7

012

") and the

7012

will unlatch, Continue

pulling

on the latch to slide

the

7012

out of the oscillos

cop

e.

MODULE INSTALLATION

All modules are calibrated and ready

for

use with the

70

12

as

received. To install. align the

upper

and lower

rails

of

the module

with

the

7012

module-compartment

tracks and fully

in

sert it. The fro

nt

is flush

with

thefront

of

the 7012 when the

modul

e

Is

fully inserted. l ock the

module

securely In posit

ion

by rotating the retai

ni

ng knob

clockwise

until

it is

linger-light.

See Fig. 1-4. To remove

the

module

, reverse the above procedure.

7012

LATCH

; .

-

.

Fig. 1

-4

.

701

2e

nd

mod

ule In

lt.

llallon.

1470'"

®

Section

2-7012

Service

THEORY

OF

OPERATION

PRELIMINARY

INFORMATION

INTRODUCTION

This

section

of

the manual describes the

circuitry

used

in the 7D12

AID

Converter.

The

description

begins

with

a

discussion

of

the instrument, using the basic

block

diagram shown in Fig. 2-1. Next, each

major

circuit

is

described in detail, using detailed

block

diagramsto

show

the relationship between stages in each

major

circuit.

Detailed schematics

of

each

circuit

are located in the

Diagrams Section atthe back

of

this manual; referto these

schematics

throughout

the

following

circuit

description

for

specific

electrical values and relationships.

MODULE

r--

--I

AID

CONVERT

I I

COMMAND

I

INPUT

I 1

I

I I

ANALOG

DC

VOLTAGE

SIGNAL

I PROCESSING I

I

SECTION

I I

I

BLOCK DIAGRAM

BLOCK DIAGRAM DESCRIPTION

The function

of

each·block in the basic

block

diagram,

Fig. 2-1, is readily apparent except

for

the InverterPower

Supply.

This

supply

permits

floating the

AID

Converter

section, enabling measurements with the inputs elevated

as

high

as

1kV. Further,

not

all modules utilizethe Display

and Gate

amplifier

circuits

shown. Each

block

represents

a

major

circuit

within the instrument. The numbered

diamond

in each

block

refers

to

the

circuit

diagram,

(located at the back

of

this manual)

which

covers that

specific part

of

the instrument.

7012

AID

CONVERTER

F·

···

---.

.

---.

--~

I.

. r

·1

LOGIC

I

TRIGGERING

1

I I

[ 0 I

I l

I I

4%

DIGIT

AID

READOUT

I

VHI

CONVERTER

LOGIC

TO

l-

:

VLO

~ ~

~ 1

OSCI LLOSCOPE

CHARACTER

GENERATOR

I

I 1

I I

I I I

I

INVERTER

: POWER SUPPLY I POWER

SUPPLY

I I

I I I I

DISPLAY

1 0

I

AMPLIFIER

.1

I

I I

I I I I

I

SIGNAL

I

DUAL

TRACE

I

I I

VERTICAL

GATE

AMPLIFIE

R

I

AMPLIFIER

I I I

I I

GATE

<9

I

I I I

I

I I

I I I

I

SCALE

FACTOR,

I I I

MEASUREMENT

UNIT,

1

DECIMAL

POINT,

, I

1

LAST

DIGIT

I I

SUPPRESSION I

~--

---~

L~

__

..

___

....

_'----'--""'

Fig. 2-1.

Block

diagram

of

module

and

7012

AID

Converter.

®

SIGNAL

TO

OSCILLOSCOPE

VERTICAL

1470-5

2-'

Theory

of

Operation-7D12

Service

The

7012

AID

Converter

plug-in

unit

contains

afast, 4-

1/2

digit

analog-to-digital

converter, Inverter Power

Supply, Dual-Trace Vertical Amplifier, Readout

Logic

and

Trigger

Logic

circuit. The modules process various

analog signals, such

as

peak voltage, rms voltage,

resistance, temperature, etc. and

produce

a dc voltage

which

the

7012

converts

to

digital

readout

information

for

the 7000-series oscilloscope.

The

modules also provide

an

analog signal

for

display

on the crt.

LOGIC

TRIGGERING

INTRODUCTION

The

block

diagram

for

the

Logic

Triggering

circuitry

is

shown in Fig. 2-2. The

trigger

signal is connected

internally from the

7012

AID

Converter to the module.

The

M1

and M3 modules return the

trigger

signal

directly

to the

7012

AID

Converteras an

AID

Convert Command.

The M2 module, however, holds the triggersignal

until

the

M2 sampling process is

complete

before releasing an

AID

Convert Command.

TRIGGERING SWITCH

Auto

Mode

Free-Run

Oscillator

0610

is connected as the

trigger

source. The

oscillator

hasa

nominal

output

frequency

of4

hertz.

External

Mode

The

Free-Run

Oscillator

and

+5

volt sources are

disconnected. External

trigger

signals connected to the

7012

EXT IN

connector

are used

directly

as

the

trigger

source.

MODULE

7012

AID

CONVERTER

MAINFRAME

r---

I

M1

AND

M3

DIRECT

INTERNAL

CONNECTION

I

L

__

A/D

CONVERT

b7

COMMAND

AID

BUSY

a6

~

LOGIC

2-2

j

"

I

/

"'

FREE-RUN

OSCILLATOR

0410

I

+5 V

b

SINGLE

SWEEP

RESET

INVERTER

0404,

U402C

1""------""1

: I

~

: (

SPRING\

RETURN)

IAUTOI

~

IEXTI

~

IMANI

~

....

:S4:2~4~~~~~~L

____

~J

ITRIGGERINGI

60

ms

MUL

TIVIBRATOR

U440A,0434

U436A

t ,

AID

BUSY

TO

2 ms

MONOSTABLE

MULTI,

U440B

TRIG'D

CR438

Fig. 2-2.

Block

diagram

of

the

Logic

Triggering

section.

SINGLE

B15

SWEEP

RESET

I

"-

,

A22

AID

BUSY

1470-6

®

Manual Mode

The Free-Run

Oscillator

is disconnected and the EXT

switch is closed,

shunting

R422. Manual operation

provides a

+5

volt

pulse as the

trigger

signal.

TRIGGER HOLDOFF

The

trigger

signalbecomes the

AID

Convert

Command

either

directly

or

indirectly,

depending

upon

the

module

used.

The

AID

Convert

Command

switches the state

of

the 60 mS Multivibrator.

The

multivibrator

rejects all

additional

AID

Convert

Command

signals

during

the 60

millisecond period.

The

TRIG'D

indicator, CR438, is

energized

during

the 60

millisecond

period to indicatethe

measurement

circuits

are busy.

4-1/2

DIGIT

AID

CONVERTER

AND

LOGIC

INTRODUCTION

A

block

diagram

of

the

4-1/2

Digit

AID

Converter and

Logic

functions

is shown in Fig. 2-4. Refer

to

the

timing

diagram in Fig. 2-3 and the

block

diagram in Fig. 2-4

throughout

the

following

discussion. All

of

the switches

shown in Fig. 2-4 are

electronic

switches such as

MOS-

FETs, JFET's and diodes.

The

circuitry

enclosed by the

dotted

lines is a floating section powered

by

the Inverter

Power Supply. Positive

logic

is assumed

to

set and reset

all

circuit

shown in the

block

diagram.

BEFORE TIME ZERO

The

following

conditions

exist before a

trigger

signal

(AID

Busy)

is

received at the 2 mS

Monostable

MV

(Multivibrator) U440B.

1.

The analog

output

of

the

module

is

coupled

to the4-

1/2

Digit

AID

Converter Vh; and V

lo

electronic

input

switches.

2.

Sw

1 is open and

Sw

2 is closed,

disconnecting

Vh,

and

connecting

V

lo

to

the

input

of

the

Buffer

and

IGml

Converter stages.

3.

Sw3 is closed,

connecting

the

Auto-Zeroing

Circuit

to the

IGml

Converter.

The

Auto-Zeroing

Circuit

automatically produces

the

same voltage level at

Input

2

as

that

of

the offset voltage appearing at

Input

1,

thereby

®

Theory of

Operation-7D12

Service

holding

the I

Gml

Converter

output

at zero volts.

Capacitor

C302 stores the offset voltage required to hold the

IGml

Converter

output

at zero volts

during

integration.

4.

Sw

6 is closed, setting the

Integrator

output

to zero

volts.

AT

TIME

ZERO (to)

A negative-going

trigger

pulse

(AID

Busy) Sets the 2

ms Monostable MV U440B. The 0

output

of

the MV holds

the

Clock

Sync

ff

(flip-flop)

Master Reset and the

Measurement Period ff, Set on

for

2 milliseconds.

The

0

output

pulse from the

Clock

Sync

ff

performs the

follow-

ing functions:

1.

Sets the

AID

Standby

ff

changing

the electronic

switch stages

as

follows:

a.

Sw

1 closes and

Sw

2 opens,

disconnecting

V

lo

and

connecting

Vh;

to

the

input

of

the

Buffer

and

IGml

Converter stages.

b.

Sw 3 opens,

disconnecting

the

Auto-Zeroing

Circuit

from

the

IGml

Converter

output.

The charge

on

capacitor

C302 maintains the offset voltage

balance between

Input

1and

Input

2;

therefore, the

IGml

Converter

output

remains referenced at zero

volts.

c.

Sw

6 opens,

arming

the Integrator circuit.

2.

Sets the Measurement Period ff.

3.

The

1

output

from the 2 ms Monostable MV U440B,

Resets the 4 Decade Counter-Latches in U500, thereby

clearing any stored

information

from the previous

measurement.

The 2 millisecond delay between

to

and tl allows all

switching

circuits

and the

IGml

Converter to stabilize

before starting the measurement.

AT

TIME

ONE

(tl)

The 2 ms Monostable MV, U440B, returnsto itsoriginal

state, thereby releasing the Clock Sync

ff

Master Reset.

The first negative-going pulse from the 1 mHz

Clock

Generator, U402, Sets the

Clock

Sync ff. The 0

output

from the

Clock

Sync

ff

enables AND gate U436C and

U492C, allowing the

clock

signal

to

pass and begin

counting

at the Counters.

The

0

output

from the

Clock

2-3

Theory of

Operation-7D12

Service

TIME

TRIGGER

PULSE

2 ms

MULTI

U440B

ON

CLOCK

SYNC

FF 1

OUTPUT

1

MHz

CLOCK

AID

STANDBY

PULSE

SW

1

CLOSED

SW

2,

SW

3 OPEN 1

START

RAMP

PULSE

SW4

CLOSED

1

to

tl

1-2m

s-l.

20

ms

1111111111111111111111111111111111111111111111111111111111111

I

,

:

IREF

I

OUTPUT

OF

INTEGRATOR

I : x

~,------

:

....

0------

20,000

COUNTS

----

....

'-COUNTS--'

2-4

SW

5

CLOSED

1

SW

6 OPEN1

20

K

COUNT

PULSE

STOP

COUNT

PULSE

1

The

switch

states

mentioned

occur

at

the

positive-going

transition.

Fig. 2-3.

Timing

diagram

of

the

4112

Digit

AID

Converter.

1470-7

®

Sync

ff

also enables

the

Start

Ramp

ff,

closing

Sw

4.

The

rectified

input

current

(Ln)

from

the

IGml

Converter

begins

to

charge

capacitor

C379 in

the

Intergrator.

The

0

output

from

the

Clock

Sync

ff

Sets

the

AID

Converting

Pulse

Generator

ff, U436B

and

D,

thereby

allowing

the

1

output

to

go

hi

at

tl.

AT

TIME

TWO

(1

2)

The

4

decade

Counter-Latches

and

+ 4

ff

have

counted

20,000

clock

pulses.

At

the

20K

count,

the

+4

ffgenerates

a

negative-going

pulseto

the

20K

Count

Logic

circuit.

The

output

of

the 20K

Count

Logic

changes

the

electronic

switch

states as

follows:

1.

Resets

the

Start

Ramp

ff

that

switches:

a.

Sw

4 open,

disconnecting

the

IGml

Converter

output

from

the

Integrator.

2.

Sets

Stop

Count

ff

that

switches:

a.

Sw

5 is closed,

connecting

the

Reference

Current

Generator

output

to

the

Integrator.

3.

Resets

the

AID

Standby

ff

that

switches:

a.

Sw

1

is

open

and

Sw

2 is closed,

disconnecting

the

input

Signal

to

the

Buffer

and

I

Gml

Converter

stages.

b.

Sw

3 is closed,

connecting

the

Auto-Zeroing

Circuit

to

the

IGml

Converter.

4. Resets the

AID

Converting

Pulse

Generator

ff,

U436B and

D.

The

1

output

goes

hi

at

tl

and

10

at

t2.

The

AID

Converting

Pulse is

connected

to

the

module

gate

circuitry,

allowing

the

measured

gating

time

(tl-t2)

to

be

observed

on

the

crt

display.

®

Theory of

Operation-7D12

Service

The

Reference

Current

Generator

output

current

(Irer)

begins

discharging

C379, and

the

4 Decade

Counters-

Latches are cleared

to

measure C379

discharge

time.

AT

TIME

THREE

(t

3)

The

output

of

the

Integrator

(C379) is

discharged

to

zero

volts

and

the

Comparator

output

Resets

the

Stop

Count

ff.

The

0

output

of

the

Stop

Count

ff

changes

the

electronic

switch

states as

follows:

1.

Sw

5 opens,

disconnecting

the

Reference

Current

Generator.

2. Sets

the

Integrator

Zeroing

Logic

circuit,

closing

Sw

6.

Sw

6

holds

the

Integrator

output

level

at

zero

volts.

3.

Resets

the

Measurement

Period ff.

AND

gates

U436C and U492C are

disabled,

preventing

the

1

MHz

clock

pulse

from

reaching

the

counters.

AND

gate

U492D

is enabled,

transferring

the

stored

information

in

the

4

Decade

Counters

and + 4

ff

to

the Latches.

The

output

of

the

Latches is

connected

to

the

Readout

Control

Section

in the

mainframe.

A 60

millisecond

monostable

multivibrator

in

the

Trigger

Logic

circuit

prevents

another

trigger

from

oc-

curing

until

one

measurement

cycle

has been

completed.

READOUT LOGIC

INTRODUCTION

The

Readout

Logic

circuit

encodes

the

Indicator

Oscilloscope

readout

system

to

display

the

measurement

made

by

the 7D12

and

module.

The

Readout

Logic

circuit

also

encodes

the

readout

system

to

display

the

ap-

propriate

measurement

units

and

polarity

symbols,

along

with

positioning

the

display

decimal

point

and

indicating

an

over-range

measurement.

A

discussion

entitled

the

Tektronix

Readout

System

following

the 7D12

Theory

of

Operation

gives a

brief

description

of

the readout system used in

Tektronix

7000-

series

Oscilloscopes.

2-5

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U356,

Q363

R361,

VR354

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6

55

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CR365

CR338

>-1"

INPUT

PROTECTION

Q224

Q228

CR226

Q233

51

....,...

-

f-o

:

..,0-

.........

-.--.1

BUFFER

Q242,

Q244

R249,

Q250

Q246,

Q252

Q254,

U248A,B

I'::..

INPUT

1

r-

CR339

C379

54

Jl

.,....

liN

1\

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Q237

52

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U260,

Q262

INTEGRATOR

COUNT

CONVERTER

.......,-V"~

V

STOP

U276,

Q267

Q367.

Q369

~

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Q270.

Q278

.?

-.....r

Q275,

U283

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g~~~:

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VOLTAGE

STORAGE

CAPACITOR

C302

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U301,

Q290

Q296,

Q298

1

START

RAMP

FF

T348

Q344

Q342A.B

Q336

56

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1

INTEGRATOR

ZEROING

LOGIC

U317B

Q332

S

...r 0

r----

l

..

___

---II

I

Q313.

Q306

Q332.

U317A

5 R

20

K

COUNT

(5

R!

~

C5iJNT

~~R

S.~

____

~

____

~

______

~

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--.

L

___________

.

_______

.

__________

.

_____________

_

4,*OlCt"t

09"

tift,

2\~

I

J

START

RAMP

AID

STANDBY

20K

COUNT

STOP

COUNT

....

:s-

CD

o

-<

o

-

·

..

1

MHz

CLOCK

1

MHz

START

RAMP

AID

STANDBY

GENERATO

R

~e--------+---t----t--it---~

U402

-;-48

U456A,8

U458

Y449

U440

B

MASTER

RESET

CLOCK-

SYNC

FF

U476B,

C

U402B

CLOCK

GATE

U436C

U492C

RESET

COUNTERS

CLOCK

WAVE

SHAPING

MONOSTABLE

MV

U495

TRANSFER

LOGIC

U492D

20.8

kHz

TO

INVERTER

POWER

SUPPLY

4

DECADE

COUNTERS

LATCHES

U500

Q507

TRANSFER

Q480

S

MEASUREMENT

PERIOD

FF

R

U476A,

D o

HOLD

FROM

OSCILLOSCOPE

READOUT

SECTION

(NOT

USED

-

HELD

LO)

CARRY

20

K

COUNT

-;-4

FF

Q507

U509A,8

RESET

TO

OSCI

LLOSCOPE

LATCHES

t-~t--

~6~~:?gl

U514A,8

SECTION

~

20

ms

AID

t-.......,.

.........

C~~~~:i6NG

MODULE

-t

~

CD

o

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o

-

o

"

CD

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m

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:::::I

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c

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II.)

tn

CD

1470-168

~.

L-

__________________________________________________________________________________________________________

________

~n

CD

Theory of

Operation-7D12

Service

ENCODING

FORMAT

The

7D12 Readout

Logic

circuit

encodes

the

Rowand

Column

output

lines (pins 837-A37 respectively

of

the

oscilloscope Interface

Connector

for

channel

1,

and pins

A38-B38

for

channel

2)

according

to the

format

given in

Table 2-1. The

time-slot

puIses from the

oscilloscope

readout system are provided to the Readout

Logic

circuit

through

the Interface

Connector.

Several

of

the

time-slot

pulses are also connected

to

address·

the

Multiplexers.

TABLE

2-1

7D12 READOUT FORMAT

Time-Slot

Function Programmed

Number By

TS-1 Determines decimal position

Module

TS-2 Indicates

polarity

(+

7D12 (Disabled

or

-symbol)

of

by Module)

measurement.

Encodes a >

symbol

to 7D12

indicate over-ranging.

TS-3 Encodes 1

or

2,

and blanking 7D12

of

the most

significant

digit

of

measurement readout.

TS-4, TS-S Remaining

four

digits

of

7D12

TS-6, TS-7 measurement readout.

TS-7 also encodes blanking Module

of

the least

significant

digit

of

the measurement

readout.

TS-8 Symbols

Module

TS-9 Symbols

Module

TS-10 Symbols Module

DIGIT

AL-TO-ANALOG CONVERTER

Referto

the Readout

Logic

block

diagram shown in Fig.

2-S

throughout

the

following

discussion.

The

Digital-to-Analog

Converter

circuit

includes D-A

Converters

USOO,

OS40, OS32 and

OSS2.

2-8

Time-slot

pulses TS-4, TS-S and TS-6 from the

main-

frame are connected to

USOO

to

drive the

Output

Enable

inputs

of

the D-A Converters.

Time

slot

pulse TS-3 from

the mainframe is connected to the emitters

of

D-A

Converters OS40, OS32, and

OSS2

to provide

Output

Enable information

of

the

most

significant

digit.

Time-slot

pulse, TS-7, encodes Least

Significant

Digit

Blanking,

depending

upon

the module.

POLARITY AND OVER-RANGE

INDICATOR

The Polarity Enable

information

to

OS24 is determined

by the module.

Time-slot

pulse TS-2 is

coupled

to OS24

(via

switching

in the module)

to

provide

the

Polarity

Enable pulse. If the

input

to the base

of

OS24 goes

to

a

10

level,

current

is added

to

the

Column

Current

output

during

TS-2.

This

added

current

in TS-2 results in

the

+

symbol being changed to

-.

TS-2 also enables

the

Over-

Range Indicator. When the

output

of

US14A goes to a

10

level,

current

is added tothe

Column

Current

in TS-2.

This

added

current

in TS-2 changes

either

polarity

symbol

to

a

>

symbol

display.

SCALE FACTOR DISABLE

The

VERTICAL DISPLAY ATTEN switch encodes the

module

readout system

by

switching

resistors between

TS-4 and the

module

Column

output

line.

The

Scale

Factor Disable

current

mixes with theappropriate

module

time-slot

inputs to

supply

current

to the

Column

output

line.

The

readout system then displays the measurement

unit

in channel 2

for

the

combination

(7D12 ATTEN switch

and

module

attenuator

switch) measurement setting

selected.

THE

TEKTRONIX

READOUT SYSTEM

INTRODUCTION

The

following

discussion is provided to

acquaint

the

7D12 user with the Readout System used in

Tektronix

7000-series Oscilloscopes.

Since

the oscilloscope

Readout System provides

the

digital

readout

for

the7D12,

it

is necessary

to

relate the

function

of

the 7D12 to the

Readout System to gain a better understanding

of

the

7D12 operation. A detailed

circuit

description

of

the7000-

series Readout System is given in the

oscilloscope

instruction

manual.

THE READOUT SYSTEM

The

Readout System in the 7000-series oscilloscopes

provides

alpha-numeric

display

of

information

encoded

®

Theory of Operation--7D12 Service

.:Iioo

Rl15

Rl16

SCALE

FACTOR

D'SABLE

(I,

2,

or

5

,CH

2

ONL

V)

b~

~---------------------4--------~Ar--~

CH 2 ROW

R1l4

CH 2 ROW

b13

.----=---'--=...c-'-----------------t------------------_

bI2

.•

~~C~H~2~C~O~L~U~M~N~--------------------------_r-----------------------C--H_2

__

C_O

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L_U_M_N

__

~

bl~

.~C~H~I~R~O~W~

______________________________

+_--------------------_.-----C-H--l-R-O--W

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•

CH

1 COLUMN

CH

1 COLUMN

bI4.~~~~~~~~--------------------------_r------------------~_1r_------------~

b9

._L_E_A

__

S_T_S_'_G_N_'_F_'_C_A_N_T

__

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__

N_K_'_N_G

________

+_~.-~

R557

a144··~T-S--7------------------------------------+_------+_----------r-_+--------------~

TS

7

'i,

:.

TS

6

a

1~

",.

r----------------------------------------+--------+_.---------+--+_-------------

...

TS

6

bI6:·~

__

~T~S~5~----------------------------------~------~+_._------+_~--------------~

TS 5

TS 4

a17:

....

----------------------------------------

....

------~+_+_._----+_~--------------_

TS 4

TS 3

..

1330

A31

.831

.1'-32

·B32

a18

_-T~S~3--------------------------------------------+_+_+_+_----~~-----------'-~~_.

a19

TS

2

TS

2

:',/","

···.·1\33

a20

......

___'_T-=S...:I~

__________________________________________

++_+_+_----+_+_+---------'--=...:=--

......

TS 1

:.833

b18

COLUMN

CURRENT

REFERENCE

~r_~r_~~~~~r-~~_r+--++__I

GENERATOR

~

R499

20

K

_--_----J

.....

___

-1

DTOA

CONVERTER

OVER

RANGE

COUNT

TRANSFER

Q547

OUTPUT

...

__

-+-

______

--'

PULSE

ENABLE

~--l---====;S~~!:~::::~-,~~~~~;::::;--~r_----~H~O~L~D~(~N~O~T~U~S~E~D~)~

822

Fig. 2-5. Block diagram of the Readout Logic section.

1470-15

2-9

ArtekMedia

Digitally signed by ArtekMedia

DN: cn=ArtekMedia, o=ArtekMedia.com, ou, [email protected], c=US

Date: 2008.11.30 10:36:16 -06'00'

Theory

of

Operation-7D12

Service

by the

plug-in

units.

This

display is presented on the crt,

and is written by the

crt

beam on a time-shared basis with

the analog waveform display.

The Readout System

produces

a pulse train consisting

of

10

negative-going puIses called

time-slot

puIses.These

pulses are assigned

time-slot

numbers

corresponding

to

their

relative

position

in the pulse train. Each time-slot

pulse is directed to one

of

ten

output

lines, labeled TS-1

through TS-10 (time-slots one

through

ten) and are

connected to the vertical and horizontal

plug-in

com-

partments.

Two

output

lines, row and

column,

are

con-

nected from each channel (two channels per

plug-in

compartment) back to the Readout System.

Data is encoded

on

these

output

lines either by

connecting

resistors between them and the

time-slot

input

lines

or

by generating equivalent currents.

The

resultant

output

is a sequence

of

analog

current

levels on

the row and

column

output

lines.

The

row and

column

current

levels are decoded by the Readout System to

address a character matrix

during

each

time-slot

pulse,

thus selecting a character to be displayed

or

a special

instruction

to be followed.

J100

TO

PLUG-IN

__

--

MODULE

GUARD

a2

+15V(F)

b3

-15

v

(F)

a4

+5

v

(F)

a3

GND

(F)

b2

"

,

"

,

>-

>---C>

I

+15

V

REGULATOR

U618,0622

0620,0626

h

-15

V f.l

REGULATOR

0639

U643

0646

~

+5V

-

REGULATOR

U669

0661

0664

~

POWER

&

CO

NNECTORS

L--.

INVERTER POWER SUPPLY

INVERTER

The

block

diagram

of

the Inverter Power

Supply

is

shown in Fig. 2-6.

The

Inverteris driven with

divided-down

sync pulses from the 1 MHz

Clock

Generator.

The

sync

pulses switch

-15

volts alternately

through

the

transformer

primary

to the

+15

volt

supply

at

the center

tap.

The

Inverter side

of

the

transformer

is referenced to

chassis potential.

FLOATING REGULATORS

The

+15

and

-15

volt

regulator

voltages are based

upon the

+5

volt Reference voltage.

The

secondary

of

the

transformer and associated

circuitry

are referenced to

floating

ground.

Each floating regulator

circuit

is

equipped with

short-circuit

protection.

The

floating

power

supply

furnishes all the

power

for

the floating

portion

of

the instrument.

7D12

AID

CONVERTER

T595

f-----,

+15

V

~

...

RECTIFIER

~

CR606

~

CR607

CR608

CR609

-15

V

RECTIFIER

I----

L..............

+5V

RECTIFIER

~

CR655

CR656

f--'

+5V

REFERENCE

R613

VR613

INVERTER

0590

0593

C593

0600

0603

}

SYNC

PULSES

FROM

CLOCK

GENERATOR

+15

V

-15V

1470-8

Fig. 2-6.

Block

diagram

of

the

Inverter

Power

Supply.

2-10 ®

DUAL-TRACE

VERTICAL

AMPLIFIER

GATE AND SIGNAL DISPLAYS

The

block

diagram

for

the

amplifier

is

shown

in Fig. 2-7.

The Gate Display signal

is

fed

directly

to CH 1

of

the

Channel Switch. The

Signal

Display

information

passes

through an

Attentuator

to CH 2

of

the Channel

Switch.

Chop

or

alternate drive pulses (selected

by

the internal

Mode switch) to the Channel

Switch

is supplied

by

the

mainframe. The switched Gate and Signal Display

infor-

mation pass

through

the Signal

Amplifier

to the

main-

frame to the displayed on the crt.

TRIGGER PICKOFF

The attentuated Signal Display

information

passes

through

a

Trigger

Amplifier

to the mainframeand triggers

the time base.

CIRCUIT

OPERATION

INTRODUCTION

This section provides a detailed

description

of

the

electrical operation and relationship

of

the

circuits

in the

7D12.

The

theory

of

operation

for

circuits

unique

to this

instrument

is described in detail in this discussion.

Theory of

Operation-7D12

Service

Circuits

commonly

used in the

electronics

industry

are

not

described in detail.

If

more

information

is desired on

these

commonly

used circuits, refer to the

following

textbooks.

Jacob

Millman and Herbert Taub, "Pulse, Digital, and

Switching

Waveforms",

McGraw-Hili,

New York, 1965.

Robert

C.

Baron and

Albert

T. Piccirilli,

"Digital

Logic

and

Computer

Operations",

McGraw-Hili,

New York,

1966.

Thomas

C.

Bartee,

"Digital

Computer

Fundamentals",

McGraw-Hili,

1962.

Yaohan Chum,

"Digital

Computer

Design Fundamen-

tals,

"McGraw-Hili,

1962.

Neil A Robin,

"Analog-To-Pulse-Width

Converter

Yields

0.1

%

Accuracy",

EDN Journal, Vol. 15, Issue

21,

November

1,1970,

page 42.

MODULE

7012

AID

CONVERTER

MAINFRAME

(GATE)

SIGNAL

IpOSITIONI

JH1

AMPLIFIER

A11

}

SIGNAL

J100

R120

Q190,

Q200

B11

OUT

+

R195,C198

GATE

DISPLAY

b10

CHANNEL

(DISPLAY)

(VERT

DISPLAY)

SWITCH

MODE

IpOSITIONI

S142

R131 U148

ON

CHOP

CH 2

ALT

ATTENUATORS

OFF

SIGNAL

X1

-

C102

A2

UTILITY

DISPLAY

b20

X2

-

C106

+

COMMON

I

X5-C110

PLUG-IN

S110

B35

MODE

I

DISPLAY

CHOP CHOP

MODE

A5

DRIVE

OFFSET

AMPLIFIER

ON

OALT

GENERATOR

ALTERNATE

R138

Q144

~

DRIVE

OFF

I

A13

}

TRIGGER

I

TRIGGER

AMPLIFIER

I

OUT

I

Q170,

Q177 I B13

R169

~

0

VERTICAL

AMPLIFIER

IGATE/S165

1470-9

Fig. 2-7. Block diagram

of

the Dual-Trace Vertical Amplifier

section.

® 2-11

Tektronix 7D12 Operating instructions

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