Tektronix 7D12 User manual

TEKTRONIX
7o7z
A/D
CONVERTER
SERVICE
INSTRUCTION
MANUAL
Tektronix,
Inc .
P.O . Box
500
Beaverton,
Oregon
97005

Serial
Number
070-1470-00

First Printing JUNE 1974

WARRANTY
All TEKTRONIX instruments are warranted againsr
defective materials and
workmanship for one year .
Any questions with respect to the warrantyshould
betaken up with yourTEKTRONIX Field Engineeror
representative .
All requests for repairs and replacement
parts
shouldbe directed to
the TEKTRONIX Field Office
or representative in your area . This will assure you
the fastest possible service . Please
include the
instrument Type Number or Part Number and Serial
Number with all requests for parts or service .
Specifications and price change privileges reserved .
Copyright

1974 - by
Tektronix,
Inc .,
Beaverton,
Oregon .
Printed in the United States of America . All
rights reserved . Contents of this publication may not
be reproduced in any form' without permission of
Tektronix, Inc .
U .S .A . and
foreign
TEKTRONIX products
covered
by U .S . and foreign patents and/or patents pending .
TEKTRONIX is a registered trademark of
Tektronix .
Inc
.

TABLE
OF
CONTENTS
71312 Service
TABLE OF CONTENTS
Page
i SECTION 3 MAINTENANCE
Page
LIST OF ILLUSTRATIONS
PREVENTIVE
MAINTENANCE 3-1
LIST
OFTABLES
Introduction
3-1
Cleaning
3-1
SECTION 1 OPERATING INFORMATION
Visual Inspection
3-1
PRELIMINARY INFORMATION 1-1
Recalibration
3-1
71312 Features
1-1
TROUBLESHOOTING
3-2
Display Modes
1-2
Troubleshooting Aids 3-2
71312 Installation 1-2
Troubleshooting Equipment
3-2
Module Installation
1-2
Troubleshooting
Procedure 3-2
CORRECTIVE
MAINTENANCE 3-4
SECTION 2 THEORY OF OPERATION
General
3-4
Obtaining
Replacement Parts 3-4
PRELIMINARY INFORMATION 2-1
Soldering Techniques 3-4
BLOCK DIAGRAM 2-1
Component Replacement
3-5
Block Diagram Description 2-1
Circuit Board Replacement 3-6
LOGIC TRIGGERING
2-2
Switch Replacement
3-7
4-1/2 DIGIT A/D CONVERTER
AND LOGIC
2-3
SECTION
4 PERFORMANCE CHECK/CALIBRATION
READOUT LOGIC 2-5
THE TEKTRONIX READOUT
PRELIMINARY
INFORMATION 4-1
SYSTEM
2-8
Calibration
Interval 4-1
INVERTER POWER SUPPLY 2-10
Tektronix Field Service
4-1
DUAL-TRACE VERTICAL
Using This Procedure
4-1
AMPLIFIER 2-11
Test Equipment Required
4-1
CIRCUIT OPERATION
2-11
PART 1-PERFORMANCE
CHECK 4-5
VERTICAL AMPLIFIER1O 2-12
Index to Part 1-Performance
4-1/2 DIGIT A/D CONVERTER< 2-13
Check
4-5
LOGIC
O
2-13
Preliminary Procedure for
POWER AND CONNECTORS 4O 2-14 Performance Check
4-5

71312 Service
Page
TABLE OF
CONTENTS (cont)
LIST OF
ILLUSTRATIONS
Figure
Page Figure
Page
Number Number
2-4B Block diagram of
the
1-1 Frontispiece
.
4-1/2 Digit A/D Converter (cont .) 2-7
1-2
71312 Front-panel control
2-5 Block diagram of the
and connector
functions . 1-1
Readout Logic section
. 2-9
1-3 Display
mode switch 2-6
Block diagram of
the
location and functions .
1-2
Inverter Power Supply . 2-10
1-4 71312 and module
installation .
1-2
2-7 Block diagram of the Dual-Trace
2-1 Block
diagram of module and
Vertical Amplifier section .
2-11
71312 A/D Converter .
2-1
4-1
71312 Calibration Fixture installed . 4-5
2-2
Block diagram
of the Logic 4-2
Typical Inverter pulse waveform
Triggering section .
2-2
properly neutralized .
4-11
2-3 Timing
diagram of the
4-3 Typical time-slot pulses with
4-1/2
Digit A/D
Converter . 2-4
relation to the readout display
4-17
2-4A
Block diagram of the
4-4 Typical example of
gate
4-1/2 Digit
A/D Converter . 2-6 pulse
neutralization . 4-19
SECTION 4 PERFORMANCE
CHECK/CALIBRATION SECTION 5 ELECTRICAL
PARTS LIST
(cont)
VERTICAL DISPLAY 4-6
VOLTAGE READOUT DISPLAY
AND TRIGGERING
4-7
GATE DISPLAY
4-8
SECTION 6 DIAGRAMS AND CIRCUIT
BOARD
PART
II-CALIBRATION
ILLUSTRATIONS
PROCEDURE
4-9
Index to Calibration
Procedure 4-9
Preliminary
ProcedureFor
Calibration
4-9
SECTION
7 MECHANICAL
PARTS LIST
FLOATING POWER SUPPLY
4-10
VERTICAL DISPLAY
4-12
BANDWIDTH
4-14
ANALOGTO
DIGITAL
CONVERTER
4-16 CHANGE INFORMATION

LIST OF ILLUSTRATIONS
(cont .)
MECHANICAL PARTS
LIST
ILLUSTRATIONS
Figure
Number
1

Exploded view .
2,3

Accessories
and Repackaging
.
4 Dimensions .
LIST
OF TABLES
Table

Page
Number
2-1

7D12 Readout Format

2-8
2-2

U148 Input/Output Table
for CH 1 and CH 2 Display Modes 2-12
3-1

Fuse Ratings

3-7
4-1

Test Equipment

4-2
4-2

Vertical Display Amplitude and
Lower Numerical
Readout

4-6
4-3

Floating Power Supply Limits

4-10
4-4

Vertical Display Amplitude
and Lower
Numerical Readout

4-13
7D12 Service
Figure
Number
Figure
Number
6-1 Semiconductor
lead configurations 6-5 (A3) Triggering
switch board
Component
locations
.
Block
Diagram .
O3 Logic .
6-2 (A1) Mainboard component locations .
O Vertical
6-6 (A2)
Floating board component locations .
Amplifier .
O Power and
Connectors .
6-3 A2) Floating board component
locations .
6-7 (A1)
Main circuit board
adjustment locations .
O2 4-1/2 Digit A/D Converter .
6-8 (A2)
Floating circuit board
6-4 (A1) Mainboard component
locations . adjustment
locations .

Fig . 1-1
. 7D12 A/D Converter
with M1 Multi-function Module
partially installed,
M2 Sample/Hold
Module, and M3 RMS
Volts
Module .
7D12 Service

A
PRELIMINARY
INFORMATION
7D12 FEATURES
The 7D12
is an analog to digital converter
for use with
any 7000-series
oscilloscope mainframe
that contains
readout . Several
plug-in modules are available
for use
with the 7D12 .
Depending upon the plug-in module
used,
the
7D12 can supply up
to a 4-1/2 digit display with a full
scale
reading of 20000 on the
mainframe crt . When not
used, the most
significant digit of the display
is suppresed .
Automatic polarity
and overflow indicators are also
VERTICAL DISPLAY POSITION
Control
Positions the signal
display verti-
cally on the crt when used in the
vertical plug-in compartment
the mainframe .
ATTENUATOR Switch
Controls
signal amplitude, and
sets the first
significant readout
figure .
GATE POSITION
Control
Positions
the gate display
verti-
cally
on the mainframe crt .
GATE ON-OFF Pushbutton
of
Allows the
digital gate to be dis-
played
on the mainframe crt in
the locked in
position (see speci-
fic module
operating instructions
for applications)
.
OPERATING
INFORMATION
Fig . 1-2 . 7113112 Front-panel
control and connector functions .
Section
1-7D12 Service
contained in the 7D12 .
The A/D Converter can
be
triggered
internally by the plug-in
module, manually by a
front-panel switch,
or externally from a trigger
source
such as the 7D15
Period Timer . The 7D12 also contains a
vertical display amplifier that
displays the signal applied
to the module,
and a gate display amplifier
that displays a
representation of the 7D12
internal gate signal .
Since the 7D12 function is dictated
by the module
installed,
instructions for operating the
7D12 are located
in the Operating
Instructions for each
module (i .e ., M1, M2
or M3) . A brief
description of the 7D12
Front-Panel
Controls and Connectors
is shown in Fig . 1-2 .
TRIG'D Indicator
Indicates the
period of time the
A/D converter
is busy .
AUTO Mode Pushbutton
Connects internal triggering
signal .
Automatic recycling
is nominally
set to 4 measurements per second
.
EXT Mode Pushbutton
Accepts triggering signal connec-
ted to the EXT IN connector or
manual operation .
EXT I N Connector
Provides
a means of connecting
an external trigger signal
to
the
trigger amplifier while in the EXT
mode .
MAN Mode Pushbutton
Allows manual triggering by push-
ing the MAN button .
1470-2

Operating
Information-7D12
Service
DISPLAY
MODES
The vertical display
and the internal gate display
can be
operated in
either alternate or chop
mode, depending
upon
the 'internal Display
Mode switch setting ; see
Fig . 1-
3 .
Fig . 1-3 .
Display mode
switch Location and
functions .
Alternate
Mode
The Alt position
(toward front panel) of
the Display
Mode switch produces
a display that
alternates between
the vertical
display and the gate
display with each
sweep
on the
crt . Although the
Alt mode can be used
atall sweep
rates, the Chopmode
provides a more satisfactory
display
at sweep rates belowabout0
.2 millisecond perdivision
. At
slow
sweep rates,
alternate mode
switching becomes
visually perceptible
.
Chop Mode
The Chop position
(toward rear) of the
Display Mode
switch
produces a display that is
electronically switched
between the input display and
the trigger gate display
at
approximately a 500
kilohertz rate (controlled
by main-
frame) . In
general, the Chop mode
provides the best
display
at sweep rates slower than
about 0 .2 millisecond
per division .
7D12
INSTALLATION
CAUTION
Extreme care
should be exercised when
handling
the 7D12 to
prevent touching any
part of the circuit
boards .
This unit contains
several high impedance
circuits which can develop
inter-leakage if con-
taminated by body
salts or acids . Refer to
the
Maintenance
Section of this manual
for
recommended
cleaning methods
and solvents .
The 7D12 is calibrated
and ready for use
with a module
as received . It
can be installed in any
compartment of
Tektronix
7000-series oscilloscopes,
but is intended
prin-
cipally for use in vertical
plug-in compartments
. To install,
align the upper
and lower rails of
the 7D12 with
the
oscilloscope
tracks and
fully insert it . The front is
flush
with
the front of the oscilloscope
when the 7D12 is
fully
inserted, and the latch
at the bottom-left
corner of the
7D12 will be in
place against the front
panel . See Fig . 1-4
.
Set the
oscilloscope for a
vertical mode to
correspond
with
the vertical
compartment used when an
analog signal
is
to be displayed .
The digital readout
will be displayed
regardless of the
vertical mode selected
.
To remove the
7D12, pull on
the latch (which is
inscribed
with the unit
identification "7D12") and
the
7D12
will unlatch . Continue
pulling on the latch to
slide
the
7D12 out of the
oscilloscope .
MODULE
INSTALLATION
All modules are
calibrated and ready
for use with the
7D12 as
received . To install,
align the upper and lower
rails of the module with the
7D12 module-compartment
tracks and fully insert
it . The front is flush
with the front of
the 7D12 when
the module is
fully inserted . Lock
the
module
securely in position
by rotating the
retaining knob
clockwise until it is
finger-tight . See Fig . 1-4
.
To
remove
the module, reverse the
above procedure .
Fig . 1-4 .
7D12 and module
installation .

INTRODUCTION
THEORY OF OPERATION
PRELIMINARY INFORMATION
This section of the manual describes the circuitry used
in the 71312 A/D Converter . The description begins with a
discussion of the instrument, using the basic block
diagram shown in Fig . 2-1 . Next, each major circuit is
described in detail, using detailed block diagrams to show
the relationship between stages in each major circuit .
Detailed schematics of each circuit are located
in the
Diagrams Section at the back of this manual ; refer to these
schematics throughout the following circuit description
for specific electrical
values
and relationships .
BLOCK DIAGRAM DESCRIPTION
INPUT
SCALEFACTOR,
MEASUREMENT UNIT,
DECIMAL POINT,
LAST DIGIT
SUPPRESSION
71312 A/D CONVERTER
TO
OSCILLOSCOPE
CHARACTER
GENERATOR
SIGNALTO
~ OSCILLOSCOPE
VERTICAL
1470-5
Fig . 2-1 . Block
diagram of moduleand 71312 A/D
Converter .
BLOCK DIAGRAM
Section 2-71312 Service
The function of each block in the basic block diagram,
Fig . 2-1,
is
readily apparent except for the Inverter Power
Supply . This supply permits floating the A/D Converter
section, enabling measurements with the inputs elevated
ashighas 1 kV . Further, not all modules utilize the Display
and Gate amplifier circuits shown . Each block represents
a major circuit within the instrument . The numbered
diamond in each block refers to the circuit diagram,
(located at the back of this manual) which covers that
specific part of the instrument .

Theory of Operation-7D12
Service
The 7D12 A/D Converter plug-in unit contains a fast, 4-
1/2 digit analog-to-digital converter, Inverter Power
Supply, Dual-Trace Vertical Amplifier, Readout Logic and
Trigger Logic circuit
.
The
modules process various
analog signals, such as peak voltage, rms voltage,
resistance, temperature, etc . and produce a do voltage
which the 7D12 converts to digital readout information for
the 7000-series oscilloscope . The modules also provide
an analog signal for display on the crt .
INTRODUCTION
2-2
LOGIC TRIGGERING
The block
diagram for the Logic Triggering circuitry is
shown in Fig . 2-2 . The trigger signal
is connected
internally from the 7D12 A/D Converter to the module .
The M1
and M3 modules return the trigger signal directly
to the
7D12 A/D Converter as an A/D Convert Command .
The M2 module, however, holds the trigger signal until the
M2 sampling process is complete before releasing an A/D
Convert Command .
TRIGGERING SWITCH
Auto Mode
II
I
M1 AND M3
DIRECT
INTERNAL
CONNECTION
i
I
I
I
MODULE
LOGIC
TRIGGER
a1
SIGNAL
L__A/D
CONVERT
b7 k
COMMAND
7D12 A/D CONVERTER
S424
TRIGGERING
60 ms
MULTIVIBRATOR
U440A,Q434
U436A
MAN
A/D BUSY TO 2
ms
MONOSTABLE
MULTI, U440B
TRIG'D
C R438
SINGLE
B15 SWEEP
RESET
A22 A/D BUSY
1470-6
Fig . 2-2 . Block diagram of the Logic
Triggering section .
Free-Run Oscillator Q610 is connected as the trigger
source . The oscillatorhasa nominal output frequencyof4
hertz .
External Mode
The Free-Run Oscillator
and +5 volt sources are
disconnected . External
trigger signals connected to the
7D12 EXT IN connector are used directly as the trigger
source .

Manual Mode
The
Free-Run Oscillator is disconnected and the EXT
switch is closed, shunting R422 . Manual operation
provides a +5 volt pulse as the trigger signal .
TRIGGER HOLDOFF
The trigger signal becomes the A/D Convert Command
either directly or indirectly, depending upon the module
used . TheA/D Convert Command switches the state of
the 60 mS Multivibrator . The multivibrator rejects all
additional A/D Convert Command signals during the 60
millisecond period . The TRIG'D indicator, CR438, is
energized during the 60 millisecond period to indicate the
measurement circuits
are busy .
4-1/2 DIGIT A/D CONVERTER
AND
LOGIC
INTRODUCTION
A block diagram of the 4-1/2 Digit A/D Converter and
Logic functions is shown in Fig . 2-4 . Refer to the
timing
diagram in Fig . 2-3 and the block diagram in Fig . 2-4
throughout the following discussion . All of the switches
shown in Fig . 2-4 are electronic switches such as MOS-
FETs, JFET's and diodes . The circuitry enclosed by the
dotted lines is a floating section powered by the Inverter
Power Supply . Positive logic is assumed to set
and reset
all circuit shown in the block diagram .
BEFORE TIME ZERO
The following conditions exist before a trigger signal
(A/D Busy) is received at the 2 mS Monostable MV
(Multivibrator) U440B .
1 . The analog output of the module is coupled to the 4-
1/2 Digit A/D Converter Vh ; and V, . electronic input
switches .
2 . Sw 1 is open and Sw 2 is closed, disconnecting Vh ;
and connecting V i . t o
the input of the Buffer and 1G m 1
Converter stages .
3 . Sw 3 is closed, connecting the Auto-Zeroing
Circuit
to
the
1Gm1
Converter . The Auto-Zeroing Circuit
automatically
produces
the same voltage level at Input 2
as that of the offset voltage appearing at Input 1, thereby
AT TIME ZERO
(to)
AT TIME ONE (t,)
Theory of Operation-71312 Service
holding the 1G .1 Converter output at zero volts . Capacitor
C302 stores the offset voltage required to
hold the 1G m 1
Converter
output at zero volts during integration .
4 .

Sw 6 is closed, setting the Integrator output to zero
volts .
A negative-going trigger pulse (A/D Busy)
Sets
the 2
ms Monostable MV U440B . The 0 output of the MV holds
the Clock Sync ff (flip-flop) Master Reset and the
Measurement Period ff, Set on for 2 milliseconds . The 0
output pulse from the Clock Sync ff performs the follow-
ing functions :
1 . Sets the A/D Standby ff changing the electronic
switch stages
as follows :
a . Sw 1 closes and Sw 2 opens,
disconnecting
Vi .
and connecting Vh ; to
the input
of
the Buffer and I
Gm1
Converter stages .
b . Sw 3 opens, disconnecting the Auto-Zeroing
Circuit from the JGm J Converter output . The charge
on capacitor C302 maintains the offset voltage
balance between Input 1 and Input 2 ; therefore, the
JG, o J Converter output remains referenced at zero
volts .
c . Sw 6 opens, arming the Integrator circuit .
2 . Sets the Measurement Period ff .
3 . The 1 output from the 2 ms Monostable MV U440B,
Resets the 4 Decade Counter-Latches in U500, thereby
clearing any stored information from the previous
measurement .
The 2 millisecond delay between t
o
and t, allows all
switching circuits and the 1Gm1 Converter to stabilize
before starting the measurement .
The 2 ms Monostable MV, U440B, returns to its original
state, thereby releasing the Clock Sync ff Master Reset
.
The first negative-going pulse
from the 1 mHz Clock
Generator,
U402, Sets the Clock Sync ff . The 0 output
from the Clock Sync ff enables AND gate U436C and
U492C, allowing the clock signal to pass and begin
counting at the Counters . The 0 output
from the Clock
2- 3

Theory of
Operation-7D12 Service
TIME
TRIGGER
PULSE
2 ms MULTI
U440B ON
SW 1 CLOSED
SW
2, SW 3 OPEN 1
START RAMP
PULSE
OUTPUT OF
INTEGRATOR
SW 5 CLOSED 1
SW
6 OPEN 1
20
K COUNT
PULSE
STOP
COUNT
PULSE
t
0
t
1
t
2
t
3
I

1
20 ms
A/D STANDBY
PULSE
f--- 2 ms - yl "
CLOCK SYNC
FF 1 OUTPUT
SW4
CLOSED 1

I IN
1 The switch states mentioned occur at
the positive-going transition .
1470-7
2-
4
Fig . 2-3 . Timing diagram of
the 4 1/2 Digit A/D Converter .

Sync ff also enables the Start Ramp ff, closing Sw 4 . The
rectified input
current (I, .) from the jGmj Converter begins
to charge capacitor C379 in the Intergrator .
The 0 output from the Clock Sync ff Sets the A/D
Converting Pulse Generator ff, U436B and D, thereby
allowing the 1 output
to go
hi at
t, .
AT TIME TWO (t z )
The 4 decade Counter-Latches and =4 ff have counted
20,000 clock pulses . At the 20K count, the =4 ff generates
a negative-going pulse to the 20K Count
Logic circuit . The
output of the 20K Count Logic changes the electronic
switch states as follows :
1 . Resets the Start Ramp ff that switches :
a . Sw 4 open, disconnecting
the ~Gmj Converter
output from the Integrator .
2 . Sets
Stop Count ff that switches :
a . Sw 5
is closed, connecting the Reference
Current Generator output to the Integrator .
3 .
Resets the A/D Standby ff that switches :
a . Sw 1 is open and Sw 2 is closed, disconnecting
the input
signal to the Buffer and jGmj Converter
stages .
b . Sw 3 is closed, connecting the
Auto-Zeroing
Circuit to the ~Gmj Converter .
4 . Resets the A/D Converting
Pulse Generator ff,
U436B and D . The 1 output goes hi at t, and
to at tz . The
A/D Converting Pulse is connected to the module
gate
circuitry,
allowing the measured gating time (t,-t2) to be
observed
on
the
crt display
.
AT TIME THREE
(t 3 )
Theory of Operation-71312
Service
The Reference Current Generator output current (I re
r)
begins discharging C379, and the 4 Decade Counters-
Latches are cleared to measure C379 discharge time .
The output of the Integrator (C379) is discharged to
zero volts and the
Comparator output Resets the Stop
Count ff . The 0 output
of
the
Stop
Count ff changes the
electronic switch states as follows :
1 . Sw 5 opens, disconnecting the Reference Current
Generator .
2 . Sets the Integrator Zeroing Logic circuit, closing
Sw 6 . Sw 6 holds the
Integrator output
level
at zero
volts
.
3 . Resets the Measurement
Period
ff . AND gates
U436C and U492C are disabled, preventing the 1 MHz
clock pulse from reaching the counters . AND gate U492D
is enabled,
transferring
the stored
information
in
the 4
Decade Counters and
-
4 ff to the Latches . The output of
the Latches is connected to the Readout Control Section
in the mainframe .
A 60 millisecond
monostable
multivibrator in the
Trigger Logic circuit prevents another trigger from
oc-
curing until one measurement cycle has been completed .
INTRODUCTION
READOUT LOGIC
The Readout Logic circuit encodes the Indicator
Oscilloscope readout system to display the measurement
made by the 71312 and module . The Readout Logic circuit
also encodes the readout system to display the ap-
propriate
measurement units and polarity symbols, along
with positioning the display decimal point and indicating
an over-range measurement .
A discussion entitled
the Tektronix Readout System
following the 71312 Theory
of
Operation gives a brief
description of the readout system used
in Tektronix 7000-
series Oscilloscopes .
2-5

1C
N
A
D
W
O
0
x
a
of
3
0
s
m
A
f
N
IS
v
0
0
m
N
m
m
7
1470-16A
0
0
O
1
d
K
V
v
N
N
<D
n
!D

T
b
N
A
W
O
!!
a
d
10
d
3
0
m
A
J
N
v
D
w
v
0
7
N
1
fD
A
m
0
N/D BUSY
FROM
FRIGGER
LOGIC
STOP
COUNT
MASTERi
RESET
Q480
1 MHz
START RAMP

A/D STANDBY
RESET
COUNTERS
20 .8 kHz
TO INVERTER
POWER SUPPLY
Q507
20 K COUNT
LOGIC
TO
OSCILLOSCOPE
READOUT
CONTROL
SECTION
t1 t2
A/D
CONVERTING
PULSE TO
MODULE
1470-16B
S
N
O
O
<D
O
7
V
v
j
N
N
N
n

Theory of
Operation-7D12
Service
ENCODING
FORMAT
The 7D12 Readout Logic
circuit encodes the Row and
Column output
lines (pins B37-A37 respectively
of the
oscilloscope
Interface Connector for
channel 1, and pins
A38-1338
for channel
2) according to the format given in
Table 2-1 . The time-slot
pulses from the oscilloscope
readout system are
provided to the Readout Logic
circuit
through
the Interface Connector . Several of
the time-slot
pulses are also connected to
address-the Multiplexers .
TABLE 2-1
7D12 READOUT FORMAT
DIGITAL-TO-ANALOG
CONVERTER
Refer to the Readout Logic block diagram
shown in Fig .
2-5 throughout the following discussion
.
The Digital-to-Analog Converter circuit
includes D-A
Converters U500, Q540, Q532 and Q552
.
2 - O
Time-slot pulses
TS-4, TS-5 and TS-6 from the main-
frame are connected to U500 to drive the
Output Enable
inputs of the D-A
Converters . Time slot pulse TS-3 from
the mainframe is connected to the emitters of D-A
Converters Q540, Q532, and Q552 to
provide Output
Enable information of the most
sign ificantdigit . Time-slot
pulse, TS-7, encodes Least
Significant Digit Blanking,
depending upon
the module .
POLARITY AND
OVER-RANGE INDICATOR
The Polarity Enable information to 0524 is
determined
by
the module . Time-slot pulse TS-2 is coupled
to Q524
(via switching in the module) to
provide the Polarity
Enable pulse . If the input to the
base of Q524 goes to a to
level, current is added
to the Column Current output
during
TS-2
. This added current in TS-2 results in the
+
symbol
being changed to - . TS-2 also
enables the Over-
Range Indicator . When the output
of U514A goes to a to
level, current is added to
the Column Current in TS-2 . This
added current
in TS-2 changes either polarity symbol to a
> symbol
display .
SCALE
FACTOR DISABLE
The VERTICAL
DISPLAY ATTEN switch encodes the
module
readout system by switching resistors
between
TS-4
and the module Column output
line . The Scale
Factor Disablecurrent mixes
with theappropriate module
time-slot inputs to supply
current to the Column output
line . The readout system
then displays the measurement
unit in channel
2forthecombination (7D12ATTENswitch
and
module attenuator switch) measurement
setting
selected .
THE TEKTRONIX
READOUT SYSTEM
INTRODUCTION
The
following discussion is provided to
acquaint the
7D12 user with the Readout
System used in Tektronix
7000-series
Oscilloscopes . Since the oscilloscope
Readout System
provides the digital readout
for the 7D12,
it is
necessary to relate the function
of the 7D12 to the
Readout System to gain
a better understanding of the
7D12 operation . A detailed
circuit description of the 7000-
series
Readout System is given in the
oscilloscope
instruction
manual .
THE READOUT
SYSTEM
The Readout
System in the 7000-series
oscilloscopes
provides
alpha-numeric display of
information encoded
A
Time-Slot
Function
Programmed
Number By
TS-1 Determines
decimal position Module
TS-2
Indicates polarity (+
7D12 (Disabled
or - symbol) of
by Module)
measurement .
Encodes a > symbol to
7D12
indicate
over-ranging .
TS-3 Encodes 1 or 2, and blanking
7D12
of the most
significant digit
of measurement readout .
TS-4, TS-5 Remaining four
digits
of
7D12
TS-6, TS-7
measurement readout .
TS-7 also encodes
blanking Module
of the least
significant
digit of
the measurement
readout .
TS-8
Symbols Module
TS-9 Symbols
Module
TS-10 Sy
mbols I Module

MODULE

71312 A/D CONVERTER
a13
s
TS
8
TS 9

TS 9
a12

TS
10

TS 10
all
CH 2 COLUMN

CH 2 COLUMN
CHI ROW

CH 1 ROW
CH 1 COLUMN

CHI COLUMN
b13

B38
b12

A38
b15

B37
b14

A37
a14
a15
b16
a17
a18
a19
a20
R
(F
POLA
(FRO
COUP
b18
POLARITY ENABL
TS 8
MAINFRAME
t A30
t B29
t A29
B30
A31
B31
A32
B32
A33
B33
622
1470-15
Fig . 2-5 . Block diagram of the Readout Logic
section .
Theory of Operation-71312 Service
uv
I M I 1 MI-4 ~ O
2- 9
Rll6
SCALE FACTOR DISABLE 61,
(1, 2, or
5,CH 2 ONLY)
F
CH 2 ROW
R114
CH 2 ROW
LEAST
SIGNIFICANT DIGIT BLANKING
R557
TS 7
TS 7
TS 6_
TS 6
TS5
TS
5__ 11 _
TS 4
TS 4
TS 3
In~ TS 3
TS
2
TS 2
TS 1
TS 1
GATED
ESET PULSE
1 MHz
I
ROM U440B) C CLOCK 11500
1
I&i131'I 1
.1
LATCFi
D TU A
DECAI)E CONVERT - ER
COUNTER
2 UU I PUT
RRT ENABLE
IF IF if
LATCH
D TU A
DECAD E
CONVERTER
COUNTER
OUTPUT
R T
ENABLE
- IF IF
DECADE
LATCH
D l - O A
COUNTER
CONVERTER
I OUTPUT
R T
I .
ENABLE
i
DECADE LATCH
D TO A
COUNTER
CONVERTER
OUTPUT
COLUMN
R T ENABLE
CURRENT
8 IR REFERENCE
510
O
R499
GENERATOR
CARRY
OUT
CO
D TO A
10 K COUNT
2 BIT
CONVERTER
2
BIT - - LATCH
Q540
COUNTER ~~ Q532 OUTPUT
U509A, B
U51 4A, B
Q552 ENABLE
Q507 T
DTOA
20 K
CONVERTER
COUNT
OVERRANGE
_ TRANSFER
Q 5 47
OUTPUT
U492D
PULSE
~
ENABLE
RITY INFO
HOLD (NOT USED)
M OPTICAL
LER U289) 1 BIT
D TO A
HELDLO
U492 LATCH
CONVERTER
T U514C
Q524
OUTPUT
ENABLE

Theory of
Operation-7D12
Service
by
the plug-in units . This display is presented on the
crt,
and is written by the crt beam on a
time-shared basis with
the analog waveform
display .
The Readout System produces
a pulse train consisting
of 10 negative-going
pulses called time-slot pulses . These
pulses
are assigned time-slot numbers
corresponding to
their relative position in the pulse
train . Each time-slot
pulse is directed to
one of ten output lines, labeled TS-1
through
TS-10 (time-slots one through ten)
and are
connected to the vertical and
horizontal plug-in com-
partments . Two output
lines, rowand column, are con-
nected from
each channel (two channels per plug-in
compartment) back to the Readout System .
Data is encoded on these output
lines either by
connecting resistors
between them and the time-slot
input lines or by generating equivalent
currents . The
resultant output is a sequence of
analog current levels on
the row and column output
lines . The row and column
current levels are
decoded by the Readout System to
address
a character matrix during each time-slot
pulse,
thus selecting a character to be displayed
or a special
instruction to be followed .
1100
4O

POWER &
CONNECTORS
7D12
A/D CONVERTER
R613
VR613
T595
Q590
Q593
C593
Q600
Q603
+15V
SSYNC PULSES
FROM
CLOCK
GENERATOR
1470-8
2- 1 0
INVERTER
FLOATING REGULATORS
Fig . 2-6 . Block diagram of the
Inverter Power Supply .
INVERTER POWER
SUPPLY
The block
diagram of the Inverter Power Supply
is
shown in Fig . 2-6 . The Inverter is
driven with divided-down
sync pulses from
the 1 MHz Clock Generator . The sync
pulses switch
-15 volts alternately through
the
transformer primary to the +15 volt
supply at the center
tap . The Inverter side of the transformer
is referenced to
chassis potential
.
The+15 and
-15 volt regulator voltages are based
upon the +5
volt Reference voltage . The secondary of
the
transformer and associated circuitry are
referenced to
floating ground . Each floating
regulator circuit is
equipped with short-circuit
protection . The floating
power supply furnishes
all the power for the floating
portion of the instrument
.

DUAL-TRACE
VERTICAL AMPLIFIER
GATE AND SIGNAL DISPLAYS
The block diagram for the amplifier is
shown in Fig .2-7 .
The Gate Display signal is fed
directly to CH 1 of the
Channel Switch . The Signal
Display information passes
through
an Attentuator to CH 2 of the Channel Switch .
Chop or alternate drive pulses (selected by the internal
Mode switch) to the Channel Switch is supplied by the
mainframe . The switched
Gate and Signal Display infor-
mation pass through the Signal Amplifier to the main-
frame to the displayed on the crt .
TRIGGER PICKOFF
The attentuated
Signal Display information passes
through a Trigger Amplifier to the
mainframe and triggers
the time base .
INTRODUCTION
CIRCUIT
OPERATION
This section provides a detailed description of the
electrical operation and relationship of the circuits in the
7D12 . The theory of operation
for
circuits
unique to this
instrument is described in detail in this discussion .
Fig . 2-7 .
Block diagram of the Dual-Trace Vertical
Amplifier section .
Theory of Operation-7D12
Service
Circuits commonly used
in the electronics industry are
not
described in detail . If more information is desired on
these commonly used circuits, refer to
the following
textbooks .
Jacob Millman and Herbert Taub, "Pulse, Digital,
and
Switching Waveforms",
McGraw-Hill, New York, 1965 .
Robert C . Baron and Albert T . Piccirilli, "Digital Logic
and Computer Operations",
McGraw-Hill, New York,
1966 .
Thomas C . Bartee, "Digital
Computer Fundamentals",
McGraw-Hill, 1962
.
Yaohan Chum,"Digital Computer Design
Fundamen-
tals, "McGraw-Hill, 1962 .
Neil A Robin,
"Analog-To-Pulse-Width Converter
Yields 0 .1%
Accuracy", EDN Journal, Vol . 15, Issue 21,
November 1, 1970, page 42 .
POSITION
POSITION
GATE
2- 1 1

Theory of Operation-7D12
Service
VERTICAL AMPLIFIERO
VERTICAL DISPLAY ATTENUATOR
Module signal display information is coupled to the
7D12 vertical amplifier through pin b20 on J100
.
Refer to
the Vertical Amplifier diagram
1 in Section 6 . The signal
display passes through an attenuator network (selected
by ATTEN switch S110) to the amplifier
circuitry . The
ATTEN switch
is
a rotary-cam type and is shown in the 1 X
(unity
gain) position . Module signal display output
voltage to the CH 2 vertical amplifier are standardized in
the 1X ATTEN switch position . The 2X and 5X positions
are referenced to the 1X attentuator
network . Each
attenuator network presents a
1 kilohm load to the signal
display output
in the module . High-frequency compensa-
tion adjustments C102, C106 and C110 are adjusted to
minimize front corner rolloff and peaking . The CH
2 high-
frequency compensation
network connects to pins 8 and
9 of
U148 .
DISPLAY
OFFSET
The signal display passes from the attentuator network
to one side of
the CH 2 differential amplifier (pin 7, U148) .
The other side of the differential amplifier (pin 10, U148)
connects to the VERTICAL
DISPLAYPOSITION control,
R131
.
The POSITION control, R131,supplies
avariable dc
voltage to
the no-signal
side
of the differential amplifier,
allowing vertical trace positioning . With no-signal input,
U148 pin 7 draws a small amountof currentthrough R105,
R109 or R112 depending upon
the ATTEN switch setting .
The resulting voltage drop across these resistors can
cause vertical trace shift as the ATTEN switch setting is
changed . Display Offset adjustment R138 is set
to supply
U148
pin 7 with the required current . When properly set,
R105, R109 and R112 will have zero voltage drop .
TRIGGER LEVEL
A pickoff of the attenuated signal display information is
amplified by Q170 and Q177 . The base of 0170 and the
collector of
0177
should be
zero volts during a no-signal-
in condition . The amplifier is balanced by setting the Q177
collector (TP177) to zero volts using the Trig Level
adjustment R169 . In the balanced condition signal display
information to
the
base of
Q170 will have equal amplitude
in the positive-and negative-going excursions to internal-
ly trigger the time base .
GATE DISPLAY
Gate display
information from the module
is
coupled to
the vertical amplifier through pin b10 on J100 . The gate
display signal passes through voltage divider R128, R127
and transformer T125 to one side of differential amplifier .
2-12
The other side of the differential amplifier (pin
2,
U148)
connects through T125 to the
GATE POSITION control
R120 . GATE POSITION
control R120 supplies a variable
do voltage
to the no-signal side of the differential
amplifier, allowing gate trace positioning . Transformer
T125 allows the differential amplifier to operate push-pull
at the higher frequencies thereby reducing front-corner
degeneration . GATE DISPLAY switch S165 is
the
ON
position couples
pin 4
of
U148 to the channel switching
signals from the mainframe . The CH 1 high-frequency
compensation network connects to
pins 1 and 16 of U148 .
DISPLAY MODES
The GATE switch (S165) ON position connects the
internal Display Mode
switch, S142, to the mainframe
chop
and alternate drive signals which couple to pin 4 of
U148 . The output of U148 (pins 12 and 13) will either chop
or alternate between CH 1 (pins 2 and 15) and CH
2 (pins 7
and 10) depending on the Display
Mode switch setting .
GATE switch S165,
in the OUT-OFF position, holds pin 4
of
U148 high allowing CH 2 only to pass .
VERTICAL AMPLIFIER OUTPUT
Channel Switch U148, pins 12 and 13, is connected to
the output amplifier Q190 and Q200 . Voltage
dividers
R205, R206, and
R215, R216 presentan output impedance
of 50 ohms to the mainframe . Refer to Table 2-2 .
INPUT
DISPLAY MODE
SIGNAL
4
LO
HI
TABLE 2-2
U148 INPUT/OUTPUT TABLE FOR
CH 1 AND CH
2 DISPLAY MODES
OUTPUT
VERTICAL
OUTPUT
SIGNAL
12, 13
CH 1 and CH 2
Chopped or
Alternating
CH 2