Teledyne SP Devices ADQ7DC User manual

ADQ7DC Manual
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Teledyne Signal Processing Devices Sweden AB | Teknikringen 6, SE-583 30 Linköping, Sweden | www.spdevices.com
Regional sales offices | www.spdevices.com/contact
Manual ADQ7DC
This manual describes how to get the full potential out of Teledyne SP Devices’
digitizer ADQ7DC. The manual includes these steps:
• Set up the analog front-end
• Master the triggers
• Control the acquisition
• Manage the sampling clock
• Understanding data transfer to host PC
• Using GPIO

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Table of content
1 INTRODUCTION ........................................................................................................... 5
1.1 ADQ7DC Architecture.................................................................................................... 5
1.2 Fundamental design properties ..................................................................................... 5
1.2.1 Data format .................................................................................................................................. 6
1.2.2 Calibration.................................................................................................................................... 6
1.2.3 Data acquisition nomenclature .................................................................................................... 6
1.2.4 ADQ7DC sampling clock frequency ............................................................................................ 7
1.2.5 System clocks.............................................................................................................................. 7
1.2.6 Analog signal range ..................................................................................................................... 7
2 SETTING UP THE ANALOG FRONT-END ................................................................... 9
2.1 AFE block diagram......................................................................................................... 9
2.2 Set analog DC-offset...................................................................................................... 9
2.3 Adjusting the digital gain and offset ............................................................................. 10
3 SIGNAL QUALITY ENHANCEMENT........................................................................... 11
3.1 Digital Baseline Stabilizer ............................................................................................ 11
3.2 Interleaving correction ADX ......................................................................................... 11
4 TRIGGER..................................................................................................................... 12
4.1 Trigger block diagram .................................................................................................. 12
4.2 Position of the trigger in the data ................................................................................. 13
4.3 Timestamp ................................................................................................................... 13
4.3.1 Timestamp definitions................................................................................................................ 13
4.3.2 Timestamp reset ........................................................................................................................ 14
4.4 Blocking triggers for synchronization ........................................................................... 16
4.4.1 Function overview...................................................................................................................... 16
4.4.2 Block triggers once .................................................................................................................... 17
4.4.3 Windowing triggers .................................................................................................................... 17
4.4.4 Gating and windowing triggers .................................................................................................. 17
4.4.5 Programming sequence for using trigger blocking .................................................................... 17
4.5 Trigger jitter.................................................................................................................. 18
4.5.1 Trigger jitter definitions .............................................................................................................. 18
4.5.2 Asynchronous triggering ............................................................................................................ 18
4.5.3 Synchronous trigger................................................................................................................... 19
4.5.4 Extended trigger resolution........................................................................................................ 19
4.6 Software trigger............................................................................................................ 19
4.7 External Trigger Inputs................................................................................................. 20
4.7.1 External trigger TRIG front panel connector .............................................................................. 20
4.7.2 External trigger SYNC connector............................................................................................... 21
4.7.3 Driving the external TRIG/SYNC signal by controlling input impedance ................................... 21
4.8 External trigger in the backplane ................................................................................. 22
4.8.1 PXIe interface ............................................................................................................................ 22
4.8.2 MTCA.4 interface....................................................................................................................... 23
4.9 Level trigger ................................................................................................................. 24
4.9.1 Setting the level trigger level...................................................................................................... 25
4.9.2 Level trigger and DBS................................................................................................................ 25
4.9.3 Controlling noise sensitivity ....................................................................................................... 25
4.10 Internal trigger.............................................................................................................. 26
4.11 Trigger output............................................................................................................... 26
4.11.1Trigger output port selection ...................................................................................................... 26
4.11.2Frame sync output on SYNC connector .................................................................................... 27

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4.11.3Trigger event indicator ............................................................................................................... 27
4.11.4Triggering external equipment with internal trigger.................................................................... 27
4.11.5Distributing level trigger ............................................................................................................. 29
5 CLOCK......................................................................................................................... 30
5.1 Clock domains ............................................................................................................. 30
5.2 Flexible clock network.................................................................................................. 30
5.3 Front panel SMA connector ......................................................................................... 31
5.4 Internal clock reference................................................................................................ 31
5.5 External clock reference .............................................................................................. 31
5.6 Internal clock generator ............................................................................................... 32
5.7 External clock............................................................................................................... 32
5.8 Clock reference output................................................................................................. 32
5.9 Sample skip ................................................................................................................. 32
6 GPIO ............................................................................................................................ 33
6.1 GPIO with TRIG and SYNC ......................................................................................... 33
6.2 Using GPIO as a trigger............................................................................................... 33
6.3 Output .......................................................................................................................... 34
6.4 GPIO in ADQ Development Kit .................................................................................... 34
6.5 Dedicated GPIO connector on form factor –PCIe or –PXIe......................................... 35
7 ACQUISITION CONTROL ........................................................................................... 37
7.1 Multi-thread notice ....................................................................................................... 37
7.2 Acquisition memory...................................................................................................... 37
7.3 Acquisition modes........................................................................................................ 38
7.3.1 Continuous streaming acquisition.............................................................................................. 38
7.3.2 Triggered streaming acquisition................................................................................................. 39
7.3.3 Multi-record acquisition.............................................................................................................. 39
7.4 Data transfer modes .................................................................................................... 40
7.4.1 Streaming data transfer mode ................................................................................................... 40
7.4.2 User-scheduled data transfer mode .......................................................................................... 42
7.4.3 Transfer buffers ......................................................................................................................... 44
7.4.4 User’s buffers............................................................................................................................. 44
7.5 Users application software consuming data ................................................................ 44
7.6 Record header ............................................................................................................. 45
7.6.1 Metadata.................................................................................................................................... 45
7.6.2 Record Status ............................................................................................................................ 45
7.6.3 User ID....................................................................................................................................... 46
7.6.4 Serial number ............................................................................................................................ 46
7.6.5 Channel ..................................................................................................................................... 46
7.6.6 Record number .......................................................................................................................... 46
7.6.7 Data format ................................................................................................................................ 46
7.6.8 Record length ............................................................................................................................ 46
7.7 Over-range and under-range ....................................................................................... 47
8 HOST PC CONNECTION............................................................................................ 48
8.1 USB interface............................................................................................................... 48
8.2 PCI Express interface .................................................................................................. 48
8.3 Using several units....................................................................................................... 48
8.3.1 Using several digitizers from a single application. ..................................................................... 48
8.3.2 Using several digitizers from a several applications. ................................................................. 48
9 REFERENCES ............................................................................................................ 49

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1 INTRODUCTION
The purpose of this manual is to explain how the digitizer is operated. The datasheet [1] contain param-
eters for the specific versions of digitizer. References to software commands are made. In some places,
pseudo code is used for description. See [2] for details on how to use the software commands and see
[3] for general guidelines on programming the digitizer.
1.1 ADQ7DC Architecture
The ADQ7DC architecture is shown in Figure 1. References to the corresponding sections with further
information are also included.
1.2 Fundamental design properties
There are some fundamental design properties that are necessary to understand before continuing.
#DESCRIPTION REFERENCE
a Switch between 1 channel and 2 channels 2
b Signal conditioning analog front-end. 2
c High speed and high resolution A/D converter. The A/D converter operate interleaved at
5 GSPS per channel. The A/D converters can be further interleaved to get 10 GSPS.
3
d Digital calibration of gain and offset. 2
e Teledyne SP Devices’ proprietary technologies for signal quality enhancement; ADX for
SFDR in radio systems and DBS for baseline stability in pulse data systems.
3
f Acquisition engine that handles triggers and controls the data flow. 4, 7
g Data FIFO to buffer data before transmission to the host PC. 7
h The data transfer to the host PC is through a PCIe or a USB3.0 link. 7
i Flexible clock generator 5
j General Purpose digital Input and Output control. 6
Figure 1: ADQ7 architecture.
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1.2.1 Data format
The ADC components of ADQ7DC has 14 bits resolution, while the data format inside the ADQ7DC
and out to the host PC is 16 bits. The 14 bits from the ADCs are MSB aligned in this 16 bit data word.
Thus initially the 2 LSBs are zero.
The number representation is 2’s complement. The full scale maximum code is then 32 767 and the full
scale minimum code is –32 768. Overflow or underflow at any position in the signal path will saturate
the data and turn on an overflow flag. See Section 7.7 for more information on over- and under-flow.
The 2 LSBs may not be zero in the data output from the ADQ7DC. Calibration and other computations
in the FPGA may result in fractional result. This is not rounded to 14 bits in order to avoid adding com-
putational noise.
Example 1: A 14 bits sequence of data is subject to a gain calibration parameter of 1063. This means
that the digital word is corrected by 1063 / 1024, Section 2.3. Table 1 illustrate how the lowest bits con-
tain computation results. The analog signal level is calculated from Section 1.2.6.
1.2.2 Calibration
During the factory calibration procedure the analog properties are measured and parameters for a digi-
tal compensation are computed. An analog deviation in the front-end is thus compensated for by the
inverse function in the digital signal processing part.
Example 2: The full scale signal range of the ADQ is measured in production and the SetGainAndOff-
set function is used for adjusting to the correct signal range.
1.2.3 Data acquisition nomenclature
Table 2 defines some key data acquisition terms.
Table 1: Example of how computation results sets the lowest two LSBs.
ADC RAW CODES1
1. This is the raw codes from the ADC. It is 14 bits MSB aligned in 16 bit word. The 2 LSBs are thus 0.
GAIN CORRECTION DIGITAL CODE
LEVEL2
2. This is the result from the gain compensation. The 2 LSBs now contain a fractional result from the
computation.
ACTUAL ANALOG
RANGE
ANALOG LEVEL3
3. This is the corresponding analog signal that was present at the input at the time of measurement. See
Section 1.2.6 for details on how this is calculated.
0x0000 1063 / 1024 0x0000 1 Vpp 0.0 mV
0x0004 1063 / 1024 0x0004 1 Vpp 0.061mV
0x0008 1063 / 1024 0x0008 1 Vpp 0.122 mV
0x000B 1063 / 1024 0x000B 1 Vpp 0.168 mV
0x0010 1063 / 1024 0x0011 1 Vpp 0.259 mV
0x0014 1063 / 1024 0x0015 1 Vpp 0.320 mV
0x0018 1063 / 1024 0x0019 1 Vpp 0.381 mV
0x001B 1063 / 1024 0x001C 1 Vpp 0.427 mV

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1.2.4 ADQ7DC sampling clock frequency
ADQ7DC is designed for the specified clock frequencies only. A different sampling rate can be
achieved by using the sample skip function, Section 5.9.
The ADQ7DC is available in two different speed modes, 5 GSPS dual channel and 10 GSPS single
channel. Both modes are supported by the hardware and included with the ADQ7DC. The firmware of
the FPGA has to be changed when switching mode. This may require a re-start of parts of the system.
Use the ADQ7 Updater tool to switch firmware.
Some parts of the descriptions and examples are done for only one of these frequencies. The exam-
ples are translated to the other sample rates by multiplying or dividing with the corresponding sample
rate ratio.
1.2.5 System clocks
The different parts of the digitizer operate on different clock rates
The sampling of the analog signal is done on the sampling clock of the ADC (see Section 1.2.4).
The external trigger input has a trigger clock which is higher than the sample clock for high trigger time
precision (20 GHz).
The different host PC connections (USB, PCIe etc) has their own respective clock system.
All other interfaces operate on the data processing clock of the FPGA at 312.5 MHz. This clock is
referred to as the Data Clock.
See Section 5.1 for more details on the clock system.
1.2.6 Analog signal range
The analog signal range (ACTUAL_ANALOG_RANGE) is 1 Vpp and is by default symmetrical around
zero. The range can be adjusted from [–0 mV +1000 mV] to [–1000 mV +0 mV] by the DC-offset fea-
ture, Section 2.2.
Table 2: Data recording nomenclature.
PARAMETER DESCRIPTION REF
ADQ Collective name for digitizers from Teledyne SP Devices.
Analog Analog signal is the input to the digitizer. This is the signal to be digitized.
Waveform Analog signal with a distribution in time. This is digitized into a record.
Sample An analog signal level is digitized into a sample, that is a numerical value.
SYNC Physical connector on the front panel. 4.7, 6.1
Record A set of consecutive samples is called a record. An analog waveform is
digitized into a record of samples.
4
TRIG Physical SMA connector on the front panel. 4.7, 6.1
Trigger Trigger is a real-time event that starts acquisition of a record. 4.2
Timestamp Timestamp is a real-time value that identifies when a trigger happened.
The timestamp gives timing information for each sample.
4.3
GSPS Giga-samples per second (109). Clock frequency [Hz] and sample rate
[SPS] are both used to denote speed.
MSPS Mega-sample per second (106).
DC-offset This is an analog DC level which is added to the analog input signal inside
the digitizer to vertically move the analog signal to fit within the range of
the digitizer. This effectively doubles the ENOB for a unipolar signal.
2

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The maximum digital code 2^15 represents an analog signal with a level ACTUAL_ANALOG_RANGE / 2
at the input. A specific analog signal ANALOG_LEVEL will then be represented by the following digital
code:
DIGITAL_CODE_LEVEL = ANALOG_LEVEL / ( ACTUAL_ANALOG_RANGE / 2 ) * 2^15 (1)
A specific code DIGITAL_CODE_LEVEL then represent the analog level as:
ANALOG_LEVEL = ( DIGITAL_CODE_LEVEL / 2^15 ) * ( ACTUAL_ANALOG_RANGE / 2)(2)

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2 SETTING UP THE ANALOG FRONT-END
2.1 AFE block diagram
The analog front-end setup for ADQ7DC is found in Figure 2.
The ADQ7DC can operate with two channels at 5 GSPS or one channel at 10 GSPS. To change mode
of operation, the single or dual channel firmware has to be activated by using the ADQ7 Updater tool1.
For more information, see [6]. Note that there are different connectors for the single and dual channels
mode. This means that one detector for 10 GSPS can be connected to the channel X at the same time
as two slower detectors are connected to channel A and B.
The switch between the 1 analog input channel and 2 analog input channels modes is set in the correct
state when loading the firmware. The switch may also be controlled from software2. The front-end
switch can be used for protecting the input. By switching to the un-used input, the switch can discon-
nect the detector during certain risky operations like power up/down of detectors.
2.2 Set analog DC-offset
A user-controlled DC-offset is available. The analog DC-offset is applied to the signal to better adopt to
the signal range of the digitizer. The analog range is by default set symmetrical around zero. If the sig-
nal is unipolar or heavily unsymmetrical, the DC-offset function can adjust the signal to an optimal verti-
#DESCRIPTION USER COMMAND REF
a The analog input is terminated 50 ohms to GND.
b Switching between 1 and 2 channels. Load the correct firmware using
ADQ7 updater tool. This will set the input switch.
The input switch can also be controlled by a software command for
disconnecting the input. Note that this command do not change the ADQ7
from 1 to 2 channels acquisition.
SetAfeSwitch 2.1
c Set a DC-offset for better using the signal range when the signal is
unipolar. Changing the DC-offset requires a settling time of 1 s.
SetAdjustableBias 2.2
d The gain and offset are calibrated at DC. The digital compensation
corrects the offset and the gain at this condition. The user can access this
function to set a different gain and offset.
SetGainAndOffset 2.3
Figure 2: ADQ7 AFE control.
1. Note that there is one ADQ7 updater tool for ADQ7 and another ADQ updater for other ADQ digitizers.
2. Note that the software switch only changes the input. To change function, the firmware has to be loaded.
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cal position for the A/D converter. In this way, the full 14 bits can be used for representing the unipolar
pulse. The DC-offset is set with the command SetAdjustableBias.
The DC-offset is set in digital codes DC_OFFSET_CODE in the range [-2^15: 2^15-1], which correspond
to an analog signal level in the range:
[ –ACTUAL_ANALOG_RANGE / 2: ACTUAL_ANALOG_RANGE / 2 ]. (3)
To determine the parameter of SetAdjustableBias to get a DC-offset at the voltage level DC_OFF-
SET_ANALOG, use:
DC_OFFSET_CODE = round ( DC_OFFSET_ANALOG / ( ACTUAL_ANALOG_RANGE / 2 ) * 2^15 ) (4)
Since the digitizer has higher resolution than the intrinsic accuracy of the DC-offset generator, the
actual digital codes read out from the ADQ may differ from the expected level. For accurate baseline
measurements, the Digital Baseline Stabilizer (DBS) offers a digital correction of the baseline to an
accuracy of 22 bits, Section 3.1.
2.3 Adjusting the digital gain and offset
The digital gain and offset block is primarily intended for factory calibration but it may also be accessed
by the user, and offers an efficient way of scaling the signal to suit processing in the PC.
The default setting is the calibration parameters CAL_GAIN and CAL_OFFSET. The raw data from the A/
D converter, ADC_RAW_CODE, is corrected with the calibrated values according to:
DIGITAL_OUTPUT_CODE = ADC_RAW_CODE * CAL_GAIN – CAL_OFFSET (5)
The user can override these settings by using the software command SetGainAndOffset. The parameter
USER_GAIN and USER_OFFSET can be applied in two ways; relative to the calibrated value or relative
to the raw code.
The normal mode of operation is to apply the gain and offset settings relative to the calibrated data as
DIGITAL_OUTPUT_CODE =
ADC_RAW_CODE * CAL_GAIN * USER_GAIN – CAL_OFFSET – USER_OFFSET. (6)
By setting bit 7 in the channels parameter, the calibration data is overridden as:
DIGITAL_OUTPUT_CODE = ADC_RAW_CODE * USER_GAIN – USER_OFFSET (7)
To get the raw code, ADC_RAW_CODE, use SetGainAndOffset(128+CHANNEL,1024,0).

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3 SIGNAL QUALITY ENHANCEMENT
3.1 Digital Baseline Stabilizer
The Digital Baseline Stabilizer, DBS, is designed for pulse data measurement where high accuracy rel-
ative a known baseline is required. The key features of DBS are:
• Tracks and compensates for baseline variations from, for example, temperature and aging.
• Suppresses pattern noise1 to 22 bits precision.
• Automatically locks the baseline to a user defined-value.
Note that DBS is off at power up. DBS has to be activated by the user’s application software. The time
when DBS is activated is important. To get a good initial estimate, DBS should be activated when there
is very little signal energy present at the input. If there is too much signal power in the initial estimate,
the convergence of DBS is slowed down.
Note that DBS is defined for systems with a baseline and distinct short pulses. DBS is not intended for
sinusoidal type of signals. For sinusoidal types of signals use ADX, Section 3.2.
3.2 Interleaving correction ADX
The Interleaving correction ADX is available on the 5 GSPS, which is internally interleaved, and on the
interleaved single channel 10 GSPS version of ADQ7.
The ADX automatically corrects for interleaving mismatch in gain, offset, and timing in the ADC cores.
The ADX also compensates for variation over frequency.
At start-up, ADX is loaded with factory calibrated settings but the correction is by-passed. Control ADX
by the commands SetInterleavingIPEstimationMode and SetInterleavingIPBypassMode.
Note that DBS has to be switched off if ADX is used.
Note that ADX is intended for systems with high energy in concentrated frequency bands, like radio
channels.
1. Pattern noise is systematic errors that may arise from the actual design of the ADC IC or the board design.

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4TRIGGER
4.1 Trigger block diagram
The digitizer can be triggered in various ways with a number of different internal and external trigger
sources. Selected events in the trigger module can also be output to trigger external equipment. The
selection of trigger source is illustrated in Figure 3.
#DESCRIPTION USER COMMAND REF
a Connectors for external analog input signals. The number of
channel vary on the different models and configurations.
b Each analog input is connected to a level trigger block. SetupLevelTrigger 4.9
c Select on which channel to trigger (when using level trigger). SetupLevelTrigger 4.9
d Internal trigger generator. SetInternalTriggerPeriod 4.10
e A software trigger is available for user control. SWTrig 4.6
f External trigger input from backplane in PXIe or MTCA. 4.8
g External trigger input on front panel connector TRIG. 4.7.1
h External trigger input on front panel connector SYNC. 4.7.2
i Select which type of trigger to activate. SetTriggerMode
j Activate trigger output. SetupTriggerOutput 4.11
k Select which channels to record data from. SetStreamConfig
l Acquisition engine creates a record from streaming data 7
m Records are sent to data FIFO for transfer to the host PC 7
n The trigger blocking function controls the flow of triggers to the
acquisition engine.
SetupTriggerBlocking 4.4
o Note that the trigger output and the external trigger input are
physically the same connector on the front panel: TRIG.
p Frame sync is a function that can group triggers. SetupFrameSync 4.11.2
Figure 3: Trigger source selection and setup illustrated for a 2 channels mode.
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4.2 Position of the trigger in the data
The trigger position relative to the data record is controlled by the parameters pretrigger and trigger
delay.
The pretrigger buffer enables capturing data prior to the trigger event, Figure 4. Use the command Set-
PreTrigSamples to define the pretrigger.
The trigger delay postpone the start of the acquisition of the data record specified number of samples
after the trigger event, Figure 5. Use the command SetTriggerHoldOffSamples to define the trigger
delay.
The timing of the trigger is read from the record header (Section 7.6). The parameters TIME_STAMP
and RECORD_START are explained in Section 4.3.1.
4.3 Timestamp
4.3.1 Timestamp definitions
The timestamp counter enables real-time measurement of a trigger event. It is used for tagging an
event, sorting events in time or comparing timing between events.
The timestamp information consist of three parts, which uniquely defines the timing:
•TIME_STAMP measures the time of the trigger event relative to other trigger events.
•RECORD_START is the time between the trigger event and the start of the record. For a pretrigger,
this is a negative value. When trigger delay is used, this is a positive value.
Figure 4: Pretrigger timing.
Figure 5: Trigger delay timing.
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•SAMPLE_PERIOD is the length of a sample period. The sample period may vary with sample skip
setting and clock frequency of the digitizer.
The TIME_STAMP, RECORD_START, and SAMPLE_PERIOD are measured in the unit
TIME_BASE =25ps. See Example 3 on how to use these parameters. These parameters are available
in the record header, see Section 7.6.1.
The timestamp counter is based on the internal clock of the digitizer. The internal clock is based on the
selected clock reference. The timestamp is thus also related to the clock reference. When the clock ref-
erence is phase-locked to an external source, the timestamp counter is running synchronized with the
external source. On the other hand, if the digitizer is free running, the timestamp counter also free run-
ning. (See Section 5 for all details about the clock system of digitzer.)
The timestamp counter measures the time from a reference time point to the trigger event. The refer-
ence time point is when the counter is started or reset. See Section 4.3.2 for information on how to
reset the timestamp counter.
Example 3: Assume an ADQ7DC sampling with a clock frequency at 5 GSPS. The pretrigger is set to
80 samples and the external trigger is used. The following parameters are returned:
TIME_STAMP = 5005
RECORD_START = –645
SAMPLE_PERIOD = 8
TIME_BASE = 25 ps
The time for the trigger was then
TRIGGER_TIME = TIME_STAMP * TIME_BASE = 125125 ps = 125.125 ns
The time for the first sample in the record is
RECORD_TIME = (TIME_STAMP + RECORD_START) * TIME_BASE = 109.000 ps = 109 ns
The time between two samples are
SAMPLE_TIME = SAMPLE_PERIOD * TIME_BASE = 200 ps
The time from the record start to the trigger is
RECORD_START * TIME_UNIT = –16.125 ns.
The number of samples between the record start and the trigger event is
( TRIGGER_TIME – RECORD_TIME ) / SAMPLE_TIME =
| RECORD_START | / SAMPLE_PERIOD = 80.625 samples
This is the expected 80 samples set in the pretrigger and 5/8 sample in subsample precision in the
external trigger.
4.3.2 Timestamp reset
When powering up a system with many boards, the timestamp counter in each board will start. But the
counters start at different times in different physical digitizers. There are four methods for resetting the
timestamp and get a common time reference in all the digitizers in the system:
1. The timestamp counter is reset at power-up. This methods does not, however, have absolute preci-
sion, since the timing of the power up is not defined. In a multi-board system, the timestamp will dif-
fer between the boards.
2. With a software reference reset the user has full control of the reset procedure. A reference time
point is created in the users application, which is used for aligning time-stamps in different units.
After power-up the user runs a custom timestamp reset sequence including:
• Apply a reference signal to all boards.
• Trigger a record on the reference signal.
• Read the time-stamps from the records and call this reference; TIME_STAMP_REFERENCE.

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• Start the experiment and subtract the timing reference from each record as
TIME_STAMP = TIME_STAMP_OF_RECORD – TIME_STAMP_REFERENCE.
3. The third method is to apply an external trigger to reset the timestamp reset, Figure 6. This method
has the possibility to synchronize several boards to full precision of the external trigger. See Sec-
tion 4.4. The sequence of operation is:
•DisarmTimestampSync
•SetupTimestampSync
•ArmTimestampSync
The number of reset pulses are counted and the information is stored in the record header, Section
7.6. However, if there are no triggers accepted, there will be no record headers available. To verify
that there is activity going on, the number of reset pulses can also be read from a register via
GetTriggerBlockingGateCount.
4. The fourth method is to reset the timestamp with the sync signal, Figure 6. The difference between
using the external trigger and the sync is that the external trigger has the a sample resolution while
the sync timing resolution is controlled by the Data Clock in the FPGA. Note that the backplane trig-
gers in –PXIe and –MTCA formats work in the same way as the sync signal.
#DESCRIPTION USER COMMAND REF
a External trigger input signal on front panel connector. 4.7
b External sync input signal on front panel connector. 4.7
c Other available sources (see SetTriggerMode for a list) 4.7
d Select source for reseting timestamp. SetupTimestampSync
DisarmTimeStampSync
ArmTimeStampSync
4.3.2
e Timestamp counter value is reset at power-up of the digitizer. 4.3.2
f Reset the timestamp counter on each pulse of the selected source.
Timestamp is then measuring time relative the previous reset signal.
4.3.2
g4.3.2
h Reset the timestamp counter only on the first pulse of the selected
signal. The external signal is then a systems synchronization signal.
4.3.2
i The number of times the time stamp has been reset can be read from
a register.
GetTriggerBlockingGate
Count
4.3.2
Figure 6: Timestamp reset from external trigger.
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4.4 Blocking triggers for synchronization
4.4.1 Function overview
In order to synchronize the acquisition to external equipment or to other ADQ digitizers, there is a
mechanism for controlling the flow of triggers. The trigger blocking function allows the user to select
when to activate incoming triggers, Figure 7. The basic function of this block is to use the SYNC signal
to frame the trigger signals; for each period of the blocking function, a set of triggers are allowed and
and framed by the blocking event. This creates groups of triggers that belong together. The modes of
operation for trigger blocking are shown in Figure 7 (j, k, l).
To avoid that the boards start to produce a large amount of records out of sync, all trigger events can
be blocked until the triggers are released by a separate shared signal, Figure 7 (d). By combining the
trigger blocking and the timestamp reset, the timestamp is aligned to the start of the acquisition. The
trigger blocker source can be most available trigger sources, Figure 7 (a, b, c).
Note the order of the commands for activating triggers and trigger blockers, Figure 7 (e, g, h, i).
Figure 8 illustrates how the triggers are accepted or rejected in the window mode.
#DESCRIPTION USER COMMAND REF
a External trigger input signal on front panel connector. 4.7
b External sync input signal on front panel connector. 4.7
c Other available sources (see SetTriggerMode for a list).
d Select source for blocking triggers. SetupTriggerBlocking 4.4
e Before activating the trigger blocking any selected trigger may pass. SetupTriggerBlocking
f This signal is ignored as the trigger blocker is not armed
g Select trigger source SetTriggerMode
h Start receiving triggers. Note that triggers are still blocked. ArmTrigger
i The unblocking of triggers is armed and can be activated by (d). ArmTriggerBlocking
j Triggers are blocked until the first accepted blocker signal. SetupTriggerBlocking 4.4
k The trigger blocker can also be set up with a window function where
triggers are accepted or rejected during a user-defined window.
SetupTriggerBlocking 4.4.1
l The trigger blocker can also be set up as a gate where triggers are
accepted during a gated time set by signal (d).
SetupTriggerBlocking 4.4.1
Figure 7: Blocking and gating of triggers.
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4.4.2 Block triggers once
The mode for blocking triggers once is illustrated in Figure 7 (j). This mode is used for starting the oper-
ation simultaneously in several units. The first time the trigger blocking signal is applied, the triggers are
allowed through. Here is the motivation for this mode:
There is no way to broadcast a software command to several units. When setting up acquisition in sev-
eral units, they will therefore be activated at different times. By using the trigger blocker, an electrical
signal to all units can activate them simultaneously. The trigger blocking signal can be external or it can
be generated internally using the bussed connections proposed in Figure 13.
4.4.3 Windowing triggers
The window mode for blocking triggers is illustrated in Figure 7 (k). The edge of the trigger blocking sig-
nal is activating a window of user-defined length which allows triggers through. There is also a mode
where triggers are blocked during the window.
The window mode can be used for two-dimensional triggering where, for example, the trigger signal is a
point trigger and a sync signal is a line trigger.
4.4.4 Gating and windowing triggers
The gate mode for blocking triggers is illustrated in Figure 7 (l). The length of the window where trig-
gers are accepted is equal to the length of the trigger blocking signal.
4.4.5 Programming sequence for using trigger blocking
The order of commands is important when programming the trigger blocking. This is because the ADQ
digitizer interact with other external equipment. This external equipment is synchronized to the digitizer
through the setup procedure.
The setup of the functions has to be aligned with the expected operation. For example, by asserting the
trigger blocking through the SetupTriggerBlocking command before setting up the acquisition, no trig-
gers are let through before the digitizer is ready.
#DESCRIPTION USER COMMAND REF
a The trigger blocker in window or gate mode allows triggers during a
certain period.
SetupTriggerBlocking 4.4.1
b Example of rejected triggers outside the window.
c Trigger within the window is accepted and a data record is recorded.
Note that the pretrigger starts before the window.
d Trigger within the window is accepted and a data record is recorded.
Note that the record extends after the window.
e Several triggers within the same window.
Figure 8: Trigger blocker examples.
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The function on the digitizer has to be activated (armed) in reverse order compared to the data flow.
This means that one stage is set up to be prepared to receive data before the preceding stage is set up
to generate data. This is especially important in streaming applications where the DRAM FIFO may
overflow if the triggering is activated before the read-out to the host PC has started.
4.5 Trigger jitter
4.5.1 Trigger jitter definitions
The triggering operation is subject to two different types of jitter, Figure 9.
1. At the trigger input is a Gaussian distributed jitter which affects the timing of the incoming trigger
signal edge. This jitter is called excess jitter and is caused by noise in the input stage. The RMS
value of this excess jitter is 25 ps.
2. The actual sampling process causes a timing uncertainty. Since the trigger is sampled with the trig-
ger clock, the time points for reading the trigger are discrete. The difference between the incoming
physical trigger signal and the digital representation of the trigger is a stochastic variable with a
rectangular distribution. The RMS value of such a process is TRIGGER_CLOCK_PERIOD/sqrt(12).
The highest resolution is achieved with an external trigger connected to the TRIG connector.
ADQ7DC has a trigger clock at 20 GSPS, TRIGGER_CLOCK_PERIOD of 50 ps and a trigger jitter of
14 ps RMS (theoretical value), Section 4.5.4.
See Table 3 for time resolution all the external trigger sources.
4.5.2 Asynchronous triggering
If the trigger signal is not phase-locked to the reference clock it is called asynchronous. This trigger
does not have a well-determined relation to the sampling clock and will appear at various positions
within the sampling period. The time resolution of an asynchronous trigger connected to the TRIG input
is set by the Trigger Clock (20 GHz). The time resolution for other triggers is determined by the Data
Clock (312.5 MHz).
The asynchronous trigger will be exposed to both trigger sources from Section 4.5.1. These indepen-
dent stochastic processes are added to 28 ps. See Table 3 for time resolution of all the external trigger
sources.
There are some advantages with the asynchronous trigger:
• Any pattern noise will be reduced in repeated measurements.
• The trigger resolution of 50 ps can be used for accurate timing calculations. The TIME_STAMP con-
tains the information about the trigger time. See Section 4.5.4.
Figure 9: Sources of jitter on the trigger signal.
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4.5.3 Synchronous trigger
A synchronous trigger is phase locked to the clock of the digitizer. The trigger source needs access to
the clock reference of the digitizer. There are three ways to achieve this synchronization:
1. Output the internal clock reference of the ADQ and send it to the trigger source, Section 5.8.
2. Use the clock reference of the trigger source as clock reference for the ADQ, Section 5.5.
3. Use the internal trigger of the ADQ and output it to trigger the external equipment, Section 4.10.
When the trigger is phase-locked to the clock reference the timing is comparable to a digital signal
which defines setup and hold time.
4.5.4 Extended trigger resolution
The basic sampling process maps the trigger to the sampling rate of the digitizer. There is also addi-
tional trigger time information available; Extended trigger resolution, Figure 10.
The Trigger Clock is operating at 20 GHz. This means that the time resolution of the trigger input TRIG
is reduced to 50 ps.
Note: The extended trigger resolution is available on triggers connected to TRIG only.
The extended trigger information is included in the timestamp information, Section 4.3.
The position of the first sample is rounded up from the trigger position. The parameter RECORD_START
tells where the trigger was. Referring to Figure 10, the RECORD_START parameter can have values in
the range –75 ns up to +100 ns. A positive value means that the first sample is after the trigger. The
given range is without pretrigger or trigger delay. With pretrigger or trigger delay, the RECORD_START
will have a larger (absolute) value.
4.6 Software trigger
The software trigger is a user command that triggers the ADQ. This is for direct user control of the
acquisition and is useful for looking at continuous signals where the timing of the trigger is not critical.
The software trigger is sent through several layers of software and the time when it arrives to the digi-
tizer cannot be predicted. However, the time when it actually arrived can be read from the time stamp in
the record header, Section 4.3.
The software trigger may also be used for time-out function. This is a way to discover faults in the
setup. When the device do not trigger for some reason within a certain time frame, a software com-
mand sequence may be sent and the data can be analyzed to find out what is wrong, Example 4.
Example 4: A time-out function using software trigger can be implemented like this:
1. Time-out occurs
Figure 10: Extended trigger resolution timing for ADQ7 at 5 GSPS.
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19-2233 PC2
2019-02-01 20(50)
ADQ7DC Manual
16-1796 PC2 2019-02-01
20(50)
2. DisArmTrigger
3. SetTriggerMode(“software trigger”)
4. ArmTrigger
5. SWTrig
6. Read data and analyze the situation
4.7 External Trigger Inputs
An external trigger is a dedicated signal on a dedicated input to the ADQ. There are several inputs for
external trigger, Table 3.
4.7.1 External trigger TRIG front panel connector
The block diagram for the TRIG is shown in Figure 11 and related parameters are listed in Table 3. The
user can control the external trigger function for adapting it to the system in the following ways:
• The input impedance can be set in 50  (default) or high impedance mode, see Section 4.7.3.
• Configure the threshold level.
• Set the trigger edge to rising or falling to adjust to the polarity of the trigger signal.
CONNECTOR DESCRIPTION TIME
RESOLUTION
TOTAL
JITTER
IMPEDANCE TRIG
LEVEL
REF
TRIG External trigger on
front panel.
50 ps 28 ps 50  / 500 SW contr. 4.7.1
SYNC Sync signal on front
panel.
3.2 ns 0.9 ns 50  / 500 SW contr. 4.7.3
STARB Backplane trigger in
PXIe systems.
Requires trigger timing
card.
3.2 ns 0.9 ns PXIe standard PXIe
standard
4.8.1
MLVDS Backplane trigger in
MVLDS systems.
3.2 ns 0.9 ns MLVDS.4
standard
MLVDS.4
standard
4.8.2
Table 3: External trigger inputs.
#DESCRIPTION USER COMMAND REF
a The input is available on an SMA connector on the front panel.
b The input impedance can be set as 50  (default) or high
impedance 500 .
SetTriggerInputImpedance 4.7.3
c The trigger threshold is 0.5 V (default) and user-controlled. SetExtTrigThreshold
d High speed comparator.
e Select rising or falling edge. SetExternTrigEdge
Figure 11: External trigger on front panel.
+,
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