TENX TECHNOLOGY TM57PE10 User manual

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8-
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tenx technology inc.
Preliminary Rev 1.4, 2012/01/19
TM57PE10
8-Bit Microcontroller
User Manual
tenx reserves the right to change or discontinue the manual and online documentation to this product herein to improve reliability,
function or design without further notice. tenx does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. tenx products are not designed,
intended, or authorized for use in life support appliances, devices, or systems. If Buyer purchases or uses tenx products for any such
unintended or unauthorized application, Buyer shall indemnify and hold tenx and its officers, employees, subsidiaries, affiliates and
distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that tenx was
negligent regarding the design or manufacture of the part.

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AMENDMENT HISTORY
Version Date Description
V1.0 Oct, 2010 New release
V1.1
Jan, 2011
1. Add more description about /Borrow and /Digit Borrow in
ALU and Working (W) Register section.
2. Add Internal RC mode description and figure in System
Clock Oscillator section.
V1.2 Aug, 2011 Modify the operating voltage.
V1.3 Dec, 2011
1. Add Ordering Information table in the Packaging Information
section.
2. Add 16-pin DIP / SOP in Features section.
3. Add 16-pin Package Dimension.
V1.4 Jan, 2012
1. Add the Electrical Characteristics specs in the Features
section.
2. Add description in Reset section.
4. Merge the information about LVR Circuit Characteristics into
DC Characteristics table.

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Preliminary Rev 1.4, 2012/01/19
CONTENTS
AMENDMENT HISTORY..................................................................................................... 2
FEATURES.......................................................................................................................... 5
BLOCK DIAGRAM .............................................................................................................. 7
PIN ASSIGNMENT .............................................................................................................. 8
PIN DESCRIPTION.............................................................................................................. 9
FUNCTIONAL DESCRIPTION .......................................................................................... 10
1. CPU Core ................................................................................................................... 10
1.1 Clock Scheme and Instruction Cycle................................................................... 10
1.2 Addressing Mode................................................................................................ 10
1.3 Programming Counter (PC) and Stack................................................................ 11
1.4 ALU and Working (W) Register........................................................................... 11
1.5 STATUS Register................................................................................................ 12
1.6 Interrupt............................................................................................................... 13
2. Chip Operation Mode.................................................................................................. 14
2.1 Reset................................................................................................................... 14
2.2 System Configuration Register (SYSCFG).......................................................... 15
2.3 PROM Re-use ROM ........................................................................................... 16
2.4 Power-Down Mode.............................................................................................. 16
2.5 Dual System Clock.............................................................................................. 17
2.6 Dual System Clock Modes Transition ................................................................. 18
3. Peripheral Functional Block........................................................................................ 20
3.1 Watchdog (WDT) / Wakeup (WKT) Timer........................................................... 20
3.2 Timer0: 8-bit Timer/Counter with Pre-scale (PSC).............................................. 21
3.3 Timer2: 15-bit Timer............................................................................................ 22
3.4 PWM0: 8-bit PWM............................................................................................... 22
3.5 PWM1: 8-bit PWM............................................................................................... 24
3.6 Analog Comparator............................................................................................. 25
3.7 System Clock Oscillator ...................................................................................... 26
4. I/O Port....................................................................................................................... 27
4.1 PA0-2.................................................................................................................. 27
4.2 PA3-6, PB0-7...................................................................................................... 28
4.3 PA7..................................................................................................................... 28
MEMORY MAP.................................................................................................................. 29
F-Plane........................................................................................................................... 29
R-Plane........................................................................................................................... 31
INSTRUCTION SET........................................................................................................... 33
ELECTRICAL CHARACTERISTICS ................................................................................. 45

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Preliminary Rev 1.4, 2012/01/19
1. Absolute Maximum Ratings........................................................................................ 45
2. DC Characteristics...................................................................................................... 46
3. Clock Timing............................................................................................................... 48
4. Reset Timing Characteristics...................................................................................... 48
6. Characteristic Graphs................................................................................................. 48
PACKAGING INFORMATION........................................................................................... 51
14-DIP Package Dimension............................................................................................ 52
14-SOP Package Dimension.......................................................................................... 52
16-DIP Package Dimension............................................................................................ 53
16-SOP Package Dimension.......................................................................................... 54
18-DIP Package Dimension............................................................................................ 55
18-SOP Package Dimension.......................................................................................... 55

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FEATURES
1. ROM: 1K x 14 bits OTP or 512 x 14 bits TTP™ (Two Time Programmable ROM)
2. RAM: 48 x 8 bits
3. STACK: 5 Levels
4. I/O ports: Two Bit programmable I/O ports (Max. 16 pins)
5. Two Independent Timers
8-bit timer0 with divided by 1~256 pre-scale option, counter function, Stop counting
15-bit timer2 with 4 interrupt interval option
Timer2 is used to idle mode wake-up timer or one simple 15-bit time base
6. 8-bit PWM0 with prescale/period-adjustment/buffer-reload/clear and hold function
7. 8-bit PWM1 is a simple fixed frequency and duty cycle variable PWM generator
8. One analog voltage comparator
9. Min. Operating Voltage (power on) and Speed: VDD=1.5V, @4 MHz
10. PA1~PA6, PB1~PB6 individual pin low level wake up
11. Oscillation Sources
Fast Clock:
- FXT (Fast Crystal): 1 MHz~24 MHz
- FIRC (Fast Internal RC): 4/8 MHz
- XRC (External R, External C): 10 KHz~3 MHz
Slow Clock:
- SXT (Slow Crystal): 32768 Hz
- XRC (External R, External C): 10 KHz~3 MHz
- SIRC (Slow Internal RC): 151 KHz/37 KHz/9.4 KHz/2.4 KHz, @5V; 115 KHz/29 KHz/7.2 KHz/1.9
KHz, @3V
12. Power Saving Operation Mode
Fast Mode: Slow Clock can be disabled or enabled
Slow Mode: Fast Clock stops, CPU is running
Idle Mode: Slow Clock is running, CPU stops, Timer2 is running
Stop Mode: All Clocks stop, Wake-up Timer is disabled or enabled
13. Dual System Clock
FIRC + SIRC
FIRC + SXT
FIRC + XRC
FXT + SIRC
XRC + SIRC

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14. Reset
Power On Reset
Watchdog Reset
Low Voltage Reset
External pin Reset
15. 2-Level Low Voltage Reset: 1.5V/2.3V (Can be disabled)
16. Operation Voltage: Low Voltage Reset Level to 5.5V
- fosc = 4 MHz, 1.7V ~ 5.5V
- fosc = 8 MHz, 1.9V ~ 5.5V
- fosc = 12 MHz, 2.1V ~ 5.5V
- fosc = 16 MHz, 2.3V ~ 5.5V
17. Interrupt
Three External Interrupt pins:
- Two pins are falling edge triggered
- One pin is rising or falling edge triggered
Timer0, Timer2, Wake-up Timer Interrupt
PWM0, CMP interrupt
18. Watchdog Timer
Clocked by built-in RC oscillator with 4 adjustable Reset/Interrupt Time
(108 ms/56 ms/28 ms/14 ms, @5V; 138 ms/72 ms/36 ms/18 ms, @3V)
Watchdog timer can be disabled/enabled in STOP mode
19. I/O Ports
CMOS Output
Pseudo-Open-Drain or Open-Drain Output
Schmitt Trigger Input with/without pull-up resistor
20. Instruction set: 36 Instructions
21. Package Types: 14-DIP/SOP, 16-DIP/SOP, 18-DIP/SOP

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BLOCK DIAGRAM
1Kx14 OTP
ROM
Instruction
Register
Instruction
Decoder
W
ALU
Program
Counter
STATUS
F-Plane
Register
File
5-LEVEL
STACK
FXT/SXT
OSC
FIRC
CLOCK GEN.
& TIMING
CTRL RESET
T0I/PA2
WDT
Timeout
XRC
MUX
8
R-Plane
Register
File
MUX
7
FSR
8Data Bus
F-plane
Indirect
Address
TIMER0
TIMER0
PRESCALER
TIMER2
CPUCLK / 128
Slow Clock
WDT
WKT
PB0
PB1
PB2
PB3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
8-bit
PWM0
PB4
PB5
PB6
PB7
8-bit
PWM1 Analog
CMP

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PIN ASSIGNMENT
PWM0/PA1
1
U
14
PA0/INT0
T0I/PA2
2
13
PA4/Xin/Xrc
VPP/nReset/INT2/PA7
3
12
PA3/Xout/CLKO
VSS
4
TM57PE10
11
VDD
INT1/PB0
5 10
PB5/PWM1
IN0-/PB1
6
9
PB4/CMPO
IN1-/PB2
7
8
PB3/IN+
PWM0/PA1
1
U
16
PA0/INT0
T0I/PA2
2
15
PA4/Xin/Xrc
VPP/nReset/INT2/PA7
3 14
PA3/Xout/CLKO
VSS
4
13
VDD
INT1/PB0
5
TM57PE10
12
PB7
IN0-/PB1
6
11
PB6
IN1-/PB2
7
10
PB5/PWM1
IN+/PB3
8 9
PB4/CMPO
PA5
1
U
18
PA6
PWM0/PA1
2
17
PA0/INT0
T0I/PA2
3
16
PA4/Xin/Xrc
VPP/nReset/INT2/PA7
4
15
PA3/Xout/CLKO
VSS
5
TM57PE10
14
VDD
INT1/PB0
6
13
PB7
IN0-/PB1
7
12
PB6
IN1-/PB2
8
11
PB5/PWM1
IN+/PB3
9
10
PB4/CMPO

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PIN DESCRIPTION
Name
In/Out
Pin Description
PA0–PA2 I/O
Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or
“pseudo-open-drain” output. Pull-up resistors are assignable by software.
PA3–PA6 I/O
Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or
open-drain output. Pull-up resistors are assignable by software.
PA7
I
Schmitt-trigger input
PB0–PB7 I/O
Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or
open-drain output. Pull-up resistors are assignable by software.
nRESET I External active low reset
Xin, Xout – Crystal/Resonator oscillator connection for system clock
Xrc
–
External RC oscillator connection for system clock
CLKO
O
CPU Instruction clock output for external/internal RC mode
VDD, VSS
P
Power Voltage input pin and ground
VPP
I
PROM programming high voltage input
INT0–INT2
I
External interrupt input
PWM0–PWM1
O
PWM output
IN0-, IN1-, IN+
I
Comparator voltage input
CMPO
O
Comparator output
T0I
I
Clock input to Timer0

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FUNCTIONAL DESCRIPTION
1. CPU Core
1.1 Clock Scheme and Instruction Cycle
The system clock is internally divided by two to generate Q1 state and Q2 state for each instruction
cycle. The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program
ROM and latched into the instruction register in Q2. It is then decoded and executed during the following
Q1-Q2 cycle. Branch instructions take two cycles since the fetch instruction is ‘flushed’ from the pipeline,
while the new instruction is being fetched and then executed.
Fetch Execute
Branch
Instruction
Instruction
Pipeline
Flow Fetch Execute
Fetch Flush
Fetch Execute
Instruction
Cycle
FOSC
Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2
1.2 Addressing Mode
There are two Data Memory Planes in CPU, R-Plane and F-Plane. The registers in R-Plane are write-
only. The “MOVWR” instruction copy the W-register’s content to R-Plane registers by direct addressing
mode. The lower locations of F-Plane are reserved for the SFR. Above the SFR is General Purpose
Data Memory, implemented as static RAM. F-Plane can be addressed directly or indirectly. Indirect
Addressing is made by INDF register. The INDF register is not a physical register. Addressing INDF
actually addresses the register whose address is contained in the FSR register (FSR is a pointer). The
first half of F-Plane is bit-addressable, while the second half of F-Plane is not bit-addressable.
R-Plane
F-Plane
00
00
SFR
Bit Addressable
MOVWR Instruction
Write Only
1F
20
SRAM
Bit Addressable
3F
3F
40
SRAM
4F

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1.3 Programming Counter (PC) and Stack
The Programming Counter is 10-bit wide capable of addressing a 1K x 14 OTP ROM. As a program
instruction is executed, the PC will contain the address of the next program instruction to be executed.
The PC value is normally increased by one except the followings. The Reset Vector (000h) and the
Interrupt Vector (001h) are provided for PC initialization and Interrupt. For CALL/GOTO instructions, PC
loads 10 bits address from instruction word. For RET/RETI/RETLW instructions, PC retrieves its content
from the top level STACK. For the other instructions updating PC [7:0], the PC [9:8] keeps unchanged.
The STACK is 10-bit wide and 5-level in depth. The CALL instruction and hardware interrupt will push
STACK level in order. While the RET/RETI/RETLW instruction pops the STACK level in order.
1.4 ALU and Working (W) Register
The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. In two-operand
instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for
ALU operations. The other operand is either a file register or an immediate constant. In single operand
instructions, the operand is either W register or a file register. Depending on the instruction executed,
the ALU may affect the values of Carry (C), Digit Carry (DC), and Zero (Z) Flags in the STATUS register.
The C and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction.
Note: /Borrow represents inverted of Borrow register.
/Digit Borrow represents inverted of Digit Borrow register.

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1.5 STATUS Register
This register contains the arithmetic status of ALU and the reset status. The STATUS register can be
the destination for any instruction, as with any other register. If the STATUS register is the destination
for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits
are set or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and
MOVWF instructions are used to alter the STATUS register because these instructions do not affect
those bits.
STATUS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Value
–
0
–
0
0
0
0
0
R/W
–
R/W
–
R
R
R/W
R/W
R/W
Bit
Description
7
Not Used
6
General Purpose Bit
5
Not Used
4
TO: Time Out
0: after Power On Reset, LVR Reset, or CLRWDT/SLEEP instruction
1: WDT time out occurs
3
PD: Power Down
0: after Power On Reset, LVR Reset, or CLRWDT instruction
1: after SLEEP instruction
2
Z: Zero Flag
0: the result of a logic operation is not zero
1: the result of a logic operation is zero
1
DC: Decimal Carry Flag or Decimal /Borrow Flag
ADD instruction
SUB instruction
1: a carry from the low nibble bits of the
result occurs
0: no carry
1: no borrow
0: a borrow from the low nibble bits of the
result occurs
0
C: Carry Flag or /Borrow Flag
ADD instruction
SUB instruction
1: a carry occurs from the MSB
0: no carry
1: no borrow
0: a borrow occurs from the MSB

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1.6 Interrupt
The TM57PE10 has 1 level, 1 vector and 8 interrupt sources. Each interrupt source has its own enable
control bit. An interrupt event will set its individual pending flag; no matter its interrupt enable control bit
is 0 or 1. Because TM57PE10 has only 1 vector, there is not an interrupt priority register. The interrupt
priority is determined by F/W.
If the corresponding interrupt enable bit has been set (INTE), it would trigger CPU to service the
interrupt. CPU accepts interrupt in the end of current executed instruction cycle. In the mean while, a
“CALL 001” instruction is inserted to CPU, and i-flag is set to prevent recursive interrupt nesting.
The i-flag is cleared in the instruction after the “RETI” instruction. That is, at least one instruction in main
program is executed before service the pending interrupt. The interrupt event is level triggered. F/W
must clear the interrupt event register while serving the interrupt routine.
Interrupt Pending
Interrupt
Vector
i-Flag
Interrupt
Source
Interrupt
Enable

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2. Chip Operation Mode
2.1 Reset
The TM57PE10 can be RESET in four ways.
－Power-On-Reset
－Low Voltage Reset (LVR)
－External Pin Reset (PA7)
－Watchdog Reset (WDT)
After Power-On-Reset, all system and peripheral control registers are then set to their default hardware
Reset values. The clock source, LVR level and chip operation mode are selected by the SYSCFG
register value. The Low Voltage Reset features static reset when supply voltage is below a threshold
level. There are two threshold levels can be selected. The LVR’s operation mode is defined by the
SYSCFG register.
There are two voltage selections for the LVR threshold level, one is higher level which is suitable for
application with VDD is more than 3.3V, while another one is suitable for application with VDD is less than
3.3V. See the following LVR Selection Table; user must also consider the lowest operating voltage of
operating frequency.
LVR Selection Table:
LVR Threshold Level Consider the operating voltage to choose LVR
LVR2.3 5.5V > VDD > 3.3V
LVR1.5 VDD is wide voltage range
The External Pin Reset and Watchdog Reset can be disabled or enabled by the SYSCFG
register. These two resets also set all the control registers to their default reset value. The
TO/PD flag is not affected by these resets.

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2.2 System Configuration Register (SYSCFG)
The System Configuration Register (SYSCFG) is located at ROM address 3FCh. The SYSCFG
determines the option for initial condition of MCU. It is written by PROM Writer only. User can select
clock source, LVR threshold voltage and chip operation mode by SYSCFG register. The default value of
SYSCFG is 3FFFh. The 13th bit of SYSCFG is code protection selection bit. If this bit is 0, the data in
PROM will be protected, when user reads PROM.
Bit
13~0
Default Value
11111111111111
Bit
Description
13
nPROTECT: Code protection selection
1
No protect
0
Code protection
12
nREUSE: PROM Re-use control
1
Not Re-use
0
Re-use
11-10
LVR: LV Reset Mode
11
LVR threshold is 1.5V, always enable
10
LVR threshold is 1.5V, disable in sleep mode
01
LVR threshold is 2.3V, always enable
00
LVR disable
9-8
CLKS: Fast Clock Source Selection
11
Fast Crystal (1 MHz~24 MHz)
10
Slow Crystal
01
Fast Internal RC (4/8 MHz)
00
External RC
7
XRESETE: External pin Reset Enable
1
Enable External pin Reset
0
Disable External pin Reset to use as input pin
6
WDTE: WDT Reset Enable
1
Enable WDT Reset
0
Disable WDT Reset
5
FIRC:1:FIRCCLK=8 MHz, 0: FIRCCLK=4 MHz
4-0
FIRCF: Fast Internal RC Frequency adjustment control

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2.3 PROM Re-use ROM
The PROM of this device is 1K words. For some F/W program, the program size could be less than 512
words. To fully utilize the PROM, the device allows users to reuse the PROM. This feature is named as
Two Time Programmable (TTP) ROM. While the first half of PROM is occupied by a useless program
code and the second half of the PROM remains blank, users can re-write the PROM with the updated
program code into the second half of the PROM. In the Re-use mode, the Reset Vector and Interrupt
Vector are re-allocated at the beginning of the PROM’s second half by the Assembly Compiler. Users
simply choose the “REUSE” option in the ICE tool interface, and then the Compiler will move the object
code to proper location. That is, the user’s program still has reset vector at address 000h, but the
compiled object code has reset vector at 200h. In the SYSCFG, if nPROTECT=0 and nREUSE=1, the
Code protection area is first half of PROM. This allows the Writer tool to write then verify the Code
during the Re-use Code programming. After the Re-use Code being written into the PROM’s second
half, user should write “nREUSE” control bit to “0”. In the mean while, the Code protection area
becomes the whole PROM except the Reserved Area.
PROM, nREUSE=1
PROM, nREUSE=0
000
Reset Vector
000
001
Interrupt Vector
001
Code
Useless
Protect
Code
Area
User
Code
1FF
Code
1FF
Protect
200
200
Reset Vector
Area
201
201
Interrupt Vector
User
Code
3FC
SYSCFG
3FC
SYSCFG
3FD
Manufacturer
3FD
Manufacturer
3FE
Reserved
3FE
Reserved
3FF
Area
3FF
Area
2.4 Power-Down Mode
The Power-down mode is activated by SLEEP instruction. During the Power-down mode, the system
clock and peripherals stop to minimize power consumption, while the WDT/WKT Timer is working or not
depends on F/W setting. The Power down mode can be terminated by Reset, or enabled Interrupts
(External pins and WKT interrupt) or PA1-6 and PB1-6 pins low level wake up.

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2.5 Dual System Clock
TM57PE10 is designed with dual-clock system. There are five kinds of clock source, FXT (Fast Crystal)
Clock, SXT (Slow Crystal) Clock, XRC (External RC) Clock, SIRC (Slow Internal RC) Clock and FIRC
(Fast Internal RC). Each clock source can be applied to CPU kernel as system clock. When in idle mode,
only slow clock can be configured to keep oscillating to provide clock source to Timer2. Refer to the
Figure as below.
SYSCFG[9:8]
Fast Clock
SUBTYP[1:0]
Slow Clock
Clock
Switch
To CPU
Divide
by 128
Timer2
TM2CLK
1
0
SELSUB
10
XRC
01
SIRC
00
SXT
00
XRC
01
FIRC
10
SXT
11
FXT
Fast Mode:
After power on or reset, TM57PE10 enters fast mode. In fast mode, TM57PE10 can select FXT, XRC or
FIRC as its CPU clock by SYSCFG bit9 and bit8 setting. Besides, firmware can also enable or disable
the slow clock for the Timer2 system operating. In this mode, the program is executed using fast clock
as CPU clock. The Timer0, PWM0, PWM1 blocks are also driven by fast clock. Timer2 can also be
driven by fast clock by setting TM2CLK to “1”.
Slow Mode:
In slow mode, TM57PE10 can select SXT, XRC or SIRC as its CPU clock by R-Plane control register
(SUBTYP). In this mode, the fast clock is stopped and slow clock is enabled for power saving. All
peripheral blocks clock sources are slow clock in the slow mode.
IDLE Mode:
If slow clock is enabled and TM2CLK=0 before executing the SLEEP instruction, the TM57PE10 enters
the “Idle Mode”. In this mode, the slow clock will continue running to provide clock to Timer2 block. CPU
stop fetching code and all blocks are stop except Timer2 related circuits.
Stop Mode:
If slow clock is disabled before executing the SLEEP instruction, every block is turned off and the
TM57PE10 enters the “Stop Mode”. Stop mode is similar to idle mode. The difference is all clock
oscillators either fast or slow is powered-down and no clock is generated.

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2.6 Dual System Clock Modes Transition
TM57PE10 is operated in one of four modes: Fast Mode, Slow Mode, Idle Mode, and Stop Mode.
Modes Transition Diagram:
FAST
SLOW IDLE
STOP
SUBE= 0 or 1
SELSUB=0
STPFCK=0
SUBE=1
SELSUB=1
STPFCK=1
SUBE=1
SELSUB=0 or 1
STPFCK=0 or 1
SUBE=0
SELSUB=0 or 1
STPFCK=0 or 1
SUBE=0
SELSUB=0
STPFCK=0
SUBE=1
SELSUB=1
STPFCK=1
SUBE=1
SUBE=0
SUBE=0
SUBE=1
RESET
Fast Mode transits to Slow Mode:
Fast mode can be chosen by SYSCFG [9:8] when equals to 11 (Fast Crystal), 00 (External RC), or 01
(Fast Internal RC). The following steps are suggested to be executed by order when fast mode transits
to slow mode:
(1) Enable slow clock (SUBE=1)
(2) Switch to slow clock (SELSUB=1)
(3) Stop fast clock (STPFCK=1)
Slow Mode transits to Fast Mode:
Slow mode can be enabled by SUBE bit and SELSUB bit in CLKCTRL register. The following steps are
suggested to be executed by order when slow mode transits to fast mode:
(1) Enable fast clock (STPFCK=0)
(2) Switch to fast clock (SELSUB=0)
(3) Stop slow clock (SUBE=0)
Note: Stop slow clock (SUBE=0) is optional. Slow clock can keep oscillating to provide Timer2 Counter
block in fast mode.

Advance Information
UM-TM57PE10_E
8-
Bit Microcontroller
19
tenx technology inc.
Preliminary Rev 1.4, 2012/01/19
Idle Mode Setting:
The Idle mode can be configured by following setting in order:
(1) Enable slow clock (SUBE=1)
(2) Switch Timer2 clock source to slow clock (TM2CLK=0)
(3) Execute SLEEP instruction
Idle mode can be woken up by XINT, PAWKUP, PBWAKP, Wake-up Timer, and Timer2 interrupt.
Stop Mode Setting:
The Stop mode can be configured by following setting in order:
(1) Stop slow clock (SUBE=0)
(2) Execute SLEEP instruction
Stop mode can be woken up by XINT, PAWKUP, PBWAKP, and Wake-up Timer.
IO setting note in dual clock mode：
Note: In slow clock modes, PA3 and PA4 must be set as input pull-up mode when slow clock selects
SXT or XRC mode. PA3 and PA4 IO setting list is as shown bellow.
Fast Clock
Slow Clock
PAD3
PAE3
nPAPU3
PAD4
PAE4
nPAPU4
1
FIRC
SIRC
※ ※ ※ ※ ※ ※
2
FIRC
SXT
1
0
0
1
0
0
3
FIRC
XRC
※ ※ ※
1
0
0
4
FXT
SIRC
※ ※ ※ ※ ※ ※
5 XRC SIRC ※※※※※※
※：Don’t care

Advance Information
UM-TM57PE10_E
8-
Bit Microcontroller
20
tenx technology inc.
Preliminary Rev 1.4, 2012/01/19
3. Peripheral Functional Block
3.1 Watchdog (WDT) / Wakeup (WKT) Timer
The WDT and WKT share the same internal RC Timer. The overflow period of WDT/WKT can be
selected from 14 ms to 138 ms. The WDT/WKT is cleared by the CLRWDT instruction. If the Watchdog
Reset is enabled (WDTE=1), the WDT generates the chip reset signal, otherwise, the WKT only
generates overflow time out interrupt. The WDT/WKT works in both normal mode and sleep mode.
During sleep mode, user can further choose to enable or disable the WDT/WKT by "WKTIE". If
WKTIE=0 in sleep mode (no matter WDTE is 1 or 0), the internal RC Timer stops for power saving. In
other words, user keeps the WDT/WKT alive in Sleep Mode by setting WKTIE=1. If the WDTE=1 and
WKTIE=0, WDT/WKT timer will be cleared and stopped to power saving in sleep mode. If the WDTE=1
and WKTIE=1, WDT/WKT timer keeps counting in sleep/normal mode. Refer to the following table and
figure.
nRESET
XRSTE
Power On
Reset
Low
Voltage
Detector
WKTIE
4
WDTE
EN
Watchdog
RC-OSC
WDTE
CLR
WDT/WKT
Timer
D Q
RN
WKTIE
“CLRWDT”
Wake Up Timer
Interrupt
Time Out
System
Reset
WKTPSC[1:0]
“PWRDOWN”
SLEEP_ MODE
2
LVR[1:0]
System
Clock
VDD
VDD
EN
Oscillator
SLEEP_ MODE
VDD
2
SLEEP_ MODE
SLEEP_MODE
WDTE
WKTIE
SLEEP_ MODE
If the user program needs the MCU totally shuts down for power conservation in sleep mode, the
following setting of control bits should be followed.
Mode
WDTE
WKTIE
Watchdog RC Oscillator
Normal Mode
0
0
Stop
0
1
Run
1
0
1
1
Sleep Mode
0
0
Stop
0 1 Run
1
0
Stop
1
1
Run