NXP Semiconductors LPC1769 User manual

UM10360
LPC176x/5x User manual
Rev. 3 — 20 December 2013 User manual
Document information
Info Content
Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,
LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM
Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller
Abstract LPC176x/5x user manual

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LPC17xx user manual
Revision history
Rev Date Description
3 20131220 LPC176x/5x user manual
Modifications:
•Part ID for part LPC1763 added.
•Changed title to “LPC176x/5x User manual”.
•Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See
Section 16.13 “ID look-up table RAM”and Section 16.15 “Configuration and search algorithm”.
•Updated Serial Wire Output description (Table 609).
•Clarified burst mode information for ADGINTEN (Table 531 and Table 533).
•Condition CCLK > 18 MHz for USB operation is not applicable for this USB peripheral and was
removed (see Section 4.7.1, Section 11.13, and Section 13.11).
•Description of CAN interrupt request updated. One common CAN interrupt is triggered. See
Section 16.8.3.
•Condition on minimum frequency of CAP input clock added in Section 21.5.1.
•Description of RIMASK register corrected. See Table 433.
•Condition for maximum allowable STCLK frequency added. See Section 23.4.
•Delete statement “All PWM related Match registers are configured for toggle on match.” in
Figure 120.
•Description of INXCNT register updated. See Section 26.6.3.6.
•Reset value of the RTC_AUX register corrected. See Table 507.
•DAC power-down mode removed in Section 30.2.
•Added: The DAC output is disabled in deep-sleep, power-down, or deep power-down modes.
See Table 537.
•Boot loader SRAM use explained. See Section 33.5.
•SYSRESETREQ supported. See Table 659.
•Figure 18 “Ethernet packet fields”corrected.
•Bit description in the SPI test control register corrected. Bit 0 indicates test mode. All other bits
are reserved. See Section 17.7.5 “SPI Test Control Register (SPTCR - 0x4002 0010)”.
•Figure 117 “RI timer block diagram”updated.
2 20100819 LPC176x/5x user manual revision.
Modifications:
•UART0/1/2/3: FIFOLVL register removed.
•ADC: reset value of the ADCTRM register changed to 0xF00 (Table 500).
•Timer0/1/2/3: Description of DMA operation updated.
•USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read)
(Table 184).
•Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46).
•Part LPC1763 added.
•Update register bit description of USBIntStat register in Host and Device mode (Table 155 and
Table 221).
•Motor control PWM: update description of match and limit registers.
•GPIO: update register bit description of the FIOPIN register (Table 73).
•Numerous editorial updates throughout the user manual.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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LPC17xx user manual
1 20100104 LPC176x/5x user manual revision.
Revision history …continued
Rev Date Description

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User manual Rev. 3 — 19 December 2013 4 of 841
1.1 Introduction
The LPC176x/5x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as modernized debug
features and a higher level of support block integration.
High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU
frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The peripheral complement of the LPC176x/5x includes up to 512 kB of flash memory, up
to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either
Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN
channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S
interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder
interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC
with separate battery supply, and up to 70 general purpose I/O pins.
UM10360
Chapter 1: LPC176x/5x Introductory information
Rev. 3 — 19 December 2013 User manual

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Chapter 1: LPC176x/5x Introductory information
1.2 Features
Refer to Section 1.4.1 for details of features on specific part numbers.
•ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory
Protection Unit (MPU) supporting eight regions is included.
•ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
•Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
•Up to 64 kB on-chip SRAM includes:
–Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
–Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.
•Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
•Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.
•Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
•Serial interfaces:
–Ethernet MAC with RMII interface and dedicated DMA controller.
–USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
–Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
–Two-channel CAN controller.
–Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
–SPI controller with synchronous, serial, full duplex communication and
programmable data length. SPI is included as a legacy peripheral and can be used
instead of SSP0.
–Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.

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Chapter 1: LPC176x/5x Introductory information
–I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
•Other peripherals:
–70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
configurable pull-up/down resistors, open drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access, and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
–12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
–10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
–Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
–One motor control PWM with support for three-phase motor control.
–Quadrature encoder interface that can monitor one external quadrature encoder.
–One standard PWM/timer block with external count input.
–Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
–Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
–Cortex-M3 system tick timer, including an external clock input option.
–Repetitive interrupt timer provides programmable and repeating timed interrupts.
•Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
•Emulation trace module supports real-time trace.
•Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
•Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
•Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
•Non-maskable Interrupt (NMI) input.
•Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.
•The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.

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Chapter 1: LPC176x/5x Introductory information
•Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
•Each peripheral has its own clock divider for further power savings.
•Brownout detect with separate threshold for interrupt and forced reset.
•On-chip Power-On Reset (POR).
•On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
•4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.
•An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
•A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.
•Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
•Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm)
packages.
1.3 Applications
•eMetering
•Lighting
•Industrial networking
•Alarm systems
•White goods
•Motor control

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Chapter 1: LPC176x/5x Introductory information
1.4 Ordering information
1.4.1 Part options summary
Table 1. Ordering information
Type number Package
Name Description Version
LPC1769FBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FBD100
LPC1767FBD100
LPC1766FBD100
LPC1765FBD100
LPC1764FBD100
LPC1763FBD100
LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm SOT926-1
LPC1759FBD80
LQFP80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC1758FBD80
LPC1756FBD80
LPC1754FBD80
LPC1752FBD80
LPC1751FBD80
Table 2. Ordering options for LPC176x/5x parts
Type number Max. CPU
speed Flash Total SRAM Ethernet USB CAN I2SDAC Package
LPC1769FBD100 120 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1768FBD100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1768FET100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1767FBD100 100 MHz 512 kB 64 kB yes no no yes yes 100 pin
LPC1766FBD100 100 MHz 256 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1765FBD100 100 MHz 256 kB 64 kB no Device/Host/OTG 2 yes yes 100 pin
LPC1764FBD100 100 MHz 128 kB 32 kB yes Device 2 no no 100 pin
LPC1763FBD100 100 MHz 256 kB 64 kB no no no yes yes 100 pin
LPC1759FBD80 120 MHz 512 kB 64 kB no Device/Host/OTG 2 yes yes 80 pin
LPC1758FBD80 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 80 pin
LPC1756FBD80 100 MHz 256 kB 32 kB no Device/Host/OTG 2 yes yes 80 pin
LPC1754FBD80 100 MHz 128 kB 32 kB no Device/Host/OTG 1 no yes 80 pin
LPC1752FBD80 100 MHz 64 kB 16 kB no Device 1 no no 80 pin
LPC1751FBD80 100 MHz 32 kB 8 kB no Device 1 no no 80 pin

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Chapter 1: LPC176x/5x Introductory information
1.5 Simplified block diagram
Fig 1. LPC1768 simplified block diagram
AHB to
APB bridge AHB to APB bridge
APB slave group 1APB slave group 0
Note: shaded peripheral blocks
support General Purpose DMA
RTC Power Domain
Multilayer AHB Matrix
I2C2
I2S
UARTs 2 & 3
SSP0
Real Time Clock
20 bytes of backup
registers
SSP1
UARTs 0 & 1
CAN 1 & 2
I2C 0 & 1
SPI0
Capture/Compare
Timers 0 & 1
Watchdog Timer
PWM1
12-bit ADC
Pin Connect Block
GPIO Interrupt Ctl
32 kHz
oscillator
DMA
controller
Clock Generation,
Power Control,
Brownout Detect,
and other
system functions
RST
Xtalin
Xtalout
Clocks
and
Controls
Ethernet
PHY
interface
Ethernet
10/100
MAC
USB
device,
host,
OTG
USB
interface
JTAG
interface
ARM Cortex-M3
Test/Debug Interface
System
bus
D-code
bus
I-code
bus
ROM
8 kB
SRAM
64 kB
Trace
Port
Trace Module
High Speed GPIO
Capture/Compare
Timers 2 & 3
External Interrupts
DAC
System Control
Motor Control PWM
Quadrature Encoder
Repetitive Interrupt
Timer
Flash
512 kB
Flash
Accelerator

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Chapter 1: LPC176x/5x Introductory information
1.6 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC176x/5x uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave
ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller. The APB bus bridges are configured
to buffer writes so that the CPU or DMA controller can write to APB devices without
always waiting for APB write completion.
1.7 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with Wake-up Interrupt
Controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is
appended to this manual.
1.7.1 Cortex-M3 Configuration Options
The LPC176x/5x uses the r2p0 version of the Cortex-M3 CPU, which includes a number
of configurable options, as noted below.
System options:
•The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the
SYSTICK timer.
•The Wake-up Interrupt Controller (WIC) is included. The WIC allows more powerful
options for waking up the CPU from reduced power modes.
•A Memory Protection Unit (MPU) is included.
•A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.