NXP Semiconductors LPC1769 User manual

UM10360
LPC176x/5x User manual
Rev. 3 — 20 December 2013 User manual
Document information
Info Content
Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,
LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM
Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller
Abstract LPC176x/5x user manual

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LPC17xx user manual
Revision history
Rev Date Description
3 20131220 LPC176x/5x user manual
Modifications:
•Part ID for part LPC1763 added.
•Changed title to “LPC176x/5x User manual”.
•Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See
Section 16.13 “ID look-up table RAM”and Section 16.15 “Configuration and search algorithm”.
•Updated Serial Wire Output description (Table 609).
•Clarified burst mode information for ADGINTEN (Table 531 and Table 533).
•Condition CCLK > 18 MHz for USB operation is not applicable for this USB peripheral and was
removed (see Section 4.7.1, Section 11.13, and Section 13.11).
•Description of CAN interrupt request updated. One common CAN interrupt is triggered. See
Section 16.8.3.
•Condition on minimum frequency of CAP input clock added in Section 21.5.1.
•Description of RIMASK register corrected. See Table 433.
•Condition for maximum allowable STCLK frequency added. See Section 23.4.
•Delete statement “All PWM related Match registers are configured for toggle on match.” in
Figure 120.
•Description of INXCNT register updated. See Section 26.6.3.6.
•Reset value of the RTC_AUX register corrected. See Table 507.
•DAC power-down mode removed in Section 30.2.
•Added: The DAC output is disabled in deep-sleep, power-down, or deep power-down modes.
See Table 537.
•Boot loader SRAM use explained. See Section 33.5.
•SYSRESETREQ supported. See Table 659.
•Figure 18 “Ethernet packet fields”corrected.
•Bit description in the SPI test control register corrected. Bit 0 indicates test mode. All other bits
are reserved. See Section 17.7.5 “SPI Test Control Register (SPTCR - 0x4002 0010)”.
•Figure 117 “RI timer block diagram”updated.
2 20100819 LPC176x/5x user manual revision.
Modifications:
•UART0/1/2/3: FIFOLVL register removed.
•ADC: reset value of the ADCTRM register changed to 0xF00 (Table 500).
•Timer0/1/2/3: Description of DMA operation updated.
•USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read)
(Table 184).
•Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46).
•Part LPC1763 added.
•Update register bit description of USBIntStat register in Host and Device mode (Table 155 and
Table 221).
•Motor control PWM: update description of match and limit registers.
•GPIO: update register bit description of the FIOPIN register (Table 73).
•Numerous editorial updates throughout the user manual.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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LPC17xx user manual
1 20100104 LPC176x/5x user manual revision.
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC176x/5x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as modernized debug
features and a higher level of support block integration.
High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU
frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The peripheral complement of the LPC176x/5x includes up to 512 kB of flash memory, up
to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either
Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN
channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S
interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder
interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC
with separate battery supply, and up to 70 general purpose I/O pins.
UM10360
Chapter 1: LPC176x/5x Introductory information
Rev. 3 — 19 December 2013 User manual

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Chapter 1: LPC176x/5x Introductory information
1.2 Features
Refer to Section 1.4.1 for details of features on specific part numbers.
•ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory
Protection Unit (MPU) supporting eight regions is included.
•ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
•Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
•Up to 64 kB on-chip SRAM includes:
–Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
–Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.
•Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
•Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.
•Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
•Serial interfaces:
–Ethernet MAC with RMII interface and dedicated DMA controller.
–USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
–Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
–Two-channel CAN controller.
–Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
–SPI controller with synchronous, serial, full duplex communication and
programmable data length. SPI is included as a legacy peripheral and can be used
instead of SSP0.
–Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.

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Chapter 1: LPC176x/5x Introductory information
–I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
•Other peripherals:
–70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
configurable pull-up/down resistors, open drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access, and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
–12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
–10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
–Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
–One motor control PWM with support for three-phase motor control.
–Quadrature encoder interface that can monitor one external quadrature encoder.
–One standard PWM/timer block with external count input.
–Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
–Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
–Cortex-M3 system tick timer, including an external clock input option.
–Repetitive interrupt timer provides programmable and repeating timed interrupts.
•Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
•Emulation trace module supports real-time trace.
•Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
•Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
•Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
•Non-maskable Interrupt (NMI) input.
•Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.
•The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.

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Chapter 1: LPC176x/5x Introductory information
•Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
•Each peripheral has its own clock divider for further power savings.
•Brownout detect with separate threshold for interrupt and forced reset.
•On-chip Power-On Reset (POR).
•On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
•4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.
•An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
•A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.
•Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
•Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm)
packages.
1.3 Applications
•eMetering
•Lighting
•Industrial networking
•Alarm systems
•White goods
•Motor control

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Chapter 1: LPC176x/5x Introductory information
1.4 Ordering information
1.4.1 Part options summary
Table 1. Ordering information
Type number Package
Name Description Version
LPC1769FBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FBD100
LPC1767FBD100
LPC1766FBD100
LPC1765FBD100
LPC1764FBD100
LPC1763FBD100
LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm SOT926-1
LPC1759FBD80
LQFP80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC1758FBD80
LPC1756FBD80
LPC1754FBD80
LPC1752FBD80
LPC1751FBD80
Table 2. Ordering options for LPC176x/5x parts
Type number Max. CPU
speed Flash Total SRAM Ethernet USB CAN I2SDAC Package
LPC1769FBD100 120 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1768FBD100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1768FET100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1767FBD100 100 MHz 512 kB 64 kB yes no no yes yes 100 pin
LPC1766FBD100 100 MHz 256 kB 64 kB yes Device/Host/OTG 2 yes yes 100 pin
LPC1765FBD100 100 MHz 256 kB 64 kB no Device/Host/OTG 2 yes yes 100 pin
LPC1764FBD100 100 MHz 128 kB 32 kB yes Device 2 no no 100 pin
LPC1763FBD100 100 MHz 256 kB 64 kB no no no yes yes 100 pin
LPC1759FBD80 120 MHz 512 kB 64 kB no Device/Host/OTG 2 yes yes 80 pin
LPC1758FBD80 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes yes 80 pin
LPC1756FBD80 100 MHz 256 kB 32 kB no Device/Host/OTG 2 yes yes 80 pin
LPC1754FBD80 100 MHz 128 kB 32 kB no Device/Host/OTG 1 no yes 80 pin
LPC1752FBD80 100 MHz 64 kB 16 kB no Device 1 no no 80 pin
LPC1751FBD80 100 MHz 32 kB 8 kB no Device 1 no no 80 pin

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Chapter 1: LPC176x/5x Introductory information
1.5 Simplified block diagram
Fig 1. LPC1768 simplified block diagram
AHB to
APB bridge AHB to APB bridge
APB slave group 1APB slave group 0
Note: shaded peripheral blocks
support General Purpose DMA
RTC Power Domain
Multilayer AHB Matrix
I2C2
I2S
UARTs 2 & 3
SSP0
Real Time Clock
20 bytes of backup
registers
SSP1
UARTs 0 & 1
CAN 1 & 2
I2C 0 & 1
SPI0
Capture/Compare
Timers 0 & 1
Watchdog Timer
PWM1
12-bit ADC
Pin Connect Block
GPIO Interrupt Ctl
32 kHz
oscillator
DMA
controller
Clock Generation,
Power Control,
Brownout Detect,
and other
system functions
RST
Xtalin
Xtalout
Clocks
and
Controls
Ethernet
PHY
interface
Ethernet
10/100
MAC
USB
device,
host,
OTG
USB
interface
JTAG
interface
ARM Cortex-M3
Test/Debug Interface
System
bus
D-code
bus
I-code
bus
ROM
8 kB
SRAM
64 kB
Trace
Port
Trace Module
High Speed GPIO
Capture/Compare
Timers 2 & 3
External Interrupts
DAC
System Control
Motor Control PWM
Quadrature Encoder
Repetitive Interrupt
Timer
Flash
512 kB
Flash
Accelerator

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Chapter 1: LPC176x/5x Introductory information
1.6 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC176x/5x uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave
ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller. The APB bus bridges are configured
to buffer writes so that the CPU or DMA controller can write to APB devices without
always waiting for APB write completion.
1.7 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with Wake-up Interrupt
Controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is
appended to this manual.
1.7.1 Cortex-M3 Configuration Options
The LPC176x/5x uses the r2p0 version of the Cortex-M3 CPU, which includes a number
of configurable options, as noted below.
System options:
•The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the
SYSTICK timer.
•The Wake-up Interrupt Controller (WIC) is included. The WIC allows more powerful
options for waking up the CPU from reduced power modes.
•A Memory Protection Unit (MPU) is included.
•A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.

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Chapter 1: LPC176x/5x Introductory information
Debug related options:
•A JTAG debug interface is included.
•Serial Wire Debug is included. Serial Wire Debug allows debug operations using only
2 wires, simple trace functions can be added with a third wire.
•The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction
trace capabilities.
•The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data
address or data value matches to be trace information or trigger other events. The
DWT includes 4 comparators and counters for certain internal events.
•An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in
order to send messages to the trace port.
•The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides
trace information to the outside world. This can be on the Serial Wire Viewer pin or the
4-bit parallel trace port.
•A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware
breakpoints and remap specific addresses in code space to SRAM as a temporary
method of altering non-volatile code. The FPB include 2 literal comparators and 6
instruction comparators.
1.8 On-chip flash memory system
The LPC176x/5x contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for use with the two fast AHB-Lite buses. This
memory may be used for both code and data storage. Programming of the flash memory
may be accomplished in several ways. It may be programmed In System via the serial
port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc.
1.9 On-chip Static RAM
The LPC176x/5x contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of
SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus.
Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each
situated on separate slave ports on the AHB multilayer matrix.
This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters.

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Chapter 1: LPC176x/5x Introductory information
1.10 Block diagram
Fig 2. LPC1768 block diagram, CPU and buses
Multilayer
AHB Matrix
AHB to
APB bridge
AHB to
APB bridge
JTAG
interface Debug Port Ethernet PHY interface
SRAM
16 kB
SRAM
16 kB
EMULATION
TRACE MODULE
ARM Cortex-M3
TEST/DEBUG
INTERFACE USB
device,
host,
OTG
USB
interface
DMA
controller Ethernet
10/100
MAC
System
bus
D-code
bus
I-code
bus
DMAC
regs USB regs Ethernet regs
clock generation,
power control,
and other
system functions
SRAM
32 kB ROM 8 kB
Flash
512 kB
Flash
Accelerator
RST
Xtalin
Xtalout
X32Kin
X32Kout
APB slave group 1
Note: shaded peripheral blocks
support General Purpose DMA
Capture/compare
timers 2 & 3
I2C2
I2S
UARTs 2 & 3
SSP0
External interrupts
DAC
System control
Motor control PWM
Quadrature encoder
APB slave group 0
RTC Power Domain
Real Time Clock
SSP1
UARTs 0 & 1
CAN 1 & 2
I2C 0 & 1
SPI0
Capture/compare
timers 0 & 1
Watchdog timer
PWM1
12-bit ADC
Pin connect block
GPIO interrupt control
32 kHz
oscillator
Backup registers
(20 bytes)
Repetitive interrupt
timer
ultra-low power
regulator
Vbat
voltage regulator
clocks
and
controls
internal
power Vdd
CLK
OUT
HS
GPIO

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2.1 Memory map and peripheral addressing
The ARM Cortex-M3 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC176x/5x.
2.2 Memory maps
The LPC176x/5x incorporates several distinct memory regions, shown in the following
figures. Figure 3 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping,
which is described later in this section.
UM10360
Chapter 2: LPC176x/5x Memory map
Rev. 3 — 19 December 2013 User manual
Table 3. LPC176x/5x memory usage and details
Address range General Use Address range details and description
0x0000 0000 to
0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory.
0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory.
0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory.
0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory.
0x0000 0000 - 0x0000 7FFF For devices with 32 kB of flash memory.
On-chip SRAM 0x1000 0000 - 0x1000 7FFF For devices with 32 kB of local SRAM.
0x1000 0000 - 0x1000 3FFF For devices with 16 kB of local SRAM.
0x1000 0000 - 0x1000 1FFF For devices with 8 kB of local SRAM.
Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services.
0x2000 0000 to
0x3FFF FFFF On-chip SRAM (typically used for
peripheral data)
0x2007 C000 - 0x2007 FFFF AHB SRAM - bank 0 (16 kB), present on
devices with 32 kB or 64 kB of total SRAM.
0x2008 0000 - 0x2008 3FFF AHB SRAM - bank 1 (16 kB), present on
devices with 64 kB of total SRAM.
GPIO 0x2009 C000 - 0x2009 FFFF GPIO.
0x4000 0000 to
0x5FFF FFFF APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks, 16 kB each.
0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks,
16 kB each.
AHB peripherals 0x5000 0000 - 0x501F FFFF DMA Controller, Ethernet interface, and USB
interface.
0xE000 0000 to
0xE00F FFFF Cortex-M3 Private Peripheral Bus 0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC and System Tick Timer.

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Chapter 2: LPC176x/5x Memory map
Fig 3. LPC176x/5x system memory map
0x5000 0000
0x5000 4000
0x5000 8000
0x5000 C000
0x5020 0000
AHB peripherals
Ethernet controller
USB controller
reserved
127- 4 reserved
GPDMA controller
0
1
2
3
APB0 peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4002 C000
0x4003 4000
0x4003 0000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 C000
0x4006 0000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT
TIMER0
TIMER1
UART0
UART1
reserved
I2C0
SPI
RTC + backup registers
GPIO interrupts
pin connect
SSP1
ADC
CAN AF RAM
CAN AF registers
CAN common
CAN1
CAN2
22 - 19 reserved
I2C1
31 - 24 reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
APB1 peripherals
0x4008 0000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000
0x400F C000
0x4010 0000
SSP0
DAC
Timer 2
Timer 3
UART2
UART3
reserved
I2S
I2C2
1 - 0 reserved
2
3
4
5
6
7
8
9
10 reserved
repetitive interrupt timer
11
12 reserved
motor control PWM
30 - 16 reserved
13
14
15
system control31
reserved
reserved
32 kB local static RAM
reserved
reserved
private peripheral bus
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x0008 0000
0x1000 0000
0x1000 8000
0x1FFF 0000
0x1FFF 2000
0x2007 C000
0x2008 4000
0x2009 C000
0x200A 0000
0x2200 0000
0x2400 0000
0x4000 0000
0x4008 0000
0x4010 0000
0x4200 0000
0x4400 0000
0x5000 0000
0x5020 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
GPIO
reserved
reserved
reserved
reserved
APB0 peripherals
AHB periherals
APB1 peripherals
AHB SRAM bit band alias addressing
peripheral bit band alias addressing
AHB SRAM (2 blocks of 16 kB)
LPC1768 memory space
512 kB on-chip flash
QEI
PWM1
8 kB boot ROM
0x0000 0000
0x0000 0400 active interrupt vectors+256 words
I-code/D-code
memory space

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Chapter 2: LPC176x/5x Memory map
Figure 3 and Table 4 show different views of the peripheral address space. The AHB
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
2.3 APB peripheral addresses
The following table shows the APB0/1 address maps. No APB peripheral uses all of the
16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at
multiple locations within each 16 kB range.
Table 4. APB0 peripherals and base addresses
APB0 peripheral Base address Peripheral name
0 0x4000 0000 Watchdog Timer
1 0x4000 4000 Timer 0
2 0x4000 8000 Timer 1
3 0x4000 C000 UART0
4 0x4001 0000 UART1
5 0x4001 4000 reserved
6 0x4001 8000 PWM1
7 0x4001 C000 I2C0
8 0x4002 0000 SPI
9 0x4002 4000 RTC
10 0x4002 8000 GPIO interrupts
11 0x4002 C000 Pin Connect Block
12 0x4003 0000 SSP1
13 0x4003 4000 ADC
14 0x4003 8000 CAN Acceptance Filter RAM
15 0x4003 C000 CAN Acceptance Filter Registers
16 0x4004 0000 CAN Common Registers
17 0x4004 4000 CAN Controller 1
18 0x4004 8000 CAN Controller 2
19 to 22 0x4004 C000 to 0x4005 8000 reserved
23 0x4005 C000 I2C1
24 to 31 0x4006 0000 to 0x4007 C000 reserved

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Chapter 2: LPC176x/5x Memory map
2.4 Memory re-mapping
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the Cortex-M3. Refer to Section 6.4 and Section 34.4.3.5 of the
Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset
feature.
Boot ROM re-mapping
Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is
normally transparent to the user. However, if execution is halted immediately after reset by
a debugger, it should correct the mapping for the user. See Section 33.6.
2.5 AHB arbitration
The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3
D-code bus has the highest priority, followed by the I-Code bus. All other masters share a
lower priority.
2.6 Bus fault exceptions
The LPC176x/5x generates Bus Fault exception if an access is attempted for an address
that is in a reserved or unassigned address region. The regions are areas of the memory
map that are not implemented for a specific derivative. These include all spaces marked
“reserved” in Figure 3.
Table 5. APB1 peripherals and base addresses
APB1 peripheral Base address Peripheral name
0 0x4008 0000 reserved
1 0x4008 4000 reserved
2 0x4008 8000 SSP0
3 0x4008 C000 DAC
4 0x4009 0000 Timer 2
5 0x4009 4000 Timer 3
6 0x4009 8000 UART2
7 0x4009 C000 UART3
8 0x400A 0000 I2C2
9 0x400A 4000 reserved
10 0x400A 8000 I2S
11 0x400A C000 reserved
12 0x400B 0000 Repetitive interrupt timer
13 0x400B 4000 reserved
14 0x400B 8000 Motor control PWM
15 0x400B C000 Quadrature Encoder Interface
16 to 30 0x400C 0000 to 0x400F 8000 reserved
31 0x400F C000 System control

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Chapter 2: LPC176x/5x Memory map
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Bus Fault exception is generated for any instruction fetch that maps to an
AHB or APB peripheral address.
Within the address space of an existing APB peripheral, an exception is not generated in
response to an access to an undefined address. Address decoding within each peripheral
is limited to that needed to distinguish defined registers within the peripheral itself. For
example, an access to address 0x4000 D000 (an undefined address within the UART0
space) may result in an access to the register defined at address 0x4000 C000. Details of
such address aliasing within a peripheral space are not defined in the LPC176x/5x
documentation and are not a supported feature.
If software executes a write directly to the flash memory, the flash accelerator will
generate a Bus Fault exception. Flash programming must be accomplished by using the
specified flash programming interface provided by the Boot Code.
Note that the Cortex-M3 core stores the exception flag along with the associated
instruction in the pipeline and processes the exception only if an attempt is made to
execute the instruction fetched from the disallowed address. This prevents accidental
aborts that could be caused by prefetches that occur when code is executed very near a
memory boundary.

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User manual Rev. 3 — 19 December 2013 18 of 841
3.1 Introduction
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
•Reset
•Brown-Out Detection
•External Interrupt Inputs
•Miscellaneous System Controls and Status
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
3.2 Pin description
Table 6 shows pins that are associated with System Control block functions.
UM10360
Chapter 3: LPC176x/5x System control
Rev. 3 — 19 December 2013 User manual
Table 6. Pin summary
Pin name Pin
direction Pin description
EINT0 Input External Interrupt Input 0 - An active low/high level or falling/rising
edge general purpose interrupt input. This pin may be used to wake up
the processor from Sleep, Deep-sleep, or Power-down modes.
EINT1 Input External Interrupt Input 1 - See the EINT0 description above.
EINT2 Input External Interrupt Input 2 - See the EINT0 description above.
EINT3 Input External Interrupt Input 3 - See the EINT0 description above.
RESET Input External Reset input - A LOW on this pin resets the chip, causing I/O
ports and peripherals to take on their default states, and the processor to
begin execution at address 0x0000 0000.

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Chapter 3: LPC176x/5x System control
3.3 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
3.4 Reset
Reset has 4 sources on the LPC176x/5x: the RESET pin, Watchdog Reset, Power On
Reset (POR), and Brown Out Detect (BOD).
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the wake-up timer (see description in
Section 4.9 “Wake-up timer”in this chapter), causing reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the flash controller has completed its initialization. The reset logic is shown in
the following block diagram (see Figure 4).
Table 7. Summary of system control registers
Name Description Access Reset value Address
External Interrupts
EXTINT External Interrupt Flag Register R/W 0 0x400F C140
EXTMODE External Interrupt Mode register R/W 0 0x400F C148
EXTPOLAR External Interrupt Polarity Register R/W 0 0x400F C14C
Reset
RSID Reset Source Identification Register R/W see Table 8 0x400F C180
Syscon Miscellaneous Registers
SCS System Control and Status R/W 0 0x400F C1A0

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Chapter 3: LPC176x/5x System control
On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,
External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time
(maximum of 60 s on power-up) and after the IRC provides a stable clock output, the
reset signal is latched and synchronized on the IRC clock. Then the following two
sequences start simultaneously:
1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is
de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times
out. The boot code performs the boot tasks and may jump to the flash. If the flash is
not ready to access, the Flash Accelerator will insert wait cycles until the flash is
ready.
2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is
de-asserted. The flash wake-up timer generates the 100 s flash start-up time. Once
it times out, the flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the Flash Accelerator will be granted access to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 5 shows an example of the relationship between the RESET, the IRC, and the
processor status when the LPC176x/5x starts up after reset. See Section 4.3.2 “Main
oscillator”for start-up of the main oscillator if selected by the user code.
Fig 4. Reset block diagram including the wake-up timer
C
Q
S
APB read of
PDBIT
in PCON
power-down
C
Q
S
F
OSC
to other
blocks
WAKE-UP TIMER
watchdog
reset
external
reset
START
COUNT 2
n
internal RC
oscillator
Reset to the
on-chip circuitry
Reset to
PCON.PD
write “1”
from APB
reset
EINT0 wake-up
EINT1 wake-up
EINT2 wake-up
POR
BOD
EINT3 wake-up
RTC wake-up
BOD wake-up
Ethernet MAC wake-up
USB need_clk wake-up
CAN wake-up
GPIO0 port wake-up
GPIO2 port wake-up