Terasic CY8CKIT-035 User manual

CONTENTS
CHAPTER 1 INTRODUCTION TO THE PME EBK ...........................................................................3
1.1 Features ......................................................................................................................................................3
1.2 About the KIT.............................................................................................................................................4
1.3 PSoC Creator..............................................................................................................................................6
1.4 Getting Help ...............................................................................................................................................6
CHAPTER 2 PME EBK ARCHITECTURE ............................................................................................7
2.1 Layout and Components.............................................................................................................................7
2.2 PSoC 4+1 Power Supervisor Solution on the PME....................................................................................8
CHAPTER 3 PME EBK HARDWARE OVERVIEW .............................................................................10
3.1 2x20 pin Interface Header ........................................................................................................................ 11
3.2 PME EBK Headers and Jumpers..............................................................................................................12
3.3 Development Kit (DVK) Compatibility ...................................................................................................12
CHAPTER 4 EXAMPLE PROJECTS FOR THE PME .........................................................................13
4.1 Introduction ..............................................................................................................................................13
4.2 Software Installation.................................................................................................................................13
4.3 Hardware Setup ........................................................................................................................................14
4.4 Example Projects ......................................................................................................................................16
4.5 Power Management Component Library .................................................................................................35
4.6 Using Components in Your Own Projects ................................................................................................36
CHAPTER 5 SCHEMATICS ........................................................................................................37
5.1 Primary 12V Power Input.........................................................................................................................37
5.2 DVK Connector and Debug Test Points...................................................................................................38
5.3 Voltage Regulator V1=5V ........................................................................................................................38
5.4 Voltage Regulator V2=3.3V .....................................................................................................................39
5.5 Voltage Regulator V3=2.5V .....................................................................................................................39
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5.6 Voltage Regulator V4=1.8V .....................................................................................................................39
5.7 I2C/SMBus/PMBus Interface Connector .................................................................................................40
5.8 Layout....................................................................................................................................................... 40
5.8.1 Top Layer ..........................................................................................................................................40
5.8.2 Ground Layer ....................................................................................................................................41
5.8.3 Power Layer ......................................................................................................................................41
5.8.4 Bottom Layer.....................................................................................................................................42
5.8.5 Top Silkscreen ...................................................................................................................................43
5.9 Bill of Materials........................................................................................................................................44
CHAPTER 6 APPENDIX .....................................................................................................................48
6.1 Revision History.......................................................................................................................................48
6.2 Copyright Statement .................................................................................................................................48

Chapter 1
Introduction to the PME EBK
In general terms, power management or power supervision is a combination of sequencing,
monitoring and control of multiple regulators and/or point-of-load DC power converters in a
system. Typical solutions for power management include multiple devices such as CPLDs,
mixed-signal ASICs and/or limited-functionality and inflexible discrete devices. Power
management solutions require: (1) rapid fault detection capabilities for high-availability systems of
the power converters in the system; (2) accurate and reliable power rail sequencing of the power
converters during power-on and power-off events; (3) voltage and current measurement of the
power converters to optimize power consumption and/or for data logging; and, (4) closed-loop
control of the power converters through trimming and, for development and manufacturing test
purposes, margining of voltage rails in the system.
The PSoC Power Management Expansion Board Kit (PME EBK) is part of the PSoC development
kit ecosystem and is designed to work with the CY8CKIT-001 PSoC Development Kit (DVK) and
the CY8CKIT-030 PSoC 3 Development Kit (DVK). It enables you to evaluate the system power
management functions and capabilities of PSoC 3 devices. You can evaluate the example projects
described in this guide or design and customize your own system power management solution using
components in Cypress's PSoC CreatorTM software (included in this kit) or by altering example
projects provided with this kit.
The PSoC Power Management Expansion Board Kit (PME EBK) is used with the PSoC family of
devices and is specifically designed and packaged for use with the PSoC 3 device family. PSoC 3 is
a programmable system-on-chip platform that combines precision analog and digital logic with a
high performance, single-cycle, 67MHz 8051 processor. With the flexibility of the PSoC
architecture, you can easily create your own custom power management solution on chip with the
exact functionality you need, in the way you want it—no more, no less.
1.1 Features
The PSoC Power Management Expansion Board Kit (PME EBK) is intended to provide a
demonstration and development platform for Cypress and customers in developing power
management/supervisor solutions including:
•Power Supply Sequencing
•Power Supply Voltage and Current Measurement
•Power Supply Voltage Trimming and Margining
•Power Supply Over-Voltage and Under-Voltage Fault Detection
•EEPROM Data Recording
•I2C/SMBus/PMBus Host Communications Interface
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Figure 1-1 shows a simplified block diagram of the most fundamental components on the PME
EBK and how they interact to aid in understanding of the hardware. Not all hardware components
are shown.
Figure 1-1 PME EBK Block Diagram
1.2 About the KIT
The PSoC Power Management Expansion board kit (PME) consists of:
•Cypress PME EBK
•Quick Start Guide
•Power DC Adaptor 12V/2A
•System CD containing:
○ User’s Guide (this document)
○ PSoC Creator and pre-requisite software
○ PSoC Programmer and pre-requisite software
○ PME Example Firmware for the CY8CKIT-001 PSoC Development Kit
Advanced Sequencer
Power Supervisor
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○ PME Example Firmware for the CY8CKIT-030 PSoC 3 Development Kit
Advanced Sequencer
Power Supervisor
○ Application Note (AN62496) “Voltage Sequencing with PSoC ® 3 and PSoC ® 5”
○ Application Note (AN60220) “Multiplexed Comparator using PSoC ® 3”
○ Datasheets for key PME EBK components
Figure 1-2 shows a photograph of the PME EBK contents.
Figure 1-2 PME EBK Package Contents
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1.3 PSoC Creator
Cypress's PSoC Creator software is a state-of-the-art, easy-to-use integrated development
environment (IDE) that introduces a game changing, hardware and software design environment
based on classic schematic entry and revolutionary embedded design methodology.
With PSoC Creator, you can:
•Draw a schematic of the hardware circuit you would like to build inside PSoC and the tool will
automatically place and route the components for you
•Eliminate external CPLDs or standard logic ICs by integrating state machines and simple glue
logic in your design
Trade-off architecture decisions between hardware and software, allowing you to focus on what
matters and getting you to market faster
PSoC Creator also enables you to tap into an entire tools ecosystem with integrated compiler tool
chains, RTOS solutions, and production programmers to support PSoC 3.
1.4 Getting Help
Certified as a Cypress Authorized Design Partner, Terasic offers design expertise in rapidly
developing PSoC Solutions to get your products into production quickly and reducing your
development and BOM costs. Terasic provides customized board designs for academia and industry.
For additional information visit:
www.cypress.com/go/CY8CKIT-035
or
http://pme.terasic.com
For support please contact:
Online: www.cypress.com/go/support
Telephone (24x7): [phone] ext. 8 (USA)
[phone] ext. 8 (International)

Chapter 2
PME EBK Architecture
This chapter provides information about the architecture and block diagram of the PME EBK.
2.1 Layout and Components
Photos of the PME EBK are shown in Figure 2-1 and Figure 2-2. They depict the layout of the
board and indicate the locations of the connectors and key components.
Figure 2-1 PME PCB (Top)
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Figure 2-2 PME PCB (Bottom)
2.2 PSoC 4+1 Power Supervisor Solution on the PME
The PSoC Power Management EBK contains 4 DC voltage regulator circuits. They all have enable
inputs to allow PSoC to control the power up and power down sequencing of the regulators as well
as the necessary passive components to enable PSoC to measure their output voltage and load
currents using its built-in ADC converter. The regulators chosen support having their output voltage
trimmed (or margined) by PSoC and the necessary passive components to enable PSoC to detect
under and over voltage fault conditions using its internal window comparator hardware. PME EBK
also provides an I2C/SMBus/PMBus compatible header to support systems that have a requirement
for communication with a host controller. All of this functionality is implemented on a single PSoC
3. The PME routes all the input/output signals for power management/supervision to a PSoC 3
mounted on a development kit platform such as the CY8CKIT-001 PSoC Development Kit or
CY8CKIT-030 PSoC 3 Development Kit. PSoC 3 is not mounted on the PME EBK itself.
Figure 2-3 shows a high-level overview of the 4+1 Power Management solution that can be
implemented using the PME. Up to 4 secondary regulators can be sequenced through the logic-level
enable outputs (labeled as EN[4]). The 4 secondary voltage rails along with one primary input
power rail (labeled as V[4+1]) can be multiplexed into a 12 bit, differential Delta Sigma ADC
configured for a single-ended input range of 0-4096 mV at 27 ksps with a 0.1% accurate internal
reference. For load current measurements across a series shunt resistor (labeled as I[4+1]), the ADC
configuration is dynamically changed to a differential input range of ±256mV at 22.9 ksps. A
firmware interrupt service routine (ISR) running on PSoC is responsible for taking the raw ADC
readings and converting them to actual voltages (in mV) and currents (in μA), performing simple
IIR filtering and using this information to increase or decrease the duty cycles of the
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pulse-width-modulated (PWM) outputs for regulator trimming and margining. The trim/margin
PWM outputs from PSoC (labeled as TR[4]) are filtered with a single RC filter stage on PME EBK
and fed into the voltage feedback input of the regulators. A single time-multiplexed window
comparator is implemented in PSoC using 2 voltage DAC’s (to set the under and over voltage limits
for each rail), 2 comparators and a programmable glitch filter. This window comparator loops
through each channel at 2μs per channel that it monitors (labeled as C[4+1]). Note that all 5
monitored supply rail voltages are connected to both the V[4+1] and C[4+1] input pins. Each
voltage is connected to 2 pins to enable the hardware window comparator and the ADC with input
multiplexer to run asynchronously to each other at different speeds in order to give the fastest
possible fault detection time.
Figure 2-3 4+1 PSoC Power Management Functional Diagram
Note that PME EBK hardware limits support to a maximum of 4 secondary regulator circuits. The
PSoC 3 Power Supervisor solution can be easily extended to support up to 12 secondary regulator
circuits. Contact Cypress for further information on the full 12+1 PSoC Power Supervisor solution.
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Chapter 3
PME EBK Hardware Overview
Figure 3-1 PME Hardware Components
The Power Management EBK Board consists of a 12V primary input power source and 4 secondary
voltage rails: V1=5V, V2=3.3V, V3=2.5V and V4=1.8V. Voltage rail V1 feeds power to the other
three rails V2, V3 and V4. Therefore, disabling V1 will disable V2-V4 as a result. Each secondary
rail consists of a regulator with enable input, circuitry that enables PSoC to apply a DC control
voltage to the regulator feedback or adjust pin, as well as fixed and adjustable (potentiometer) load
elements. Two jumpers are provided for each rail to (1) disconnect all loads or (2) disconnect only
the adjustable load.
PME EBK provides an I2C/SMBus/PMBus connector. A 40-pin (2×20) header J1 is provided to
interface this board with the host PSoC on a development kit platform such as the CY8CKIT-001
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PSoC Development Kit or CY8CKIT-030 PSoC 3 Development Kit. The header carries voltage
enables, regulator voltage, regulator load currents and trim/margin control signals for each regulator
on PME EBK. The I2C physical layer signals (SDA/SCL) from PSoC are also routed across this
header to enable connection to an external host or management processor that supports standard I2C,
SMBus or PMBus protocol interfaces.
3.1 2x20 pin Interface Header
The following table outlines the definition of the 40-pin J1 header interface.
Table 3-1 2x20 Header (J1) Pin Definition
Description Signal Pin Pin Signal Description
Voltage Regulator 4, Enable V4EN 1 2 V3EN Voltage Regulator 3, Enable
Voltage Regulator 2, Enable V2EN 3 4 V1EN Voltage Regulator 1, Enable
- NC 5 6 NC -
Power Rail Current
(measured as single ended voltage)
IIN 7 8 VIN Power Rail Sensing Voltage
Analog Ground AGND 9 10 NC -
Voltage Regulator 4, Fault Sensing
Voltage
C4 11 12 C3 Voltage Regulator 3, Fault
Sensing Voltage
Voltage Regulator 2, Fault Sensing
Voltage
C2 13 14 C1 Voltage Regulator 1, Fault
Sensing Voltage
Voltage Regulator 4, Trim TR4 15 16 TR3 Voltage Regulator 3, Trim
Voltage Regulator 2, Trim TR2 17 18 TR1 Voltage Regulator 1, Trim
Analog Ground AGND 19 20 NC -
Voltage Regulator 4, Current
(Measured as differential voltage)
I4 21 22 V4 Voltage Regulator 4
Voltage Regulator 3, Current
(Measured as differential voltage)
I3 23 24 V3 Voltage Regulator 3
Voltage Regulator 2, Current
(Measured as differential voltage)
I2 25 26 V2 Voltage Regulator 2
Voltage Regulator 1 Current
(Measured as single ended voltage)
I1 27 28 V1 Voltage Regulator 1
Analog Ground AGND 29 30 NC -
- NC 31 32 /ALERT Alert Signal (I2C/SMBus/PMBus)
Serial Data (I2C/SMBus/PMBus) SDAT 33 34 SCL Serial Clock (I2C/SMBus/PMBus)
unused D3V3 35 36 VADJ unused
Digital Ground DGND 37 38 D5V unused
Optional 12V Power from DVK DVIN 39 40 DGND Digital Ground

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3.2 PME EBK Headers and Jumpers
A number of headers and jumpers are provided on the PME EBK. The following table outlines the
function of each item and the default configuration.
Table 3-2 PME Jumper Settings
PCB
Designator Description Factory Default Configuration
J1 2×20 pin header for connecting to PSoC DVK -
J2 5-pin header for connecting an external host or management
processor via I2C/SMBus/PMBus
-
J3 Power Jack -
J4 2×20 pin header that replicates signals on J1 for easy connection to a
logic analyzer or oscilloscope
-
J5 3-pin header for primary input power source selection. Place jumper in
1-2 position to source power from the DC power jack J3. Place in 2-3
position to source power from the PSoC platform DVK
2-3 position
J6 2-pin header for connecting all loads on V1=5V rail (this includes the
fixed and adjustable loads on V1 as well as the load presented by the
V2, V3 and V4 rails)
Installed
J7 2-pin header for connecting the potentiometer load on V1=5V rail Installed
J8 2-pin header for connecting both loads on V2=3.3V rail (fixed and
adjustable)
Installed
J9 2-pin header for connecting potentiometer load on V2=3.3V rail Installed
J10 2-pin header for connecting ALL loads on V3=2.5V rail (fixed and
adjustable)
Installed
J11 2-pin header for connecting variable potentiometer on V3=2.5V rail Installed
J12 2-pin header for connecting ALL loads on V4=1.8V rail (fixed and
adjustable)
Installed
J13 2-pin header for connecting variable potentiometer on V4=1.8V rail Installed
3.3 Development Kit (DVK) Compatibility
This kit contains an expansion board only and requires a Cypress development kit platform in order
to use it. This kit is compatible with both the CY8CKIT-001 PSoC DVK and the CY8CKIT-030
PSoC 3 DVK.
NOTE: Early revisions of the CY8CKIT-001 PSoC Development Kit contained an early
engineering sample release (ES2) of the PSoC 3 CY8C38xxx Device Family Processor Module
which is not compatible with the example projects that accompany this kit. If you have an early
revision of the kit you can upgrade free of charge at www.cypress.com/go/psoc3kitupgrade.

Chapter 4
Example Projects for the PME
4.1 Introduction
This section provides details on how to operate the hardware and run the example projects provided.
4.2 Software Installation
Perform the following steps to install the PSoC PME EBK software:
Insert the kit CD into the CD drive of your PC. The CD is designed to auto-run and the kit menu
should appear. (See Figure 4-1)
Figure 4-1 CD Autorun Kit Menu
NOTE: If auto-run does not execute, double-click AutoRun on the root directory of the CD.
After the installation is complete, the kit contents are available at the following location:
C:\Program Files\Terasic\PSoC Power Management EBK\1.0
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When installing the PSoC Power Management EBK software, the installer checks if your system
has the required software. This includes PSoC Creator, PSoC Programmer, Windows Installer, .NET
framework, Adobe Acrobat Reader, and KEIL Compiler. If these applications are not installed, then
the installer prompts you to install all pre-requisite software, which is also available on the kit CD.
The software can be uninstalled using one of the following methods:
zGo to Start > Control Panel > Add or Remove Programs; select appropriate software
package; select the Remove button.
zGo to Start > All Programs > Cypress > Cypress Update Manager > Cypress Update
Manager; select the Uninstall button for the appropriate software package.
zInsert the kit CD and click Install the kit contents from CD button. In the CyInstaller for
PSoC Power Management EBK 1.0 window, select Remove from the Installation Type
drop-down menu. Follow the instructions to uninstall. (NOTE: this method will only un install
the kit software and not all the other material/software that may have been installed along with
the kit software)
4.3 Hardware Setup
The kit includes example projects for both the CY8CKIT-001 PSoC DVK and the CY8CKIT-030
PSoC 3 DVK hardware platforms. The main difference between the projects for the two hardware
platforms is the PSoC pin mapping. Other differences will be highlighted in the sections that
describe details of the example projects. The following sections describe how to set up the hardware
to run the example projects. For a given DVK base platform, the same hardware configuration
applies to both example projects.
CY8CKIT-001 PSoC DVK
1. Using the pin header/breadboard area of the PSoC DVK base board, use jumper wires to make
the following connections:
z“SW1” to P1_4
z“SW2” to P1_5
Figure 4-2 CY8CKIT-001 PSoC DVK Breadboard
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2. Set the system to run at 5V using SW3 and set J6 “VDD DIG” and J7 “VDD ANLG” to
VDD=5V using J6 and J7 as shown below:
Figure 4-3 CY8CKIT-001 PSoC DVK Power Jumpers
3. Ensure that the LCD character display included with PSoC DVK is attached and that the LCD
power jumper (J12) is in the ON position:
Figure 4-4 CY8CKIT-001 PSoC DVK LCD Power Jumper
CAUTION: Do not attach the PSoC Power Management EBK to the PSoC DVK until you have
programmed the PSoC with one of the example projects. The GPIOs routed to the PSoC Power
Management EBK connect to the power regulator circuits which may be damaged if firmware
previously programmed into PSoC drives those pins. Once the PSoC has been programmed,
attach the PSoC Power Management EBK to PORT A of the PSoC DVK.
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CY8CKIT-030 PSoC 3 DVK
1. No jumper wires are required for the PSoC 3 DVK examples since the buttons and
potentiometer are hardwired to GPIOs. Ensure that the LCD character display included with
the PSoC 3 DVK is attached.
2. Set VDDD and VDDA to 5.0V using J10 and J11
Figure 4-5 CY8CKIT-030 PSoC 3 DVK Power Jumpers
CAUTION: Do not attach the PSoC Power Management EBK to the PSoC 3 DVK until you have
programmed the PSoC with one of the example projects. The GPIOs routed to the PSoC Power
Management EBK connect to the power regulator circuits which may be damaged if firmware
previously programmed into PSoC drives those pins. Once the PSoC has been programmed, attach
the PSoC Power Management EBK to PORT E of the PSoC 3 DVK.
4.4 Example Projects
The PSoC Power Management EBK includes two example projects:
1. Advanced Sequencer
2. Power Supervisor
The kit includes project workspaces for both the CY8CKIT-001 PSoC DVK and the CY8CKIT-030
PSoC 3 DVK.
To begin, go to the Start Page in PSoC Creator and under the Examples and Tutorials section,
expand the Kits and Solutions entry as shown below. Expand the PSoC Power Management EBK
entry and double click on the workspace file that matches your development kit
(CY8CKIT-001_Examples.cywrk or CY8CKIT-030_Examples.cywrk). The example projects will
be copied to any location you specify on your hard drive and then opened automatically.
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Figure 4-6 PSoC Creator Start Page showing Kits and Solutions
The example projects will be displayed in the Workspace Explorer window as shown in the
example below for the CY8CKIT-001 PSoC DVK:
Figure 4-7 Workspace Explorer View
Running the Example Firmware: CY8CKIT-001 PSoC DVK
Make sure the hardware has been configured according to the Hardware Setup section.
1. If this is the first time that the example project firmware is being programmed into PSoC, make
sure the PSoC Power Management EBK is not connected to the PSoC DVK
2. Apply 12 VDC power to the PSoC DVK
3. Attach the MiniProg3 first to a USB port on the PC and then to the PROG port on the
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CY8CKIT-009 PSoC 3 Processor Module
4. In PSoC Creator, set the appropriate example project as active by right clicking on it in the
Workspace Explorer and selecting Set As Active Project
5. In PSoC Creator, select Debug > Program to program PSoC
6. Remove power from the PSoC DVK and attach the PSoC Power Management EBK to Port A
of the PSoC DVK
7. On the PSoC Power Management EBK board, make sure the power jumper (J5) is set to
“DVK” (the default setting)
8. Apply 12 VDC power to the PSoC DVK
9. If the PME EBK cannot be detected by PSoC, status debug messages will be displayed on the
LCD to assist with rectifying the problem
Figure 4-8 CY8CKIT-001 PSoC DVK with PSoC Power Management EBK
Connected to Port A (Running Example 2)
Running the Example Firmware: CY8CKIT-030 PSoC 3 DVK
Make sure the hardware has been configured according to the Hardware Setup section.
1. If this is the first time that the example project firmware is being programmed into PSoC, make
sure the PSoC Power Management EBK is not connected to the PSoC 3 DVK
2. Attach a USB cable from the PC to the PSoC 3 DVK Program/Debug USB port (use J1 - the
USB connector closest to the corner of the board)
3. In PSoC Creator, set the appropriate example project as active by right clicking on it in the
Workspace Explorer and selecting Set As Active Project
4. In PSoC Creator, select Debug > Program to program PSoC
5. Remove the USB cable from the PSoC 3 DVK and attach the PSoC Power Management EBK
to Port E of the PSoC 3 DVK
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6. On the PSoC Power Management EBK board, make sure the power jumper (J5) is set to “EXT”.
Note that this is not the default setting for the J5 jumper.
7. Apply 12 VDC power to the PSoC Power Management EBK using J3
8. Re-attach the USB cable from the PC to the PSoC 3 DVK Program/Debug USB port (use J1 -
the USB connector closest to the corner of the board)
9. If the PME EBK cannot be detected by PSoC, status debug messages will be displayed on the
LCD to assist with rectifying the problem
10. Going forward, every time PSoC is re-programmed, press the Reset (SW1) button on the PSoC
3 DVK to run the newly programmed firmware image
Figure 4-9 CY8CKIT-030 PSoC 3 DVK with PSoC Power Management EBK Connected
to Port E (Running Example 2)
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