Terasic De0-Nano User manual

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CONTENTS
CHAPTER 1 INTRODUCTION................................................................................................................5
1.1 Features....................................................................................................................................................5
1.2 About the KIT...........................................................................................................................................7
1.3 Getting Help.............................................................................................................................................7
CHAPTER 2 DE0-NANO BOARD ARCHITECTURE............................................................................8
2.1 Layout and Components...........................................................................................................................8
2.2 Block Diagram of the DE0-Nano Board...................................................................................................9
2.3 Power-up the DE0-Nano Board..............................................................................................................10
CHAPTER 3 USING THE DE0-NANO BOARD....................................................................................11
3.1 Configuring the Cyclone IV FPGA ........................................................................................................ 11
3.2 General User Input/Output .....................................................................................................................12
3.3 SDRAM Memory...................................................................................................................................15
3.4 I2C Serial EEPROM .............................................................................................................................. 16
3.5 Expansion Headers.................................................................................................................................17
3.6 A/D Converter and 2x13 Header ............................................................................................................20
3.7 Digital Accelerometer............................................................................................................................. 23
3.8 Clock Circuitry....................................................................................................................................... 23
3.9 Power Supply ......................................................................................................................................... 24
CHAPTER 4 DE0-NANO CONTROL PANEL.......................................................................................26
4.1 Control Panel Setup................................................................................................................................26
4.2 Controlling the LEDs .............................................................................................................................28
4.3 Switches and Pushbuttons ......................................................................................................................28
4.4 Memory Controller.................................................................................................................................29
4.5 Digital Accelerometer............................................................................................................................. 31
4.6 ADC .......................................................................................................................................................32
4.7 Overall Structure of the DE0-Nano Control Panel..................................................................................33
CHAPTER 5 DE0-NANO SYSTEM BUILDER......................................................................................34
5.1 Introduction............................................................................................................................................34

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5.2 General Design Flow..............................................................................................................................34
5.3 Using DE0-Nano System Builder........................................................................................................... 36
CHAPTER 6 TUTORIAL: CREATINGAN FPGA PROJECT .............................................................40
6.1 Design Flow ........................................................................................................................................... 40
6.2 Before You Begin...................................................................................................................................41
6.3 What You Will Learn..............................................................................................................................45
6.4 Assign The Device..................................................................................................................................45
6.5 Creating an FPGA design.......................................................................................................................49
6.6 Assign the Pins .......................................................................................................................................71
6.7 Create a Default TimeQuest SDC File....................................................................................................73
6.8 Compile Your Design ............................................................................................................................. 74
6.9 Program the FPGA Device .....................................................................................................................76
6.10 Verify The Hardware ............................................................................................................................79
CHAPTER 7 TUTORIAL: CREATINGA NIOS II PROJECT.............................................................82
7.1 Required Features...................................................................................................................................82
7.2 Creation of Hardware Design.................................................................................................................82
7.3 Download the Hardware Design........................................................................................................... 117
7.4 Create a hello_world Example Project .................................................................................................120
7.5 Build and Run the Program ..................................................................................................................123
7.6 Edit and Re-Run the Program...............................................................................................................124
7.7 Why the LED Blinks ............................................................................................................................126
7.8 Debugging the Application...................................................................................................................127
7.9 Configure System Library ....................................................................................................................128
CHAPTER 8 DE0-NANO DEMONSTRATIONS .................................................................................130
8.1 System Requirements........................................................................................................................... 130
8.2 Breathing LEDs.................................................................................................................................... 130
8.3 ADC Reading .......................................................................................................................................132
8.4 SOPC Demo......................................................................................................................................... 136
8.5 G-Sensor...............................................................................................................................................142
8.6 SDRAM Test by Nios II .......................................................................................................................143
CHAPTER 9 APPENDIX.......................................................................................................................147
9.1 Programming the Serial Configuration Device.....................................................................................147
9.2 EPCS Programming via nios-2-flash-programmer ...............................................................................155

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9.3 Revision History...................................................................................................................................155
9.4 Copyright Statement............................................................................................................................. 155

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Chapter 1
Introduction
The DE0-Nano board introduces a compact-sized FPGA development platform suited for to a wide
range of portable design projects, such as robots and mobile projects.
The DE0-Nano is ideal for use with embedded soft processors—it features a powerful Altera Cyclone
IV FPGA (with 22,320 logic elements), 32 MB of SDRAM, 2 Kb EEPROM, and a 64 Mb serial
configuration memory device. For connecting to real-world sensors the DE0-Nano includes a
National Semiconductor 8-channel 12-bit A/D converter, and it also features an Analog Devices
13-bit, 3-axis accelerometer device.
The DE0-Nano board includes a built-in USB Blaster for FPGA programming, and the board can be
powered either from this USB port or by an external power source. The board includes expansion
headers that can be used to attach various Terasic daughter cards or other devices, such as motors
and actuators. Inputs and outputs include 2 pushbuttons, 8 user LEDs and a set of 4 dip-switches.
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1. .1 1 F Fe ea at tu ur re es s
Figure 1-1 shows a photograph of the DE0-Nano Board.
Figure 1-1 The DE0-Nano Board

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The key features of the board are listed below:
Featured device
oAltera Cyclone® IV EP4CE22F17C6N FPGA
o153 maximum FPGA I/O pins
Configuration status and set-up elements
oOn-board USB-Blaster circuit for programming
oSpansion EPCS64
Expansion header
oTwo 40-pin Headers (GPIOs) provide 72 I/O pins, 5V power pins, two 3.3V power pins and
four ground pins
Memory devices
o32MB SDRAM
o2Kb I2C EEPROM
General user input/output
o8 green LEDs
o2 debounced pushbuttons
o4-position DIP switch
G-Sensor
oADI ADXL345, 3-axis accelerometer with high resolution (13-bit)
A/D Converter
oNS ADC128S022, 8-Channel, 12-bit A/D Converter
o50 Ksps to 200 Ksps
Clock system
oOn-board 50MHz clock oscillator
Power Supply
oUSB Type mini-AB port (5V)
oDC 5V pin for each GPIO header (2 DC 5V pins)
o2-pin external power header (3.6-5.7V)

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1. .2 2 A Ab bo ou ut t t th he e K KI IT T
The kit comes with the following contents:
DE0-Nano board
System CD-ROM.
USB Cable
The system CD contains technical documents for the DE0-Nano board, which includes component
datasheets, demonstrations, schematic, and user manual.
Figure 1-2 shows the photograph of the DE0-Nano kit contents.
Figure 1-2 DE0-Nano kit package contents
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1. .3 3 G Ge et tt ti in ng g H He el lp p
Here is information of how to get help if you encounter any problem:
Terasic Technologies
Tel: [phone]
Email: [email protected]om
Altera Corporation
Email: [e-mail]

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Chapter 2
DE0-Nano Board Architecture
This chapter describes the architecture of the DE0-Nano board including block diagram and
components.
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2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
The picture of the DE0-Nano board is shown in Figure 2-1 and Figure 2-2. It depicts the layout of
the board and indicates the locations of the connectors and key components.
Figure 2-1 The DE0-Nano Board PCB and component diagram (top view)

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Figure 2-2 The DE0-Nano Board PCB and component diagram (bottom view)
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2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E0 0- -N Na an no o B Bo oa ar rd d
Figure 2-3 shows the block diagram of the DE0-Nano board. To provide maximum flexibility for
the user, all connections are made through the Cyclone IV FPGA device. Thus, the user can
configure the FPGA to implement any system design.
Figure 2-3 Block diagram of DE0-Nano Board

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2. .3 3 P Po ow we er r- -u up p t th he e D DE E0 0- -N Na an no o B Bo oa ar rd d
The DE0-Nano board comes with a preloaded configuration bit stream to demonstrate some
features of the board. This allows users to see quickly if the board is working properly. To power-up
the board two options are available which are described below:
1. Connect a USB Mini-B cable between a USB (Type A) host port and the board. For
communication between the host and the DE0-Nano board, it is necessary to install the Altera USB
Blaster driver software.
2. Alternatively, users can power-up the DE0-Nano board by supplying 5V to the two DC +5
(VCC5) pins of the GPIO headers or supplying (3.6-5.7V) to the 2-pin header.
At this point you should observe flashing LEDs on the board.

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Chapter 3
Using the DE0-Nano Board
This chapter gives instructions for using the DE0-Nano board and describes in detail its components
and connectors, along with the required pin assignments.
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3. .1 1 C Co on nf fi ig gu ur ri in ng g t th he e C Cy yc cl lo on ne e I IV V F FP PG GA A
The DE0-Nano board contains a Cyclone IV E FPGA which can be programmed using JTAG
programming. This allows users to configure the FPGA with a specified design using Quartus II
software. The programmed design will remain functional on the FPGA as long as the board is
powered on, or until the device is reprogrammed. The configuration information will be lost when
the power is turned off.
To download a configuration bit stream file using JTAG Programming into the Cyclone IV FPGA,
perform the following steps:
1. Connect a USB Mini-B cable between a host computer and the DE0-Nano.
2. The FPGA can now be programmed through the Quartus II Programmer by selecting a
configuration bit stream file with the .sof filename extension.
Configuring the Spansion EPCS64 device
The DE0-Nano board contains a Spansion EPCS64 serial configuration device. This device
provides non-volatile storage of the configuration bit-stream, so that the information is retained
even when the power supply to the DE0-Nano board is turned off. When the board’s power is
turned on, the configuration data in the EPCS64 device is automatically loaded into the Cyclone IV
E FPGA.
The Cyclone IV E device supports in-system programming of a serial configuration device using
the JTAG interface via the serial flash loader design. The serial flash loader is a bridge design for
the Cyclone IV E device that uses its JTAG interface to access the EPCS .jic file and then uses the
AS interface to program the EPCS device. Figure 3-1 illustrates the programming method when
adopting a serial flash loader solution. Chapter 9 of this document describes how to load a circuit to
the serial configuration device.

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Figure 3-1 Programming a serial configuration device with serial flash loader solution
JTAG Chain on DE0-Nano Board
The JTAG Chain on the DE0-Nano board is connected to a host computer using an on-board
USB-blaster. The USB-blaster consists of a USB Mini-B connector, a FTDI USB 2.0 Controller,
and an Altera MAX II CPLD.
Figure 3-2 illustrates the JTAG configuration setup.
Figure 3-2 JTAG Chain
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3. .2 2 G Ge en ne er ra al l U Us se er r I In np pu ut t/ /O Ou ut tp pu ut t
Pushbuttons
The DE0-Nano board contains two pushbuttons shown in Figure 3-3. Each pushbutton is
debounced using a Schmitt Trigger circuit, as indicated in Figure 3-4. The two outputs called KEY0,
and KEY1 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA. Each
pushbutton provides a high logic level when it is not pressed, and provides a low logic level when
pressed. Since the pushbuttons are debounced, they are appropriate for using as clock or reset
inputs.

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Figure 3-3 Connections between the push-buttons and Cyclone IV FPGA
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced
Figure 3-4 Pushbuttons debouncing
LEDs
There are 8 green user-controllable LEDs on the DE0-Nano board. The eight LEDs, which are
presented in Figure 3-4, allow users to display status and debugging information. Each LED is
driven directly by the Cyclone IV E FPGA. Each LED is driven directly by a pin on the Cyclone IV
E FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low
turns it off.

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Figure 3-5 Connections between the LEDs and Cyclone IV FPGA
DIPSwitch
The DE0-Nano board contains a 4 dip switches. A DIP switch provides, to the FPGA, a high logic
level when it is in the DOWN position, and a low logic level when in the UPPER position.
Table 3-1 Pin Assignments for Push-buttons
Signal Name
FPGA Pin No.
Description
I/O Standard
KEY[0]
PIN_J15
Push-button[0]
3.3V
KEY[1]
PIN_E1
Push-button[1]
3.3V
Table 3-2 Pin Assignments for LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LED[0]
PIN_A15
LED Green[0]
3.3V
LED[1]
PIN_A13
LED Green[1]
3.3V
LED[2]
PIN_B13
LED Green[2]
3.3V
LED[3]
PIN_A11
LED Green[3]
3.3V
LED[4]
PIN_D1
LED Green[4]
3.3V
LED[5]
PIN_F3
LED Green[5]
3.3V
LED[6]
PIN_B1
LED Green[6]
3.3V
LED[7]
PIN_L3
LED Green[7]
3.3V

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Table 3-3 Pin Assignments for DIP Switches
Signal Name
FPGA Pin No.
Description
I/O Standard
DIP Switch[0]
PIN_M1
DIP Switch[0]
3.3V
DIP Switch[1]
PIN_T8
DIP Switch[1]
3.3V
DIP Switch[2]
PIN_B9
DIP Switch[2]
3.3V
DIP Switch[3]
PIN_M15
DIP Switch[3]
3.3V
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3. .3 3 S SD DR RA AM M M Me em mo or ry y
The board features a Synchronous Dynamic Random Access Memory (SDRAM) device providing
32MB with a 16-bit data lines connected to the FPGA. The chip uses 3.3V LVCMOS signaling
standard. All signals are registered on the positive edge of the clock signal, DRAM_CLK.
Connections between the FPGAand SDRAM chips are shown in Figure 3-6.
Figure 3-6 Connections between FPGA and SDRAM
Table 3-4 SDRAM Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
DRAM_ADDR[0]
PIN_P2
SDRAM Address[0]
3.3V
DRAM_ADDR[1]
PIN_N5
SDRAM Address[1]
3.3V
DRAM_ADDR[2]
PIN_N6
SDRAM Address[2]
3.3V
DRAM_ADDR[3]
PIN_M8
SDRAM Address[3]
3.3V
DRAM_ADDR[4]
PIN_P8
SDRAM Address[4]
3.3V
DRAM_ADDR[5]
PIN_T7
SDRAM Address[5]
3.3V
DRAM_ADDR[6]
PIN_N8
SDRAM Address[6]
3.3V
DRAM_ADDR[7]
PIN_T6
SDRAM Address[7]
3.3V
DRAM_ADDR[8]
PIN_R1
SDRAM Address[8]
3.3V
DRAM_ADDR[9]
PIN_P1
SDRAM Address[9]
3.3V
DRAM_ADDR[10]
PIN_N2
SDRAM Address[10]
3.3V
DRAM_ADDR[11]
PIN_N1
SDRAM Address[11]
3.3V

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DRAM_ADDR[12]
PIN_L4
SDRAM Address[12]
3.3V
DRAM_DQ[0]
PIN_G2
SDRAM Data[0]
3.3V
DRAM_DQ[1]
PIN_G1
SDRAM Data[1]
3.3V
DRAM_DQ[2]
PIN_L8
SDRAM Data[2]
3.3V
DRAM_DQ[3]
PIN_K5
SDRAM Data[3]
3.3V
DRAM_DQ[4]
PIN_K2
SDRAM Data[4]
3.3V
DRAM_DQ[5]
PIN_J2
SDRAM Data[5]
3.3V
DRAM_DQ[6]
PIN_J1
SDRAM Data[6]
3.3V
DRAM_DQ[7]
PIN_R7
SDRAM Data[7]
3.3V
DRAM_DQ[8]
PIN_T4
SDRAM Data[8]
3.3V
DRAM_DQ[9]
PIN_T2
SDRAM Data[9]
3.3V
DRAM_DQ[10]
PIN_T3
SDRAM Data[10]
3.3V
DRAM_DQ[11]
PIN_R3
SDRAM Data[11]
3.3V
DRAM_DQ[12]
PIN_R5
SDRAM Data[12]
3.3V
DRAM_DQ[13]
PIN_P3
SDRAM Data[13]
3.3V
DRAM_DQ[14]
PIN_N3
SDRAM Data[14]
3.3V
DRAM_DQ[15]
PIN_K1
SDRAM Data[15]
3.3V
DRAM_BA[0]
PIN_M7
SDRAM Bank Address[0]
3.3V
DRAM_BA[1]
PIN_M6
SDRAM Bank Address[1]
3.3V
DRAM_DQM[0]
PIN_R6
SDRAM byte Data Mask[0]
3.3V
DRAM_DQM[1]
PIN_T5
SDRAM byte Data Mask[1]
3.3V
DRAM_RAS_N
PIN_L2
SDRAM Row Address Strobe
3.3V
DRAM_CAS_N
PIN_L1
SDRAM Column Address Strobe
3.3V
DRAM_CKE
PIN_L7
SDRAM Clock Enable
3.3V
DRAM_CLK
PIN_R4
SDRAM Clock
3.3V
DRAM_WE_N
PIN_C2
SDRAM Write Enable
3.3V
DRAM_CS_N
PIN_P6
SDRAM Chip Select
3.3V
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3. .4 4 I I2 2C C S Se er ri ia al l E EE EP PR RO OM M
The DE0-Nano contains a 2Kbit Electrically Erasable PROM (EEPROM). The EEPROM is
configured through a 2-wire I2C serial interface. The device is organized as one block of 256 x 8-bit
memory. The I2C write and read address are 0xA0 and 0xA1, respectively. Figure 3-7 illustrates its
connections with the Cyclone IV FPGA.

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Figure 3-7 Connections between FPGA and EEPROM
Table 3-5 Pin Assignments for I2C Serial EEPROM
Signal Name
FPGA Pin No.
Description
I/O Standard
I2C_SCLK
PIN_F2
EEPROM clock
3.3V
I2C_SDAT
PIN_F1
EEPROM data
3.3V
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3. .5 5 E Ex xp pa an ns si io on n H He ea ad de er rs s
The DE0-Nano board provides two 40-pin expansion headers. Each header connects directly to 36
pins of the Cyclone IV E FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two
GND pins. Figure 3-8 shows the I/O distribution of the GPIO connectors.

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Figure 3-8 Pin arrangement of the GPIO expansion headers
The pictures below indicate the pin 1 location of the expansion headers.
Figure 3-9 Pin1 locations of the GPIO expansion headers
Table 3-6 GPIO-0 Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
GPIO_0_IN0
PIN_A8
GPIO Connection DATA
3.3V
GPIO_00
PIN_D3
GPIO Connection DATA
3.3V
GPIO_0_IN1
PIN_B8
GPIO Connection DATA
3.3V
GPIO_01
PIN_C3
GPIO Connection DATA
3.3V

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GPIO_02
PIN_A2
GPIO Connection DATA
3.3V
GPIO_03
PIN_A3
GPIO Connection DATA
3.3V
GPIO_04
PIN_B3
GPIO Connection DATA
3.3V
GPIO_05
PIN_B4
GPIO Connection DATA
3.3V
GPIO_06
PIN_A4
GPIO Connection DATA
3.3V
GPIO_07
PIN_B5
GPIO Connection DATA
3.3V
GPIO_08
PIN_A5
GPIO Connection DATA
3.3V
GPIO_09
PIN_D5
GPIO Connection DATA
3.3V
GPIO_010
PIN_B6
GPIO Connection DATA
3.3V
GPIO_011
PIN_A6
GPIO Connection DATA
3.3V
GPIO_012
PIN_B7
GPIO Connection DATA
3.3V
GPIO_013
PIN_D6
GPIO Connection DATA
3.3V
GPIO_014
PIN_A7
GPIO Connection DATA
3.3V
GPIO_015
PIN_C6
GPIO Connection DATA
3.3V
GPIO_016
PIN_C8
GPIO Connection DATA
3.3V
GPIO_017
PIN_E6
GPIO Connection DATA
3.3V
GPIO_018
PIN_E7
GPIO Connection DATA
3.3V
GPIO_019
PIN_D8
GPIO Connection DATA
3.3V
GPIO_020
PIN_E8
GPIO Connection DATA
3.3V
GPIO_021
PIN_F8
GPIO Connection DATA
3.3V
GPIO_022
PIN_F9
GPIO Connection DATA
3.3V
GPIO_023
PIN_E9
GPIO Connection DATA
3.3V
GPIO_024
PIN_C9
GPIO Connection DATA
3.3V
GPIO_025
PIN_D9
GPIO Connection DATA
3.3V
GPIO_026
PIN_E11
GPIO Connection DATA
3.3V
GPIO_027
PIN_E10
GPIO Connection DATA
3.3V
GPIO_028
PIN_C11
GPIO Connection DATA
3.3V
GPIO_029
PIN_B11
GPIO Connection DATA
3.3V
GPIO_030
PIN_A12
GPIO Connection DATA
3.3V
GPIO_031
PIN_D11
GPIO Connection DATA
3.3V
GPIO_032
PIN_D12
GPIO Connection DATA
3.3V
GPIO_033
PIN_B12
GPIO Connection DATA
3.3V
Table 3-7 GPIO-1 Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
GPIO_1_IN0
PIN_T9
GPIO Connection DATA
3.3V
GPIO_10
PIN_F13
GPIO Connection DATA
3.3V
GPIO_1_IN1
PIN_R9
GPIO Connection DATA
3.3V
GPIO_11
PIN_T15
GPIO Connection DATA
3.3V
GPIO_12
PIN_T14
GPIO Connection DATA
3.3V
GPIO_13
PIN_T13
GPIO Connection DATA
3.3V
GPIO_14
PIN_R13
GPIO Connection DATA
3.3V
GPIO_15
PIN_T12
GPIO Connection DATA
3.3V

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GPIO_16
PIN_R12
GPIO Connection DATA
3.3V
GPIO_17
PIN_T11
GPIO Connection DATA
3.3V
GPIO_18
PIN_T10
GPIO Connection DATA
3.3V
GPIO_19
PIN_R11
GPIO Connection DATA
3.3V
GPIO_110
PIN_P11
GPIO Connection DATA
3.3V
GPIO_111
PIN_R10
GPIO Connection DATA
3.3V
GPIO_112
PIN_N12
GPIO Connection DATA
3.3V
GPIO_113
PIN_P9
GPIO Connection DATA
3.3V
GPIO_114
PIN_N9
GPIO Connection DATA
3.3V
GPIO_115
PIN_N11
GPIO Connection DATA
3.3V
GPIO_116
PIN_L16
GPIO Connection DATA
3.3V
GPIO_117
PIN_K16
GPIO Connection DATA
3.3V
GPIO_118
PIN_R16
GPIO Connection DATA
3.3V
GPIO_119
PIN_L15
GPIO Connection DATA
3.3V
GPIO_120
PIN_P15
GPIO Connection DATA
3.3V
GPIO_121
PIN_P16
GPIO Connection DATA
3.3V
GPIO_122
PIN_R14
GPIO Connection DATA
3.3V
GPIO_123
PIN_N16
GPIO Connection DATA
3.3V
GPIO_124
PIN_N15
GPIO Connection DATA
3.3V
GPIO_125
PIN_P14
GPIO Connection DATA
3.3V
GPIO_126
PIN_L14
GPIO Connection DATA
3.3V
GPIO_127
PIN_N14
GPIO Connection DATA
3.3V
GPIO_128
PIN_M10
GPIO Connection DATA
3.3V
GPIO_129
PIN_L13
GPIO Connection DATA
3.3V
GPIO_130
PIN_J16
GPIO Connection DATA
3.3V
GPIO_131
PIN_K15
GPIO Connection DATA
3.3V
GPIO_132
PIN_J13
GPIO Connection DATA
3.3V
GPIO_133
PIN_J14
GPIO Connection DATA
3.3V
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3. .6 6 A A/ /D D C Co on nv ve er rt te er r a an nd d 2 2x x1 13 3 H He ea ad de er r
The DE0-Nano contains an ADC128S022 lower power, eight-channel CMOS 12-bit
analog-to-digital converter. This A-to-D provides conversion throughput rates of 50 ksps to 200
ksps. It can be configured to accept up to eight input signals at inputs IN0 through IN7. This eight
input signals are connected to the 2x13 header, as shown in Figure 3-10. The remaining I/Os of the
2x13 header are a DC +3.3V (VCC33), a GND and 13 pins, which are connect directly to the
Cyclone IV E device.
For more detailed information on the A/D converter chip, please refer to its datasheet which is
available on manufacturer’s website or under the /datasheet folder of the system CD.