Terasic Altera DE3 User manual

Altera DE3 Board

Altera DE3 Board
ii
CONTENTS
Chapter 1 Overview...........................................................................................................................1
1.1 Introduction..........................................................................................................................1
1.2 Layout and Components ......................................................................................................1
1.3 Block Diagram of the DE3 Board........................................................................................4
Chapter 2 Using the DE3 Board.......................................................................................................8
2.1 Configuring the FPGA and Serial Configuration Device ....................................................8
2.2 JTAG Chain........................................................................................................................10
2.3 Using the User I/O Interface..............................................................................................13
2.4 I/O Groups and V
CCIO
Control Circuit ...............................................................................14
2.5 Using the HSTC Connectors..............................................................................................17
2.6 Connecting HSTC/HSMC Daughter Boards to DE3 HSTC connectors ...........................20
2.7 Using the GPIO Expansion Headers..................................................................................20
2.8 Using the DDR2 SO-DIMM..............................................................................................21
2.9 Using the USB OTG..........................................................................................................22
2.10 Using the SD Card .............................................................................................................23
2.11 LED Indicators...................................................................................................................24
2.12 Clock Circuitry...................................................................................................................24
2.13 Using the Temperature Sensor...........................................................................................27
Chapter 3 Control Panel..................................................................................................................28
3.1 Control Panel Setup ...........................................................................................................28
3.2 Controlling the LEDs and 7-Segment Displays.................................................................31
3.3 SWITCH/BUTTON...........................................................................................................33
3.4 Memory Controller ............................................................................................................33
3.5 USB2.0 OTG......................................................................................................................35
3.6 SD CARD ..........................................................................................................................36
3.7 Temperature Monitor .........................................................................................................37
3.8 I/O Group...........................................................................................................................38
3.9 Overall Structure of the DE3 Control Panel ......................................................................40
Chapter 4 DE3 System Builder.......................................................................................................41
4.1 Introduction........................................................................................................................41
4.2 General Design Flow .........................................................................................................41
4.3 Using DE3 System Builder................................................................................................43
4.4 Creating My First DE3 Project ..........................................................................................49
4.5 Connect TERASIC Daughter Boards to a DE3 Board ......................................................50
4.6 Connect Multiple DE3 Boards...........................................................................................53
4.7 Connect a Custom-Made Daughter Board to the DE3 Board............................................56

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Chapter 5 Examples of Advanced Demonstration........................................................................58
5.1 USB Host ...........................................................................................................................58
5.2 USB Device........................................................................................................................65
5.3 SD Card..............................................................................................................................68
5.4 DDR2 SDRAM..................................................................................................................73
Appendix APin connections between components and FPGA on the DE3 board.....................80
Appendix B Pin Compatible List for HSTC and HSMC Connector ..........................................98
Appendix C Programming the Serial Configuration Device.....................................................102
Appendix D DE3_HSTC Utility....................................................................................................108
Appendix E LVDS Termination Resistors ...................................................................................112
Additional Information..................................................................................................................114
Getting Help.................................................................................................................................114
Revision History ..........................................................................................................................114

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Chapter 1
Overview
1
This chapter presents the features and design characteristics of the DE3 board.
1.1 Introduction
The DE3 board has plenty of features that allow users to implement a wide range of designed
circuits. The Stratix® III device is capable of dealing with resource-consuming projects and
complex algorithm verification; the HSTC interface is equipped for high-speed inter-connection and
configurable I/O standards. The DDR2 SO-DIMM socket puts the experience of faster memory
access into practice, while the SD card socket provides the realization of data storage extension.
In addition, the DE3 board has an innovative stackable mechanism which allows users to assemble
DE3 boards into a powerful system as shown in Figure 1.1. The DE3 can also connect with multiple
daughter boards designed by Terasic in stock.
Figure 1.1 The stackable mechanism of the DE3 board
1.2 Layout and Components
Figure 1.2 and Figure 1.3 is the top and bottom view of the DE3 board. It depicts the layout of the
board and indicates the location of the connectors and key components. Users can refer to this
figure for relative location when the connectors and key components are introduced in the following
chapters.

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50MHz Oscillator
Expansion Header 2
SMA External Clock In
DDR2 SO-DIMM Socket
4 Slide Switches
7-Segment Displays
Altera USB Blaster
Controller Chipset
Altera EPCS128 / EPCS64
Configuration Device
USB Host/Device
Controller
HSTC Bottom Side
Enable
8 RGB LEDs
Expansion Header 1
4 Push-Button Switches
USB Blaster
Power ON/OFF Switch
Power Supply
Connector USB Device
SD Card Slot
USB Device
USB Host/Device SMA PLL Clock Out
Altera Stratix III
3SL340 (DE3-340)
or
3SL260 (DE3-260)
or
3SL150 (DE3-150)
Reconfigure Switch
CPU RESET Switch 8-Position Dip Switch
HSTC Connector C
HSTC Connector D
HSTC Connector B
HSTC Connector A
+12V Fan Connector
Figure 1.2 The DE3 board (Top view)

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Temperature Sensor
HSTC connector B
HSTC connector A
HSTC connector C
SD Card Slot
HSTC connector D
Figure 1.3. The DE3 board (Bottom view)
The following hardware is implemented on the DE3 board:
•Altera Stratix ® III FPGA device (3SL340/3SE260/3SL150)
•FPGA configuration interface:
 Built-in USB Blaster circuit for programming and user API control
 Altera Serial Configuration device – EPCS128/EPCS64
•Expansion Interface:
 8 HSTC connectors
 Two 40-pin Expansion Headers
•Memory Interface:
 DDR2 SO-DIMM socket
 SD Card socket

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•User I/O Interface:
 4 push-button switches
 4 slide switches
 1 eight position DIP switch
 2 seven-segment displays
 8 RGB LEDs
•Clock system
 One 50MHz oscillator
 2 SMA connectors for external clock input and PLL clock output
•Other interface
 1USB Host/Slave controller(1 three-ports USB Host/Device controller)
 1 temperature sensor chip for FPGA temperature measurement
1.3 Block Diagram of the DE3 Board
Figure 1.4 shows the block diagram of the DE3 board. To provide maximum flexibility for the users,
all key components are connected with the Stratix III FPGA device. Thus, users can configure the
FPGA to implement any system design.

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Power
1.1V
3.3V
5.0V
12V
GPIO 0
EPCS128
HOST
CON
x120
USB
Hi-Speed
OTG
x60
HSTC C
HSTC B
HSTC A
HSTC D
DDR2 SO-DIMM
x120 x120
x120
Clock IN x5
Clock OUT x5 Clock IN x5 Clock OUT x5
Clock IN x5
Clock OUT x5
1.5V
1.8V
2.5V
3.3V
VCCIO(BA,BB,BC,BD)
PLL_OUT
CLOCK_IN
Clock IN x5
Clock OUT x5
HOST
CON DEVICE CON
GPIO 1
x80
PLL OUT
CLOCK IN
50 MHz
OSC
OSC x6
EPM240
JTAG x4
USB
CON
7-Seg x 16
DIP Switch x 8
I
2
C x2
I
2
C x2
I
2
C x2
I
2
C x2
JVC x4
Select and
Power ON
I
2
C x2
Stratix III
EP3SL150F1152/
EP3SL340F1152/
EP3SE260F1152
Adjustable Voltage Signal
3.3V
Bank I/O Voltage
3.3V Signal
SD Card
Socket
Button Switch x4
Color LED x 24
Slider Switch x4
SD Card x 4
x120
Temperature
Sensor
Temp. Sensor x 6
Figure 1.4 Block diagram of the DE3 board

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Below is more detailed information regarding the blocks in Figure 1.4:
Stratix III FPGA
• EP3SL340
-338,000 logic elements (LEs)
-18,381K Total Memory Kbits
-526 18x18-bit Multipliers blocks
-12 phase-locked-loops (PLLs)
-
• EP3SE260
-254,400 logic elements (LEs)
-16,282K Total Memory Kbits
-768 18x18-bit Multipliers blocks
-12 phase-locked-loops (PLLs)
• EP3SL150
-142,000 logic elements (LEs)
-6,390K Total Memory Kbits
-384 18x18-bit Multipliers blocks
-8 phase-locked-loops (PLLs)
Serial Configuration device and USB Blaster circuit
•Altera’s EPCS128/EPCS64 Serial Configuration device
•On-board USB Blaster for programming and user API control
•Support JTAG mode
DDR2 SO-DIMM socket
•Up to 4GB capacity
•Share the same I/O bus with HSTC connector B
SD card socket
•Provides SPI and 1-bit SD mode for SD Card access

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Push-button switches
•6 push-button switches
-1 CPU Reset
-1 FPGA Reconfigure
-4 user-defined inputs
•Debounced by a Schmitt trigger circuit
•Normally high; generates one active-low pulse when the switch is pressed
Slide switches
•4 slide switches for user-defined inputs
•When a switch is set to the DOWN or UP position (i.e., close to or away from the edge of
the DE3 board), it causes logic 0 or 1, respectively.
Clock inputs
•50MHz oscillator
•1 SMA connector for PLL clock output
•1 SMA connector for external clock input
USB Host/Slave controller
•Complies fully with Universal Serial Bus Specification Rev. 2.0
•Support data transfer at high-speed, full-speed, and low-speed
•Support both USB host and device
•Three USB ports (one type mini-AB for host/device and two type A for host)
•Support Nios II with the Terasic driver
•Support Programmed I/O (PIO) and Direct Memory Access (DMA)
Eight 180-pin High Speed Terasic Connectors (HSTC) expansion headers
•4 male and 4 female connectors are on the top and the bottom of DE3 board, respectively.
•240 LVDS pairs of user-defined IO pins
•Configurable I/O voltage for 3.3V, 2.5V, 1.8V, and 1.5V
Two 40-pin expansion headers
•72 FPGA I/O pins, as well as 8 power and ground lines, are brought out to two 40-pin
expansion connectors
•40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives
•Share the same I/O pins with HSTC connector A

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Chapter 2
Using the DE3 Board
2
This chapter gives instructions for using the DE3 board and its components.
It is strongly recommended that users should read the Getting Started with the Altera DE3 board.pdf
before using the DE3 board. The document is located in the DE3_usermanual folder on the DE3
System CD. The contents of the document includes following:
1. Purpose of the DE3 Board
2. Scope of the DE3 Board and Supporting Material
3. Installing the Altera Design Software
4. Obtain a License File from Altera’s website
5. Setup the License File for Terasic Power Controller IP.
6. Install the USB Blaster Driver
7. Power up the DE3 Board
8. Programming the FPGA Device on the DE3 Board
2.1 Configuring the FPGA and Serial Configuration Device
 Programming the FPGAdevice:
The DE3 board has a built-in USB Blaster circuit, which allows users to program the FPGA
device using USB cable and Quartus II programmer in JTAG mode. Current configuration will
be lost when the power is turned off.
To download a configuration bit stream into the Stratix III FPGA, perform the following steps:
•Make sure that power is provided to the DE3 board
•Connect the USB cable supplied to the USB Blaster port of the DE3 board (see Figure 2.1)
•The FPGA can now be programmed in the Quartus II Programmer by selecting a
configuration bit stream file with the .sof filename extension.
Please refer to Getting Started with the Altera DE3 board.pdf for more detailed procedure of
FPGA programming.

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Quartus II
Programmer USB Blaster
Circuit JTAG Config Signals
JTAGUART
Figure 2.1 The JTAG configuration scheme
 Programming the serial configuration device :
The DE3 board contains a serial configuration device (U4) that stores configuration data for
the Stratix III FPGA. This configuration data is automatically loaded from the serial
configuration device chip into the FPGA when the board is powered up.
Since the Active Serial programming interface is not supported on the DE3 board, users will
need to use a Serial Flash Loader (SFL) function to program the serial configuration device via
the JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within the
FPGA that bridges the JTAG and flash interfaces. The SFL mega-function is available from
Quartus II software. Figure 2.2 shows the programming method when adopting a SFL solution.
Please refer to Appendix C Programming the Serial Configuration device for the basic
programming instruction on the serial configuration device. More detailed information on the
SFL mega-function can be found in Altera Application Note 370: Using the Serial Flash
Loader With the Quartus II Software.
Quartus II
Programmer USB Blaster
Circuit
Serial Configuration Device
JTAG EPCS
128
SFL Image
to bridge
The
JTAG and ASMI
JTAG ASMI
Figure 2.2. Programming a serial configuration device with the SFL solution

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2.2 JTAG Chain
This section describes how to setup the JTAG chain on DE3 board.
If the DE3 board is used without any board connected and all the positions in SW6 are switched to
OFF (i.e., down position), the JTAG-interface signals of all HSTC connectors are bypassed, as
shown in Figure 2.3.
When the top HSTC connector is not connected with any daughter board, the JTGA interface is
bypassed. If a daughter board is connected to the top HSTC connector, the JTAG interface will be
enabled automatically. Figure 2.4 shows the JTAG chain with a daughter board connected to the
DE3 board via top HSTC connector A. Note that if the daughter board does not use the JTAG
interface, the TDI and TOD pins on the daughter board must be shorted for the JTAG signals to pass
through.
A four position DIP switch (SW6) on DE3 board is used to control the JTAG interface signals of
bottom HSTC connectors. Table 2-1 indicates the detailed configurations of SW6. When the bottom
connector is connected with other DE3 board or an daughter board, users need to configure the
SW6 to connect the JTAG chain to other board accordingly. Figure 2.5 shows there are two DE3
boards stacked, and the JTAG chain is established through HSTA connector A, as shown in Figure
2.6.
Table 2-1. DIP switch (SW6) setting for JTAG interface on bottom HSTC connectors
Position Switch Setting
Turn OFF (lower position) Turn ON (upper position)
1 Bypass the JTAG interface on
the Bottom HSTC connector A(J2)
Enable the JTAG interface for
Bottom HSTC connector A(J2)
2 Bypass the JTAG interface on
the Bottom HSTC connector B(J4)
Enable the JTAG interface for
Bottom HSTC connector B(J4)
3 Bypass the JTAG interface on
the Bottom HSTC connector C(J6)
Enable the JTAG interface for
Bottom HSTC connector C(J6)
4 Bypass the JTAG interface on
the Bottom HSTC connector D(J8)
Enable the JTAG interface for
Bottom HSTC connector D(J8)

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TDI TDO
TDO
TDI
USB Blaster
Circuit
USB
Cable
Host
PC
Statix III FPGA
DE3 Board
OFF
OFF
OFF
OFF
SW6
HSTC Connector A
Bypassed
HSTC Connector B
Bypassed
HSTC Connector C
Bypassed
HSTC Connector D
Bypassed
2
3
4
1
Figure 2.3. JTAG chain for a standalone DE3 board
TDOTDI
TDI TDO
HSTC Connector
A Top
TDI TDO
TDO
TDI
USB
Blaster
Circuit
USB
Cable
Host
PC
Stratix III FPGA
Daughter
Board
DE3 Board
OFF
OFF
OFF
OFF
SW6
Figure 2.4. JTAG chain for a daughter board connected with DE3 board via top HSTC connector A

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Figure 2.5. The two DE3 boards stacked and the JTAG path is established through HSTC connector
A.
TDO TDI
HSTC Connector A
Bottom
TDI TDO
TDO
TDI
USB
Blaster
Circuit
USB
Cable
Host
PC
TDOTDI
HSTC Connector A
Top
TDI TDO
TDO
TDI
USB
Blaster
Circuit
SW6
1
2
3
4
ON
OFF
DE3 Board 1
DE3 Board 2
OFF
OFF
Stratix III FPGA
Stratix III FPGA
SW6
1
2
3
4
OFF
OFF
OFF
OFF
Figure 2.6. JTAG chain for two stacked DE3 boards

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2.3 Using the User I/O Interface
 Push-Button Switches:
The DE3 board provides four user-defined, one CPU reset, and one Reconfigure push-button
switches. The Reconfigure push-button is used to force a re-boot of the FPGA from the serial
configuration device.
The CPU reset push-button is an input to the Stratix III device. It is intended to be the master
reset signal for the FPGA designs loaded into the Stratix III device. The CPU reset push
-button is connected to the DEV_CLRn pin on the FPGA. The DEV_CLRn setting is a pin
option in the Quartus II software that users must enable to function the CPU reset as
DEV_CLRn instead of a standard I/O.
Each of these switches is de-bounced using a Schmitt Trigger circuit, as indicated in Figure
2.7. Each push-button provides a high logic level (3.3 volts) or a low logic level (0 volts)
when it is not pressed or pressed, respectively. Table A-1 shows the connections between the
push-buttons and the FPGA.
Push
PushPush
Push-
--
-button depressed
button depressedbutton depressed
button depressed
Before
BeforeBefore
Before
Debouncing
DebouncingDebouncing
Debouncing
Schmitt Triger
Schmitt TrigerSchmitt Triger
Schmitt Triger
Debounced
DebouncedDebounced
Debounced
Push
PushPush
Push-
--
-button released
button releasedbutton released
button released
Figure 2.7. Switch debouncing
 Slide Switches and DIPSwitch
There are also four slide switches and one 8-position DIP switch on the DE3 board. Each
switch is connected directly to a pin of the Stratix III FPGA. When a slide switch is in the
DOWN position (i.e., closest to the edge of the board) or the UP position, it provides a low
logic level (0 volts) or a high logic level (3.3 volts) to the FPGA, respectively. For 8-position
DIP switch, when a switch is in the DOWN position (closest to the edge of the board) or the
UP position, it provides a high logic level (3.3 volts) or a low logic level (0 volts) to the FPGA.
The connections between the slide switches and the FPGA are shown in Table A-2, whereas
Table A-3 shows the connections between the 8-position DIP switch and the FPGA.
 RGB LEDs
There are 8 RGB user-controllable LEDs on the DE3 board. Each LED has red, green, and

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blue color, driven directly by the Stratix III FPGA; The LED is turned on or off when the
associated pins are driven to a low or high logic level, respectively. A list of the pin names on
the FPGA that are connected to the RGB LEDs is given in Table A-4.
 7-Segment Displays
The DE3 board has two 7-segment displays. As indicated in the schematic in Figure 2.8, the
seven segments are connected to pins of the Stratix III FPGA. Applying a low or high logic
level to a segment to light it up or turns it off.
Each segment in a display is identified by an index listed from 0 to 6 with the positions given
in Figure 2.9. In addition, the decimal point is identified as DP. Table A-5 shows the mapping
of the FPGA pin assignments to the 7-segment displays.
3
7
9
8
5
10
4
2
HEX1_D0
M1
L1
L2
V4
P3
N4
Y11
W12
Y5
Y6
V3
HEX1
HEX0
HEX1_D1
HEX1_D2
HEX1_D3
HEX1_D4
HEX1_D5
HEX1_D6
HEX1_DP
HEX0_D0
HEX0_D1
HEX0_D2
HEX0_D3
HEX0_D4
HEX0_D5
HEX0_D6
HEX6_DP
N3
N1
W7
W8
W10 3
7
9
8
5
10
4
2
Figure 2.8. Connection between 7-segment displays and Stratix III FPGA
0
3
1
24
56
DP
Figure 2.9. Position and index of each segment in a 7-segment display
2.4 I/O Groups and V
CCIO
Control Circuit
Most of the user-defined I/O pins on Stratix III device are used for connectors. They are divided

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into four I/O groups, named A, B, C and D. Table 2-2 shows the relation between I/O groups and
connectors.
Table 2-2 The relation between I/O groups and connectors
I/O Group Connectors
A HSTC connector A, GPIO expansion headers (1)
B HSTC connector B, DDR2 SO-DIMM socket (2)
C HSTC connector C
D HSTC connector D
Note:
(1): HSTC connector A and GPIO expansion headers share the same I/O pins.
(2): HSTC connector B and DDR2 SO-DIMM socket share the same I/O pins.
Besides, the V
CCIO
level for these I/O groups of the FPGA can be configured, and many I/O
standards are supported. The I/O standard of each I/O group on DE3 board has to be set through a
software utility named “DE3 System Builder”. Such tool is intended to generate a top level
Quartus II project, which includes the power controller IP.
After the FPGA is programmed, the power controller IP will control the V
CCIO
control circuit to
provide desired V
CCIO
and V
CCPD
level to the FPGA, according to I/O standard selected by users as
indicated in Figure 2.10.With this feature, users can not only confirm if the V
CCIO
level meets the
design requirement, but also reduce the chance of the DE3 board and its daughter cards being
damaged.
Please refer to Stratix III handbook chapter 7. Stratix III Device I/O Features for more information
about the I/O standard and voltage levels of the Stratix III device. There will be more instructions
for DE3 System Builder in Chapter 4.
V CCIO Selection Power Control
IP
V CCIO to I/O bank
V CCIO Voltage-Level
Control Circuit
Figure 2.10. The architecture of Power Control IP and V
CCIO
control circuit

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Finally, there are LEDs located at the left-top corner of the DE3 board to indicate the V
CCIO voltage
level of each I/O group, as shown in Figure 2.11. For example, the LED VA1 and VA2 will be
turned on and off, respectively, when the V CCIO of I/O Group A is set to 2.5V. Please refer to Table
2-3 for the status of the LED indicator.
For I/O
Group A
For I/O
Group D
For I/O
Group C For I/O Group B
Power
ON/OFF
Indicator
Figure 2.11. The Voltage-Level Indicator for the I/O Groups
Table 2-3 The LEDs indicates the V CCIO voltage level of each IO Group.
LED
V CCIO Vx1(1) Vx0(1) OK
3.3V Light ON Light ON Light ON
2.5V Light ON Light OFF Light ON
1.8V Light OFF Light ON Light ON
1.5V Light OFF Light OFF Light ON
0V Light OFF Light OFF Light OFF
Note:
(1): Vx1 can be VA1, VB2, VC3, and VD1; Vx0 can be VA0, VB0, VC0, and VD0

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2.5 Using the HSTC Connectors
The High Speed Terasic Connector (HSTC) is a high speed expansion interface defined by Terasic
Technologies. The DE3 board is equipped with 8 HSTC connectors (J1 ~ J8), which can be used to
connect the Stratix III FPGA with daughter boards or the other DE3 boards. The detailed
specifications of the HSTC connector are described below:
 4 HSTC Connector Groups:
The eight HSTC connectors on the DE3 board are divided into 4 groups: HSTC A, HSTC B,
HSTC C, and HSTC D. Each group has a male and female HSTC connector on the top and
bottom side of the DE3 board, respectively. In addition, both the male and female HSTC
connector shares the same I/O pins except JTAG and I2C interface.
 I/O Distribution:
Each HSTC connector has 120 single-ended I/O (60 pair differential channels), 10
single-ended IO with 5 each for clock input and output (2 differential clock input and output
channel), JTAG and I2C bus. In addition, there are three banks on a HSTC connector. The I/O
pins used in differential transceiver channels on bank 1 support true LVDS inout. On bank 2
and 3, the I/O pins used in differential transmitter channels support emulated LVDS via a
termination resistor, and the differential receiver channels support true LVDS, as shown in.
Figure 2.12. In addition, there is a software utility named “DE3_HSTC” which can perform
the connection test between the I/O pins of the HSTC connector and Stratix III FPGA. The
detailed information about this utility can be found in Appendix D : DE3_HSTC Utility.
 Configurable I/O Standards:
The I/O pins of the HSTC connector support many I/O standards with different voltage level,
as the V
CCIO
supplied to FPGA bank I/O is configurable. Users can choose the I/O standard of
HSTC connector in the software utility “DE3 System Builder”.
 Compatible with HSMC Connector :
The HSTC connector is not only designed to be backward-compatible with the HSMC
products, but also provides more I/O pins for further connection. The pin assignments of bank
1 and 2 are exactly the same. The only difference between the HSMC and HSTC connector is
the pin assignments for bank 3. For HSTC connector, all the I/O pins on the bank 3 are well
defined. Figure 2.13 shows the I/O distribution of the bank3 for the HSTC and HSMC
connector. Table B-1 shows the pin compatible list for HSTC and HSMC connector.