Terasic TR4 User manual

TR4 User Manual
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TR4 User Manual
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March 30, 2017
CONTENTS
CHAPTER 1 OVERVIEW ........................................................................................................................................1
1.1 GENERAL DESCRIPTION ............................................................................................................................................1
1.2 KEY FEATURES..........................................................................................................................................................2
1.3 BOARD OVERVIEW....................................................................................................................................................3
1.4 BLOCK DIAGRAM......................................................................................................................................................4
1.5ASSEMBLY.................................................................................................................................................................8
CHAPTER 2 USING THE TR4 BOARD ................................................................................................................9
2.1 CONFIGURATION OPTIONS ........................................................................................................................................9
2.2 SETUP ELEMENTS....................................................................................................................................................16
2.3 STATUS ELEMENTS..................................................................................................................................................17
2.4 GENERAL USER INPUT/OUTPUT ..............................................................................................................................18
2.5 HIGH-SPEED MEZZANINE CARDS............................................................................................................................20
2.6 GPIO EXPANSION HEADERS ...................................................................................................................................32
2.7 DDR3SO-DIMM...................................................................................................................................................36
2.8 CLOCK CIRCUITRY ..................................................................................................................................................40
2.9 PCI EXPRESS ..........................................................................................................................................................45
2.10 FLASH MEMORY ...................................................................................................................................................48
2.11 SSRAM MEMORY.................................................................................................................................................51
2.12 TEMPERATURE SENSOR AND FAN ..........................................................................................................................53
2.13 POWER..................................................................................................................................................................53
2.14 SECURITY..............................................................................................................................................................54
2.15 USING EXTERNAL BLASTER..................................................................................................................................54
CHAPTER 3 CONTROL PANEL ..........................................................................................................................56
3.1 CONTROL PANEL SETUP ..........................................................................................................................................56
3.2 CONTROLLING THE LEDS.......................................................................................................................................60
3.3 SWITCHES AND PUSH-BUTTONS..............................................................................................................................61
3.4 MEMORY CONTROLLER...........................................................................................................................................62
3.5 TEMPERATURE MONITOR ........................................................................................................................................65
3.6 PLL ........................................................................................................................................................................66
3.7 HSMC ....................................................................................................................................................................67
3.8 FAN .........................................................................................................................................................................68

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3.9 INFORMATION .........................................................................................................................................................69
CHAPTER 4 TR4 SYSTEM BUILDER ................................................................................................................71
4.1 INTRODUCTION .......................................................................................................................................................71
4.2 GENERAL DESIGN FLOW.........................................................................................................................................72
4.3 USING TR4 SYSTEM BUILDER.................................................................................................................................73
CHAPTER 5 EXAMPLES OF ADVANCED DEMONSTRATION ....................................................................83
5.1 BREATHING LEDS...................................................................................................................................................83
5.2 EXTERNAL CLOCK GENERATOR ..............................................................................................................................84
5.3 HIGH SPEED MEZZANINE CARD (HSMC) ...............................................................................................................90
5.4 DDR3 SDRAM (1GB) ...........................................................................................................................................92
5.5 DDR3 SDRAM (4GB) ...........................................................................................................................................96
ADDITIONAL INFORMATION ...................................................................................................................................100

TR4 User Manual
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March 30, 2017
Chapter 1
Overview
This chapter provides an overview of the TR4 Development Board and details the components and
features of the board.
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1. .1 1 G Ge en ne er ra al l D De es sc cr ri ip pt ti io on n
The TR4 Development Board provides the ideal hardware platform for system designs that demand
high-performance, serial connectivity, and advanced memory interfacing. Developed specifically to
address the rapidly evolving requirements in many end markets for greater bandwidth, improved
jitter performance, and lower power consumption, the TR4 is powered by the Stratix® IV GX
device and supported by industry-standard peripherals, connectors and interfaces that offer a rich set
of features that is suitable for a wide range of compute-intensive applications.
The advantages of the Stratix® IV GX FPGA platform with integrated transceivers have allowed
the TR4 to be fully compliant with version 2.0 of the PCI Express standard. This will accelerate
mainstream development of PCI Express-based applications and enable customers to deploy
designs for a broad range of high-speed connectivity applications.
The TR4 is supported by multiple reference designs and six High-Speed Mezzanine Card (HSMC)
connectors that allow scaling and customization with mezzanine daughter cards. For large-scale
ASIC prototype development, multiple TR4s can be stacked together to create an
easily-customizable multi-FPGA system.

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1. .2 2 K Ke ey y F Fe ea at tu ur re es s
Featured Device
Altera Stratix® IV GX FPGA (EP4SGX230C2/EP4SGX530C2)
Configuration and Set-up Elements
Built-in USB Blaster circuit for programming
Fast passive parallel (FPP) configuration via MAX II CPLD and FLASH
Components and Interfaces
Six HSMC connectors (two with transceiver support)
Two 40-pin GPIO expansion headers (shares pins with HSMC Port C)
Two external PCI Express 2.0 (x4 lane) connectors
Memory
DDR3 SO-DIMM socket (4GB Max)
64MB FLASH
2MB SSRAM
General User Input/Output:
Four LEDs
Four push-buttons
Four slide switches
Clock system
On-board 50MHz oscillator
Three on-board programmable PLL timing chips
SMA connector pair for differential clock input
SMA connector pair for differential clock output
SMA connector for external clock input
SMA connector for clock output

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Other
Temperature sensor
FPGA cooling fan
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1. .3 3 B Bo oa ar rd d O Ov ve er rv vi ie ew w
Figure 1-1 and Figure 1-2 show the top and bottom view of the TR4 board. It depicts the layout of
the board and indicates the location of the connectors and key components. Users can refer to these
figures for relative location when the connectors and key components are introduced in the
following chapters.
Figure 1-1 TR4 Board View (Top)

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Figure 1-2 TR4 Board View (Bottom)
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1. .4 4 B Bl lo oc ck k D Di ia ag gr ra am m
Figure 1-3 shows the block diagram of the TR4 board. To provide maximum flexibility for the
users, all key components are connected with the Stratix IV GX FPGA device, allowing the users to
implement any system design.

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Figure 1-3 TR4 Block Diagram
Below is more detailed information regarding the blocks in Figure 1-3.
Stratix IV GX FPGA
EP4SGX230C2
228,000 logic elements (LEs)
17,133 total memory Kb
1,288 18x18-bit multipliers blocks
2 PCI Express hard IP blocks

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744 user I/Os
8 phase locked loops (PLLs)
EP4SGX530C2
531,200 logic elements (LEs)
27,376K total memory Kb
1,024 18x18-bit multipliers blocks
4 PCI Express hard IP blocks
744 user I/Os
8 phase locked loops (PLLs)
Configuration Device and USB Blaster Circuit
MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP)
configuration
On-board USB Blaster for use with the Quartus II Programmer
Programmable PLL timing chip configured via MAX II CPLD
Supports JTAG mode
Memory Devices
64MB Flash (32M x16) with a 16-bit data bus
2MB SSRAM (512K x 32)
DDR3 SO-DIMM Socket
Up to 4GB capacity
Maximum memory clock rate at 533MHz
Theoretical bandwidth up to 68Gbps
LEDs
4 user-controllable LEDs
Active-low|

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Push-buttons
4 user-defined inputs
Active-low
Slide Switches
4 slide switches for user-defined inputs
Logic low for DOWN position; Logic high for UP position
On-Board Clocking Circuitry
50MHz oscillator
SMA connector pair for differential clock inputs
SMA connector pair for differential clock outputs
SMA connector for external clock input
SMA connector for clock output
Two PCI Express x4 Edge Connectors
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Support downstream mode
Six High Speed Mezzanine Card (HSMC) Connectors
Two HSMC ports include 16 pairs of CDR-based transceivers at data rates of up to 6.5Gbps
Among HSMC Port A to D, there are 55 true LVDS TX channels to 1.6Gbps and 17
emulated LVDS TX channels up to 1.1Gbps whereas there are 9 additional TX channels from
HSMC Port E.
Configurable I/O standards - 1.5V, 1.8V, 2.5V, 3.0V
Two 40-pin GPIO Expansion Headers

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72 FPGA I/O pins; 4 power and ground lines
Shares pins with HSMC Port C
Configurable I/O standards: 1.5V, 1.8V, 2.5V, 3.0V
Power
Standalone DC 19V input
Other
Temperature Sensor
Cooling Fan
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1. .5 5 A As ss se em mb bl ly y
Attach the included rubber (silicon) foot stands, as shown in Figure 1-4, to each of the four copper
stands on the TR4 board.
Figure 1-4 Mount Silicon Foot Stands

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Chapter 2
Using the TR4 Board
This chapter gives instructions for using the TR4 board and its components.
It is strongly recommended that users read the TR4 Getting Started Guide.pdf before operating the
TR4 board. The document is located in the Usermanual folder on the TR4 System CD. The contents
of the document include the following:
Introduction to the TR4 Development Board
TR4 Development Kit Contents
Key Features
Before You Begin
Software Installation
Development Board Setup
Programming the Stratix IV GX Device
Programming through Flash
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2. .1 1 C Co on nf fi ig gu ur ra at ti io on n O Op pt ti io on ns s
JTAG FPGA Programming with USB-Blaster
The USB-blaster is implemented on the TR4 board to provide a JTAG configuration through the
on-board USB-to-JTAG configuration logic through the type-B USB connector, an FTDI USB 2.0
PHY device, and an Altera MAX II CPLD. For this programming mode, configuration data will be
lost when the power is turned off.
To download a configuration bit stream into the Stratix IV GX FPGA, perform the following steps:

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Make sure that power is provided to the TR4 board.
Open JP7 to bypass the JTAG interface of the HSMC if it won’t be used.
Connect the USB cable supplied directly to the USB Blaster port of the TR4 board (see
Figure 2-1).
The FPGA can now be programmed in the Quartus II Programmer by selecting a
configuration bit stream file with the .sof filename extension.
If users need to use the JTAG interface on HSMC, please refer to Section 2.2 for detailed
HSMC JTAG switch settings.
Figure 2-1 JTAG Configuration Scheme
JTAG FPGA Programming with External Blaster
The TR4 board supports JTAG programming over external blaster via J2. To use this interface,
users need to solder a 2x5 pin connector (2.54mm pitch) to J2. Make sure JP7 is open to bypass the
JTAG interface of HSMC.
Flash Programming
The TR4 development board contains a common Flash interface (CFI) memory to meet the
demands for larger FPGA configurations. The Parallel Flash Loader (PFL) feature in MAX II
devices provides an efficient method to program CFI flash memory devices through the JTAG
interface and the logic to control configuration from the flash memory device to the Stratix IV GX
FPGA. Figure 2-2 depicts the connection setup between the CFI flash memory, Max II CPLD, and
Stratix IV GX.

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Figure 2-2 Flash Programming Scheme
Programming Flash Memory using Batch File
The TR4 provides a batch file (program_Flash.bat) to limit the steps that are taken when users
program the flash memory on the TR4.
Software Requirements:
Quartus II 11.1 or later
Nios II IDE 11.1 or later
Program_Flash folder contents:
Program_Flash.bat
Program_Flash.pl
Program_Flash.sh
tr4_default_flash_loader.sof
boot_loader_cfi.srec
Before you use the program_Flash.bat batch file to program the flash memory, make sure the TR4 is

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turned on and USB cable is connected to the USB blaster port (J4). In addition, place the .sof
and .elf file you wish to program/convert in the Program_Flash directory.
Programming Flash Memory with .sof using Program_Flash.bat
1. Launch the program_Flash.bat batch file from the directory (\demonstrations\TR4_<Stratix
device>\ TR4_Default_Flash_Loaderr\Program_Flash) of the TR4 system CD-ROM.
2. The Flash program tool shows the menu options.
Figure 2-3 Flash Program Tools
3. Select option 2.

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Figure 2-4 Option 2
4. Enter the .sof file name to be programmed onto the flash memory.
Figure 2-5 Enter .sof Name to Program

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5. The following lines will appear during Flash programming: ‘Extracting Option bits SREC’,
‘Extracting FPGA Image SREC’, and ‘Deleting intermediate files’. If these lines don’t appear on
the windows command, programming on the flash memory is not successfully set up. Please make
sure Quartus II 11.1 and Nios II 11.1 IDE or later is used.
Figure 2-6 Loading .sof File
6. Erasing Flash.

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Figure 2-7 Erasing Flash
7. Programming Flash.
Figure 2-8 Programming Flash
8. Programming complete.

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Figure 2-9 Programming Flash complete
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2. .2 2 S Se et tu up p E El le em me en nt ts s
JTAG Control DIPSwitch
The TR4 supports individual JTAG interfaces on each HSMC connector. This feature allows users
to extend the JTAG chain to daughter cards or additional TR4s. Before using this interface, JP7
needs to be shorted to enable the JTAG interface on all the HSMC connectors.
The JTAG signals on each HSMC connector can be removed or included in the active JTAG chain
via DIP switches. Table 2-1 lists the position of the DIP switches and their associated interfaces.
Note that if the JTAG interface on HSMC connector is enabled, make sure that the active JTAG
chain must be a closed loop or the FPGA may not be detected. Section 2.5 will give an example on
how to extend the JTAG interface to a daughter card. Also, a document named
Using_Mult-TR4_system.pdf in TR4 system CD shows how to connect the JTAG interface on two
stacked TR4 boards.

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Table 2-1 JTAG Control
Components
Name
Description
Default
SW4
position 1
HSMCA_TOP
ON: HSMA TOP in-chain OFF: Bypass HSMA TOP
OFF
position 2
HSMCB_TOP
ON: HSMB TOP in-chain OFF: Bypass HSMB TOP
OFF
position 3
HSMCC_TOP
ON: HSMC TOP in-chain OFF: Bypass HSMC TOP
OFF
position 4
HSMCD_TOP
ON: HSMD TOP in-chain OFF: Bypass HSMD TOP
OFF
SW5
position 1
HSMCA_BOT
ON: HSMA BOT in-chain OFF: Bypass HSMA BOT
OFF
position 2
HSMCB_BOT
ON: HSMB BOT in-chain OFF: Bypass HSMB BOT
OFF
position 3
HSMCC_BOT
ON: HSMC BOT in-chain OFF: Bypass HSMC BOT
OFF
position 4
HSMCD_BOT
ON: HSMD BOT in-chain OFF: Bypass HSMD BOT
OFF
SW6
position 1
HSMCE_TOP
ON: HSME TOP in-chain OFF: Bypass HSME TOP
OFF
position 2
HSMCF_TOP
ON: HSMF TOP in-chain OFF: Bypass HSMF TOP
OFF
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2. .3 3 S St ta at tu us s E El le em me en nt ts s
The TR4 includes status LEDs. Please refer Table 2-2 for the status of the LED indicator.
Table 2-2 LED Indicators
Board
Reference
LED name
Description
D13
HSMC Port E present
These LEDs are lit when HSMC Port A/B/C/D/E/F have a
board or cable plugged-in such that pin 160 becomes
grounded.
D14
HSMC Port D present
D15
HSMC Port A present
D20
HSMC Port C Present
D27
HSMC Port B Present
D28
HSMC Port F Present
D16
USB Blaster Circuit
This LED is lit when the USB blaster circuit transmits or
receives data.
D17
MAX_LOAD
This LED is lit when the FPGA is being actively configured.