Acrosser Technology AR-B2002 User manual

AR-B2002 User’s Guide
AR-B2002 Gaming I/O board
PCI I/O board with discrete I/O, battery backup SRAM,
Timer, power off intrusion event logger and Protect-U
Edition: 2.1
Book Number: AR-B2002-07.10.20
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AR-B2002 User’s Guide
@Copyright 2006
All Rights Reserved.
Manual first edition October 31, 2006
The information in this document is subject to change without prior notice in order to improve reliability,
design and function and does not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential
damages arising out of the use or inability to use the product or documentation, even if advised of the
possibility of such damages.
This document contains proprietary information protected by copyright. All rights are reserved. No part of
this
Manual may be reproduced by any mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.
Trademarks
AR-B2002 is registered trademarks Gaming and Multimedia Acrosser, IBM PC is a registered trademark
of International Business Machines Corporation. Pentium is a registered trademark of Intel Technologies
Inc. Award is registered trademarks of Award Software International, Inc. Other product names mentioned
herein are used for identification purposes only and may be trademarks and/or registered trademarks of
their respective companies.
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AR-B2002 User’s Guide
Content
Content ...................................................................................................... 3
Introduction............................................................................................... 4
1.1 Specification ...................................................................................................... 4
1.2 What You Have ................................................................................................. 5
Installation................................................................................................. 6
2.1 Function Block Diagram .................................................................................... 6
2.2 AR-B2002 Placement........................................................................................ 7
2.3 100 Pins SCSI II Connector (CN2).................................................................... 8
2.4 Universal PCI Gold Finger................................................................................. 9
2.5 ISP FPGA Connector (CN1).............................................................................. 9
2.6 10-Pin Serial Connector (COM1) ...................................................................... 9
2.7 DIP Switch (SW1) ........................................................................................... 10
2.8 AGC as System controller ............................................................................... 10
2.9 SRAM Memory................................................................................................ 10
2.10 SRAM backup battery (J4) .............................................................................11
2.12 RTC & Intrusion Logger Batery (J3) ...............................................................11
2.13 I/O Buffer........................................................................................................11
2.14 ProtectU, Intrusion Logger, RTC ....................................................................11
AGC Register Description...................................................................... 12
3.1 PCI Configuration Register ..................................................................... 12
3.2 SRAM Memory Address Map.................................................................. 16
3.3 I/O-Interface Address Map ...................................................................... 16
Software Utility, Driver, and Library....................................................... 25
4.1 Windows Driver and Libraries ................................................................. 25
4.2 Linux Driver and Libraries ....................................................................... 39
AGA Functions........................................................................................ 50
5.1 Protect-U System.................................................................................... 50
5.2 Data Sets ................................................................................................ 51
5.3 Using AGA Functions .............................................................................. 52
5.4 AGA-API Library Introduction.................................................................. 53
5.5 AGA-API Library ..................................................................................... 55
5.6 Error Messages ...................................................................................... 71
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AR-B2002 User’s Guide
1Introduction
1.1 Specification
Model number: AR-B2002
Description: PCI bus Gaming I/O boards with 96-bit discrete inputs or 88-bit
discrete outputs, Timer, Protect-U, SRAM and power off intrusion event logger
Dimension: Half Size PCI card
Number of I/O: Programmable 96 bits Input or 88 bits output
Digital Input:
1. Compatibility: TTL level
2. Digital Level input:
A. Input high: 2 to 5.25V
B. Input low: 0 to 0.8V
3. Interrupt: change-of-state detection on all input bits
4. After Power On: all 96 I/O are defined as inputs
5. Intrusion logger:
A. Microchip PIC16F687A SSOP
B. 8 inputs on Port-A are monitored by logger processor with latest 16
events
C. Real time clock for time stamp
Digital output:
1. Output status software readable
2. TTL level output:
A. Output high: 2 to 3.3V
B. Output low: 0 to 0.8V
3. Output driving current:
A. Source: 15mA
B. Sink: 48mA
DIP switch: 8-bit DIP switch and software readable
Programmable Timer:
1. Four independent 16 bit programmable timer up to 65536 second or ~ 18 hour
2. Timer resolution: 1 second (default), 1ms or 1us
3. Interrupt: support interrupt after reach zero state by countdown
SRAM:
1. 512MB battery backup SRAM
2. Divided in to 64 banks & every bank has 8 Kbyte memory size
3. Access through PCI bus
Security: Protect-U software protection through 10-pin serial pin header
Connector: 100-pin SCSI II connector
Header: RS-232 10-pin pin header for Protect-U and Intrusion Data
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AR-B2002 User’s Guide
1.2 What You Have
These accessories are included with the system. Before you begin installing your
AR-B2002 board, please make sure that the following items have been included inside
the AR-B2002 package.
•The quick setup manual
•AR-B2002 PCI board
•Driver, Software utility & Manual CD
•One RS-232 serial ports cable with bracket
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AR-B2002 User’s Guide
2Installation
This chapter describes how to install the AR-B2002. At first, the Function diagram and
layout of AR-B2002 is shown, and the unpacking information that you should be careful
is described. The jumpers and switches setting for the AR-B2002’s configuration
2.1 Function Block Diagram
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AR-B2002 User’s Guide
2.2 AR-B2002 Placement
I/O Buffer
SW1
COM1
A
GA
100 PIN SCSI II Connector (CN2)
BAT1
BAT2
AGC SRAM
CN1
Universal PCI Gold Finger
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2.3 100 Pins SCSI II Connector (CN2)
1
2
3
4
..
..
..
51
52
53
54
..
..
..
..
..
..
47
48
49
50
..
..
..
97
98
99
100
Pin
No Function
Pin
No Function
Pin
No Function Pin No Function
1 Port-J I/O0 26 Port-E I/O0 51 Port-K I/O0 76 Port-F I/O0
2 Port-J I/O1 27 Port-E I/O1 52 Port-K I/O1 77 Port-F I/O1
3 Port-J I/O2 28 Port-E I/O2 53 Port-K I/O2 78 Port-F I/O2
4 Port-J I/O3 29 Port-E I/O3 54 Port-K I/O3 79 Port-F I/O3
5 Port-J I/O4 30 Port-E I/O4 55 Port-K I/O4 80 Port-F I/O4
6 Port-J I/O5 31 Port-E I/O5 56 Port-K I/O5 81 Port-F I/O5
7 Port-J I/O6 32 Port-E I/O6 57 Port-K I/O6 82 Port-F I/O6
8 Port-J I/O7 33 Port-E I/O7 58 Port-K I/O7 83 Port-F I/O7
9 Port-B I/O0 34 Port-A I/O0 59 Port-H I/O0 84 Port-D I/O0
10 Port-B I/O1 35 Port-A I/O1 60 Port-H I/O1 85 Port-D I/O1
11 Port-B I/O2 36 Port-A I/O2 61 Port-H I/O2 86 Port-D I/O2
12 Port-B I/O3 37 Port-A I/O3 62 Port-H I/O3 87 Port-D I/O3
13 Port-B I/O4 38 Port-A I/O4 63 Port-H I/O4 88 Port-D I/O4
14 Port-B I/O5 39 Port-A I/O5 64 Port-H I/O5 89 Port-D I/O5
15 Port-B I/O6 40 Port-A I/O6 65 Port-H I/O6 90 Port-D I/O6
16 Port-B I/O7 41 Port-A I/O7 66 Port-H I/O7 91 Port-D I/O7
17 Port-I I/O0 42 Port-G I/O0 67 Port-C I/O0 92 Port-L I/O0
18 Port-I I/O1 43 Port-G I/O1 68 Port-C I/O1 93 Port-L I/O1
19 Port-I I/O2 44 Port-G I/O2 69 Port-C I/O2 94 Port-L I/O2
20 Port-I I/O3 45 Port-G I/O3 70 Port-C I/O3 95 Port-L I/O3
21 Port-I I/O4 46 Port-G I/O4 71 Port-C I/O4 96 Port-L I/O4
22 Port-I I/O5 47 Port-G I/O5 72 Port-C I/O5 97 Port-L I/O5
23 Port-I I/O6 48 Port-G I/O6 73 Port-C I/O6 98 Port-L I/O6
24 Port-I I/O7 49 Port-G I/O7 74 Port-C I/O7 99 Port-L I/O7
25 Ground 50 Ground 75 Ground 100 Ground
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AR-B2002 User’s Guide
2.4 Universal PCI Gold Finger
The 32 Bit universal PCI Gold Finger support +5V and +3V PCI Slot and by Installation,
the position of connector key must be correct. Be careful, the wrong position of
installation can damage the system!
2.5 ISP FPGA Connector (CN1)
This Pin Header will be used to program the logics of FPGA
PIN NO. DESCRIPTION
1 +3V
2 TDO
3 TDI
4 NC
5 NC
6 TMS
7 GROUND
8 TCK
+5V Connector Key
+3.3V Connector Key
1
8
2.6 10-Pin Serial Connector (COM1)
Serial pin header will be used as user interface for ProtectU, Intrusion Logger and RTC
function on this system.
PIN NO. DESCRIPTION
10
9
2
1
1 N.C
2 N.C
3 RECEIVE DATA (RXD)
4 N.C
5 TRANSMIT DATA (TXD)
6 N.C
7 N.C
8 N.C
9 GROUND
10 GROUND
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AR-B2002 User’s Guide
2.7 DIP Switch (SW1)
The user can use DIP Swith for application software setting. It is 8 bit switch and
software readable.
2.8 AGC as System controller
We have design a AGC chip by ourself to realize all functions in AR-B2002. This chip will
work as controller for whole system. Following functions are integrated in AGC chip :
•PCI interface
•SRAM controller
•I / O controller
•Interruppt Managemant
•Programable Timer controller
•Dip-Switch logics
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
Bit 5
Bit 6 Bit 7
2.9 SRAM Memory
AR-B2002 give the user the possibility to backup the data in on-board SRAM. It’s 512
Kbyte SRAM and divided in 64 banks. SRAM will be powered with Battery (BAT1) in
standby mode.
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AR-B2002 User’s Guide
2.10 SRAM backup battery (J4)
Battery on AR-B2002 will be used for SRAM data backup in standby mode, it mean the
data on SRAM will be not lose as long as the Battery has enough power.
2.12 RTC & Intrusion Logger Batery (J3)
Battery on AR-B2002 will be used to supply power for RTC and Intrusion Logger function
when the system power is off.
2.13 I/O Buffer
I/O Buffer on AR-B2002 has the function to buffer 96 I/O signals, so that it has enough
current and TTL Levels.
2.14 ProtectU, Intrusion Logger, RTC
AR-B2002 integrates the functions ProtectU, Intrusion Logger, RTC and I-Button.
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AR-B2002 User’s Guide
3AGC Register Description
This chapter describes the function’s Register inside an AGC chip. To program the
application’s software, user must have the know-how of these Registers.
3.1 PCI Configuration Register
32 bit Register
PCI CFG
Register Offset
Address 31
24
23
16
15
8
7
0
PCI
Readable PCI Writable
00h Device ID Vendor ID Yes No
04h Status Command Yes No
08h Class Code Revision ID Yes No
0Ch BIST Header Type Latency Timer Cache Line Size Yes No
10h PCI Base Address 0 for Memory Mapped Configuration Registers Yes Yes
14h PCI Base Address 1 for I/O Mapped Configuration Registers Yes Yes
18h PCI Base Address 2 (Not Supported) No No
1Ch PCI Base Address 3 (Not Supported) No No
20h PCI Base Address 4 (Not Supported) No No
24h PCI Base Address 5 (Not Supported) No No
28h Cardbus CIS Pointer (Not Supported) Yes No
2Ch Subsystem ID Subsystem Vendor ID Yes No
30h PCI Base Address for Local Expansion ROM (Not Supported) Yes No
34h Reserved No No
38h Reserved No No
3Ch Max_Lat Min_Gnt Interrupt Pin Interrupt Line Yes Yes / No
Vendor ID Register (00h : 01h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
15 : 0 Vendor ID. Identifies manufacturer of the device. Yes No 1573h
Device ID Register (02h : 03h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 16 Device ID. Identifies particular device. Yes No 0000h
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Command Register (04h : 05h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 I/O Space. Value of 1 allows device to respond to I/O space
accesses. Yes No 1
1 Memory Space. Value of 1 allows device to respond to
memory space accesses Yes No 1
2 Master Enable. Value of 0 disables device from generating
bus master accesses. Not Supported Yes No 0
3 Special Cycle. Not Supported. Yes No 0
4 Memory Write/Invalidate. Not Supported. Yes No 0
5 VGA Palette Snoop. Not Supported. Yes No 0
6 Parity Error Response. Not Supported. Yes N o 0
7 Wait Cycle Control. Not Supported. Yes No 0
8 SERR# Enable. Not Supported. Yes No 0
9 Fast Back-to-Back Enable. Not Supported. Yes No 0
15 : 10 Reserved Yes No 0
Status Register (06h : 07h)
Bit Field Description Software
Readable Software Writable Value after Reset
22 : 16 Reserved Yes No 0
23 Fast Back-to-Back Capable. Not Supported. Yes No 0
24 Master Data Parity Error Detected. Not supported Yes No 0
26 : 25 DEVSEL Timing. Value of 01 is Slow. Yes No 10
27 Target Abort. 1 if Device has Signal Target Abort. Yes Yes 0
28 Received Target Abort. Not Supported. Yes No 0
29 Received Master Abort. Not Supported. Yes No 0
30 Signaled System Error. Not Supported. Yes N o 0
31 Detected Parity Error. Not Supported. Yes No 0
Revision ID Register (08h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
7 : 0 Revision ID. Identifies particular device. Yes No 2002
Class Code Register (09h : 0Bh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
15 : 8 Specific Register Level Programming Interface (00h). No
interface defined. Yes No 00
23 : 16 Subclass Encoding (80h). Other bridge device. Yes No 80h
31 : 24 Base Class Encoding. Other bridge Device. Yes No 06h
Cache Line Size Register (0Ch)
Bit Field Description Software
Readable
Software
Writable Value after Reset
7 : 0
System Cache Line Size (in units of 32-bit words). Can be
written and read; however, the value has no effect on
operation of chip.
Yes No 0
Latency Timer Register (0Dh)
Bit Field Description Software Software Value after
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AR-B2002 User’s Guide
Readable Writable Reset
15 : 8 PCI Latency Timer. Not Supported. Yes No 0
Header Type Register (0Eh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
22 : 16
Configuration Layout Type. Specifies layout of bits 10h
through 3Fh in configuration space. Only one encoding 0 is
defined. All other encodings are reserved.
Yes No 0
23
Header Type. Value of 1 indicates multiple functions. Value of
0 indicates a single
function.
Yes No 0
Built-In Self Test Register (0Fh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 24 Built-In Self Test. Value of 0 indicates that device has passed
its test. Not Supported. Yes No 0
Base Address 0 Registers for Memory Accesses to Local Configuration (10h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0
Memory Space Indicator. Value of 0 indicates register maps
into Memory space. Value of 1 indicates register maps into I/O
space.
Yes No 0
2 : 1
Location of register:
00 = Locate anywhere in 32 bit memory address space
01 = Locate below 1 MB memory address space
10 = Locate anywhere in 64 bit memory address space
11 = Reserved
Yes No 0
3 Prefetchable. Value of 1 indicates no side effect on reads. Ye s No 0
6 : 4 Memory Base Address. Memory base address for access to
local configuration registers (default 8 Kbytes). Yes No 0
31 : 7 Memory Base Address. Memory base address for access to
local configuration registers. Yes Yes 0
Base Address 1 Register for I/O Accesses to Local Configuration (14h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0
Memory Space Indicator. Value of 0 indicates register maps
into Memory space. Value of 1 indicates register maps into
I/O space.
Yes No 1
1 Reserved Yes No 0
6 : 2 I/O Base Address. Base address for I/O access to local
configuration registers (default 128 bytes). Yes No 0
31 : 7 I/O Base Address. Base address for I/O access to local
configuration registers Yes Yes 0
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AR-B2002 User’s Guide
Base Address 2 Registers (18h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Not Supported Yes No 0
Base Address 3 Registers (1Ch)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Not Supported Yes No 0
Base Address 4 Registers (20h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Not Supported Yes No 0
Base Address 5 Registers (24h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Not Supported Yes No 0
Cardbus CIS Pointer Registers (28h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Cardbus Information Structure Pointer for PCMCIA. Not
Supported. Yes No 0
Subsystem Vendor ID Registers (2Ch)
Bit Field Description Software
Readable
Software
Writable Value after Reset
15 : 0 Subsystem Vendor ID. (Unique add-in board Vendor ID) Yes Yes 00
Subsystem ID Registers (2Eh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 16 Subsystem ID. (Unique add-in board Device ID) Yes Yes 00
Base Address for Local Expansion ROM Registers (30h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 0 Not Supported Yes No 0
Interrupt Line Registers (3Ch)
Bit Field Description Software
Readable
Software
Writable Value after Reset
7 : 0 Interrupt Line Routing Value indicates which system interrupt
controller(s) input the interrupt line of device is connected to. Yes Yes 0
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AR-B2002 User’s Guide
Interrupt Pin Registers (3Dh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
15 : 8
Interrupt Pin Register indicates the interrupt pin that the
device uses. The following values are decoded:
0 = No Interrupt Pin
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
Note: supports only one PCI interrupt (INTA#).
Yes No 1
Min Gnt Registers (3Eh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
23 : 16
Min Gnt. Specifies needed length of Burst period for the
device, assuming a clock rate of 33 MHz. Value is a multiple
of 1/4 µs increments. Not Supported.
Yes No 0
Max Lat Registers (3Fh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
31 : 24
Max Lat. Specifies how often the device must gain access to
PCI bus. Value is a multiple of 1/4 µs increments. Not
Supported.
Yes No 0
3.2 SRAM Memory Address Map
The following table shows the SRAM Memory Address map (max. 8 KB) and their offset
addresses, relative to the “PCI Base Address 0”. To access SRAM memory, the user
must use Byte-Access command.
32 bit Data width
Memory Offset
Address
31
24
23
16
15
8
7
0
Software
Readable Software Writable
00h Byte 3 Byte 2 Byte 1 Byte 0 Yes Yes
04h Byte 7 Byte 6 Byte 5 Byte 4 Yes Yes
08h Byte 11 Byte 10 Byte 9 Byte 8 Yes Yes
.... .... .... .... .... Yes Yes
.... .... .... .... .... Yes Yes
1FF4h Byte 8183 Byte 8182 Byte 8181 Byte 8180 Yes Yes
1FF8h Byte 8187 Byte 8186 Byte 8185 Byte 8184 Yes Yes
1FFCh Byte 8191 Byte 8190 Byte 8189 Byte 8188 Yes Yes
3.3 I/O-Interface Address Map
The following table shows the I/O Address map, including descriptions and their offset
addresses relative to the “PCI Base Address1”.
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AR-B2002 User’s Guide
32 bit Register
I/O Offset
Address
31
24
23
16
15
8
7
0
Software
Readable Software Writable
00h Reserved SRAM Bank
Yes Yes
04h Reserved DIP Switch Yes No
08h Reserved Interrupt & Timer Enable Register Yes Yes
0Ch Reserved I/O & Timer Interrupt Source
Registers Ye s No
10h Reserved Port BCD Mode Yes Ye s
14h Reserved Port A Data Yes Yes
18h Reserved Port B Data Ye s Yes
1Ch Reserved Port C Data Yes Yes
20h Reserved Port D Data Yes Yes
24h Reserved Port EFGH Mode Yes Yes
28h Reserved Port E Data Yes Yes
2Ch Reserved Port F Data Yes Ye s
30h Reserved Port G Data Yes Yes
34h Reserved Port H Data Yes Yes
38h Reserved Port IJKL Mode Yes Ye s
3Ch Reserved Port I Data Ye s Yes
40h Reserved Port J Data Yes Yes
44h Reserved Port K Data Yes Yes
48h Reserved Port L data Yes Yes
4Ch TIMER-A Register Yes Yes
50h TIMER-B Register Yes Ye s
54h TIMER-C Register Yes Ye s
58h TIMER-D Register Yes Ye s
5Ch Timer Resolution Yes Yes
SRAM Bank Select (00h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
5 : 0
SRAM memory will be divided into 64 banks, this register will
show which bank of SRAM is momentarily active. The
Register Value is from 0 t0 63
Yes Ye s 0
7 : 6 Reserved Yes Yes 0
DIP Switch (04h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 DIP Switch1 Yes No 0 / 1
1 DIP Switch2 Yes No 0 / 1
2 DIP Switch3 Yes No 0 / 1
3 DIP Switch4 Yes No 0 / 1
4 DIP Switch5 Yes No 0 / 1
5 DIP Switch6 Yes No 0 / 1
6 DIP Switch7 Yes No 0 / 1
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7 DIP Switch8 Yes No 0 / 1
Interrupt & Timer Enable Register (08h & 09h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 Port A Interrupt Enable bit. ‘0’ = No support Interrupt from
Port A as Input; ‘1’ = Support Interrupt from Port A as Input Yes Yes 0
1 Port B Interrupt Enable bit. ‘0’ = No support Interrupt from
Port B as Input; ‘1’ = Support Interrupt from Port B as Input Ye s Yes 0
2 Port C Interrupt Enable bit. ‘0’ = No support Interrupt from
Port C as Input; ‘1’ = Support Interrupt from Port C as Input Yes Yes 0
3 Port D Interrupt Enable bit. ‘0’ = No support Interrupt from
Port D as Input; ‘1’ = Support Interrupt from Port D as Input
Yes Ye s 0
4 Port E Interrupt Enable bit. ‘0’ = No support Interrupt from
Port E as Input; ‘1’ = Support Interrupt from Port E as Input
Yes Ye s 0
5 Port F Interrupt Enable bit. ‘0’ = No support Interrupt from
Port F as Input; ‘1’ = Support Interrupt from Port F as Input
Yes Ye s 0
6 Port G Interrupt Enable bit. ‘0’ = No support Interrupt from
Port G as Input; ‘1’ = Support Interrupt from Port G as Input
Yes Ye s 0
7 Port H Interrupt Enable bit. ‘0’ = No support Interrupt from
Port H as Input; ‘1’ = Support Interrupt from Port H as Input
Yes Ye s 0
8 Port I Interrupt Enable bit. ‘0’ = No support Interrupt from Port
I as Input; ‘1’ = Support Interrupt from Port I as Input
Yes Ye s 0
9 Port J Interrupt Enable bit. ‘0’ = No support Interrupt from
Port J as Input; ‘1’ = Support Interrupt from Port J as Input
Yes Ye s 0
10 Port K Interrupt Enable bit. ‘0’ = No support Interrupt from
Port K as Input; ‘1’ = Support Interrupt from Port K as Input
Yes Ye s 0
11 Port L Interrupt Enable bit. ‘0’ = No support Interrupt from
Port L as Input; ‘1’ = Support Interrupt from Port L as Input
Yes Ye s 0
12 Timer-A Enable bit. ‘0’ = Timer-A disable; ‘1’ = Timer-A
Enable
Yes Ye s 0
13 Timer-B Enable bit. ‘0’ = Timer-B disable; ‘1’ = Timer-B
Enable
Yes Ye s 0
14 Timer-C Enable bit. ‘0’ = Timer-C disable; ‘1’ = Timer-C
Enable
Yes Ye s 0
15 Timer-D Enable bit. ‘0’ = Timer-D disable; ‘1’ = Timer-D
Enable
Yes Ye s 0
Interrupt Source Register (0Ch & 0Dh)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0
Interrupt Status in Port A. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port A as
Input
Yes N o 0
1
Interrupt Status in Port B. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port B as
Input
Yes N o 0
2
Interrupt Status in Port C. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port C as
Input
Yes N o 0
3
Interrupt Status in Port D. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port D as
Input
Yes N o 0
4
Interrupt Status in Port E. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port E as
Input
Yes N o 0
5
Interrupt Status in Port F. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port F as
Input
Yes N o 0
AR-B2002 PCI I/O board with discrete I/O, battery backup SRAM,
Timer, power off intrusion event logger and Protect-U
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AR-B2002 User’s Guide
6
Interrupt Status in Port G. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port G as
Input
Yes N o 0
7
Interrupt Status in Port H. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port H as
Input
Yes N o 0
8 Interrupt Status in Port I. 0 = No Interrupt, 1 = Interrupt active.
To clear this bit, must be wrote any data to Port I as Input Yes N o 0
9
Interrupt Status in Port J. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port J as
Input
Yes N o 0
10
Interrupt Status in Port K. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port K as
Input
Yes N o 0
11
Interrupt Status in Port L. 0 = No Interrupt, 1 = Interrupt
active. To clear this bit, must be wrote any data to Port L as
Input
Yes N o 0
12
Timer-A Interrupt status. 0 = No Interrupt from Timer-A, 1 =
Timer-A Interrupt activ. To clear this bit, must be wrote to
Timer-A register
Yes N o
0
13
Timer-A Interrupt status. 0 = No Interrupt from Timer-B, 1 =
Timer-B Interrupt activ. To clear this bit, must be wrote to
Timer-B register
Yes N o
0
14
Timer-A Interrupt status. 0 = No Interrupt from Timer-C, 1 =
Timer-C Interrupt activ. To clear this bit, must be wrote to
Timer-C register
Yes N o
0
15
Timer-A Interrupt status. 0 = No Interrupt from Timer-D, 1 =
Timer-D Interrupt activ. To clear this bit, must be wrote to
Timer-D register
Yes N o 0
Port BCD Mode (10h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 Port A (8 bit). 0 = Input Mode, Output Mode disable Yes No 0
1 Port B (8 bit). 0 = Input Mode, 1 = Output Mode Yes Yes 0
2 Port C (8 bit). 0 = Input Mode, 1 = Output Mode Yes Yes 0
3 Port D (8 bit). 0 = Input Mode, 1 = Output Mode Yes Yes 0
7 : 4 Reserved Yes No 0
Port A Data (14h)
Bit Field Description Software
Readable Software Writable Value after Reset
0 Bit 1 of Port A Yes Only to clear
Interrupt 0 / 1
1 Bit 2 of Port A Yes Only to clear
Interrupt
0 / 1
2 Bit 3 of Port A Yes Only to clear
Interrupt
0 / 1
3 Bit 4 of Port A Yes Only to clear
Interrupt
0 / 1
4 Bit 5 of Port A Yes Only to clear
Interrupt
0 / 1
5 Bit 6 of Port A Yes Only to clear
Interrupt
0 / 1
6 Bit 7 of Port A Yes Only to clear
Interrupt
0 / 1
7 Bit 8 of Port A Yes Only to clear
Interrupt
0 / 1
AR-B2002 PCI I/O board with discrete I/O, battery backup SRAM,
Timer, power off intrusion event logger and Protect-U
19/45

AR-B2002 User’s Guide
Port B Data (18h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 Bit 1 of Port B Yes Yes (only in
Output Mode) 0 / 1
1 Bit 2 of Port B Yes Yes (only in
Output Mode)
0 / 1
2 Bit 3 of Port B Yes Yes (only in
Output Mode)
0 / 1
3 Bit 4 of Port B Yes Yes (only in
Output Mode)
0 / 1
4 Bit 5 of Port B Yes Yes (only in
Output Mode)
0 / 1
5 Bit 6 of Port B Yes Yes (only in
Output Mode)
0 / 1
6 Bit 7 of Port B Yes Yes (only in
Output Mode)
0 / 1
7 Bit 8 of Port B Yes Yes (only in
Output Mode)
0 / 1
Port C Data (1Ch)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 Bit 1 of Port C Yes Yes (only in
Output Mode) 0 / 1
1 Bit 2 of Port C Yes Yes (only in
Output Mode)
0 / 1
2 Bit 3 of Port C Yes Yes (only in
Output Mode)
0 / 1
3 Bit 4 of Port C Yes Yes (only in
Output Mode)
0 / 1
4 Bit 5 of Port C Yes Yes (only in
Output Mode)
0 / 1
5 Bit 6 of Port C Yes Yes (only in
Output Mode)
0 / 1
6 Bit 7 of Port C Yes Yes (only in
Output Mode)
0 / 1
7 Bit 8 of Port C Yes Yes (only in
Output Mode)
0 / 1
Port D Data (20h)
Bit Field Description Software
Readable
Software
Writable Value after Reset
0 Bit 1 of Port D Yes Yes (only in
Output Mode) 0 / 1
1 Bit 2 of Port D Yes Yes (only in
Output Mode)
0 / 1
2 Bit 3 of Port D Yes Yes (only in
Output Mode)
0 / 1
3 Bit 4 of Port D Yes Yes (only in
Output Mode)
0 / 1
4 Bit 5 of Port D Yes Yes (only in
Output Mode)
0 / 1
5 Bit 6 of Port D Yes Yes (only in
Output Mode)
0 / 1
6 Bit 7 of Port D Yes Yes (only in
Output Mode)
0 / 1
AR-B2002 PCI I/O board with discrete I/O, battery backup SRAM,
Timer, power off intrusion event logger and Protect-U
20/45