Tews Technologies TPMC682-10 User manual

The Embedded I/O Company
TPMC682
3 x 16 bit I/O Ports with
512 Word FIFO and Handshake
Version 1.0
User Manual
Issue 1.1
September 2006
D76682800
TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
Phone: [phone]
Fax: [phone]
e-mail: [email protected]
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: [phone]
Fax: [phone]
e-mail: [email protected]

TPMC682 User Manual Issue 1.1 Page 2 of 36
TPMC682-10
3 x 16 bit I/O Ports with
512 Word FIFO and Handshake
HD68 front panel connector
P14 Back I/O
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2005-2006 by TEWS TECHNOLOGIES GmbH

TPMC682 User Manual Issue 1.1 Page 3 of 36
Issue Description Date
1.0 First Issue April 2005
1.1 New address TEWS LLC September 2006

TPMC682 User Manual Issue 1.1 Page 4 of 36
Table of Contents
1PRODUCT DESCRIPTION.........................................................................................6
2TECHNICAL SPECIFICATION...................................................................................7
3HANDSHAKE MODE .................................................................................................8
4LOCAL SPACE ADDRESSING................................................................................11
4.1 PCI9030 Local Space Configuration ...........................................................................................11
4.2 FPGA Control Register Space.....................................................................................................12
4.2.1 Interrupt and FIFO Control Register (IFCR; 0x00).............................................................13
4.2.2 Port Data Direction Register (PDDR; 0x04) .......................................................................13
4.2.3 Handshake Status and Control Register 2 (HSCR2; 0x11)................................................14
4.2.4 Handshake Status and Control Register 1 (HSCR1; 0x12)................................................15
4.2.5 Handshake Status and Control Register 0 (HSCR0; 0x13)................................................16
4.2.6 Timeout Counter Preload Register 2 (TCPR2; 0x14).........................................................17
4.2.7 Timeout Counter Preload Register 1 (TCPR1; 0x18).........................................................17
4.2.8 Timeout Counter Preload Register 0 (TCPR0; 0x1C)........................................................17
4.2.9 FIFO Data Counter Register 2 (FDCR2; 0x20)..................................................................18
4.2.10 FIFO Data Counter Register 1 (FDCR1; 0x24)................................................................18
4.2.11 FIFO Data Counter Register 0 (FDCR0; 0x28)................................................................18
4.2.12 FIFO Threshold Register 2 (FTHR2; 0x30)......................................................................19
4.2.13 FIFO Threshold Register 1 (FTHR1; 0x34)......................................................................19
4.2.14 FIFO Threshold Register 0 (FTHR0; 0x38)......................................................................19
4.3 FPGA Port Register Space...........................................................................................................20
4.3.1 HS-Port Data Register 2 (PDR2; 0x0 or 0x2).....................................................................21
4.3.2 HS-Port Data Register 1 (PDR1; 0x4 or 0x6).....................................................................23
4.3.3 HS-Port Data Register 0 (PDR0; 0x8 or 0xA) ....................................................................23
4.3.4 Port Data Register 5 (PDR5; 0xC)......................................................................................24
4.3.5 Port Data Register 4 (PDR4; 0xD)......................................................................................24
5PCI9030 TARGET CHIP...........................................................................................25
5.1 PCI Configuration Registers (PCR).............................................................................................25
5.1.1 PCI9030 Header.................................................................................................................25
5.1.2 PCI Base Address Initialization ..........................................................................................26
5.2 Local Configuration Register (LCR)............................................................................................27
5.3 Configuration EEPROM................................................................................................................28
5.4 Local Software Reset....................................................................................................................29
6CONFIGURATION HINTS........................................................................................30
6.1 Big / Little Endian..........................................................................................................................30
7INSTALLATION........................................................................................................32
7.1 I/O Circuit.......................................................................................................................................32
7.2 Back I/O Configuration.................................................................................................................33
8PIN ASSIGNMENT – I/O CONNECTOR ..................................................................35
8.1 Back I/O P14 ..................................................................................................................................35
8.2 Front Panel I/O...............................................................................................................................36

TPMC682 User Manual Issue 1.1 Page 5 of 36
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7
FIGURE 3-1 : INPUT TRANSFER TIMING DIAGRAM.....................................................................................9
FIGURE 3-2 : OUTPUT TRANSFER TIMING DIAGRAM...............................................................................10
FIGURE 4-1 : PCI9030 LOCAL SPACE CONFIGURATION..........................................................................11
FIGURE 4-2 : CONTROL REGISTER SPACE ...............................................................................................12
FIGURE 4-3 : INTERRUPT AND FIFO CONTROL REGISTER (IFCR).........................................................13
FIGURE 4-4 : PORT DATA DIRECTION REGISTER (PDDR).......................................................................13
FIGURE 4-5 : HANDSHAKE STATUS AND CONTROL REGISTER 2 (HSCR2) ..........................................14
FIGURE 4-6 : HANDSHAKE STATUS AND CONTROL REGISTER 1 (HSCR1) ..........................................15
FIGURE 4-7 : HANDSHAKE STATUS AND CONTROL REGISTER 0 (HSCR0) ..........................................16
FIGURE 4-8 : FIFO THRESHOLD REGISTER 2 (FTHR2).............................................................................17
FIGURE 4-9 : FIFO THRESHOLD REGISTER 1 (FTHR1).............................................................................17
FIGURE 4-10: FIFO THRESHOLD REGISTER 0 (FTHR0)............................................................................17
FIGURE 4-11: FIFO DATA COUNTER REGISTER 2 (FDCR2).....................................................................18
FIGURE 4-12: FIFO DATA COUNTER REGISTER 1 (FDCR1).....................................................................18
FIGURE 4-13: FIFO DATA COUNTER REGISTER 0 (FDCR0).....................................................................18
FIGURE 4-14: FIFO THRESHOLD REGISTER 2 (FTHR2)............................................................................19
FIGURE 4-15: FIFO THRESHOLD REGISTER 1 (FTHR1)............................................................................19
FIGURE 4-16: FIFO THRESHOLD REGISTER 0 (FTHR0)............................................................................19
FIGURE 4-17: PORT REGISTER SPACE......................................................................................................20
FIGURE 4-18: HS-PORT DATA REGISTER 2 ...............................................................................................21
FIGURE 4-19: EXAMPLE OF A 32 BIT PORT DATA REGISTER WRITE ACCESS.....................................22
FIGURE 4-20: HS-PORT DATA REGISTER 1 ...............................................................................................23
FIGURE 4-21: HS-PORT DATA REGISTER 0 ...............................................................................................23
FIGURE 4-22: PORT DATA REGISTER 5 (PDR5).........................................................................................24
FIGURE 4-23: PORT DATA REGISTER 4 (PDR4).........................................................................................24
FIGURE 5-1 : PCI9030 HEADER....................................................................................................................25
FIGURE 5-2 : PCI9030 PCI BASE ADDRESS USAGE..................................................................................26
FIGURE 5-3 : PCI9030 LOCAL CONFIGURATION REGISTER....................................................................27
FIGURE 5-4 : CONFIGURATION EEPROM...................................................................................................28
FIGURE 6-1 : LOCAL BUS LITTLE/BIG ENDIAN...........................................................................................30
FIGURE 7-1 : I/O CIRCUITRY ........................................................................................................................32
FIGURE 7-2 : JUMPER POSITIONS FOR GROUND OPTION.......................................................................33
FIGURE 7-3 : JUMPER POSITIONS FOR PORT 2 SIGNAL OPTION ...........................................................33
FIGURE 7-4 : JUMPER POSITIONS FOR BACK I/O OPTIONS.....................................................................34
FIGURE 8-1 : P14 I/O PIN ASSIGNMENT......................................................................................................35
FIGURE 8-2 : FRONT I/O PIN ASSIGNMENT................................................................................................36

TPMC682 User Manual Issue 1.1 Page 6 of 36
1 Product Description
The TPMC682 is a standard single-width 32 bit PMC with three 16 bit TTL digital input/output lines
controlled by handshake signals. These handshake signals run over an additional 8 bit input and an 8
bit output port. Interlocked or pulsed handshake protocol is provided. Each I/O port has a 512 words
deep FIFO. All I/O lines are protected by bus transceivers and ESD protection devices.
The PLX PCI9030 PCI target chip is used for the PCI interface.
An interrupt can be generated on INTA, when the filling level of a FIFO exceeds the value of the
individually programmable threshold. Each port has a programmable timeout counter for input
direction of data.
The TPMC682 provides front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14
(Port 2 not fully supported over back I/O).
Figure 1-1 : Block Diagram

TPMC682 User Manual Issue 1.1 Page 7 of 36
2 Technical Specification
PMC Interface
Mechanical Interface PCI Mezzanine Card (PMC) Interface
Single Size
Electrical Interface PCI Rev. 2.1 compliant
33 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI Target Chip PCI9030 (PLX Technology)
Local Control Logic FPGA Spartan2 XC2S100-5 FG256 I (Xilinx)
I/O Interface 64 lines arranged in 3 x 16 bit handshake ports (Port 0-2)
and 2 x 8 bit ports (Port 4/5) for handshake signals,
Number of I/O Lines
Max. output current per line: -8mA (High level)
8mA (Low level)
I/O Connector PMC P14 I/O (64pin Mezzanine Connector): all ports, except for
upper byte of port 2 (can be changed to all signals of Port 2,
without ground lines)
Front panel HD68 SCSI-3 type Connector: all ports
Physical Data
Power Requirements 100mA typical @ +3.3V DC
70mA typical (no load) @ +5V DC
Temperature Range Operating
Storage -40 °C to +85 °C -40°C to +125°C
MTBF 373000 h
Humidity 5 – 95 % non-condensing
Weight 74 g
Figure 2-1 : Technical Specification

TPMC682 User Manual Issue 1.1 Page 8 of 36
3 Handshake Mode
There are three 16 bit ports available (Port 0 - 2), input and output transfers are buffered by FIFOs,
each 512 words deep. Buffering allows orderly transfers by using the handshake pins in one of two
programmable protocols.
Use of buffering is most beneficial in situations where a peripheral device and the computer system
are capable of transferring data at roughly the same speed. Buffering allows the write operation of the
data transmitter to be overlapped with the fetch operation of the data receiving device. Thus,
throughput may be greatly enhanced. If there is a large mismatch in transfer capability between the
computer and the peripheral, little or no benefit is obtained. In these cases there is no penalty in using
buffering.
Port 4 is an input port, bit 0, 1 and 2 of port 4 are used as handshake input signals H1/H3/H5.
Port 5 is an output port, bit 0, 1 and 2 are the handshake output signals H2/H4/H6. The action is
programmable.
The FIFO_STATUS0/1/2 flag, which is bit 7 of the Handshake Status and Control Registers
HSCR0/1/2, gives information about the fill status of the FIFO. An interrupt is triggered if
FIFO_STATUS0/1/2 flag is set and it is enabled by bit 1 of Handshake Status and Control Register
HSCR0/1/2 as well as the global interrupt is enabled: bit 0 of IFCR.
H1 and H2 belong to the 16 bit port on port 0, H3/H4 belong to port 1 and H5/H6 belong to port 2.
Handshake Input
Signals
H1: Port 4 Line 0
H3: Port 4 Line 1
H5: Port 4 Line 2
Handshake Output
Signals
H2: Port 5 Line 0
H4: Port 5 Line 1
H6: Port 5 Line 2
Input Transfers:
If input direction is set for a handshake port, H1 (H3/H5) input signal is used for acquisition of data.
Data is buffered on a falling edge of H1 (H3/H5). FIFO_STATUS0/1/2 is set when the number of
stored data words in the FIFO exceeds the value specified by the corresponding FIFO threshold
register FTHR0/1/2. If the handshake output signals H2 (H4/H6) are used, they indicate whether there
is room for more data in the FIFO or not.
If H2 (H4/H6) output is used, it may be in the interlocked or pulsed input handshake protocol. The
protocol is set by bit 5 and 6 of the Handshake Status and Control Registers HSCR0/1/2.
In the interlocked input handshake protocol signal H2 (H4/H6) is cleared when the port input buffers
are ready to accept new data. It is set following the falling edge of the H1 (H3/H5) input. When ready
for new data, H2 (H4/H6) is cleared again. When FIFO is full H2 (H4/H6) remains high until data is
removed by a read of port data register. Thus, anytime H2 (H4/H6) output is low, new input data may
be entered by a falling edge on H1 (H3/H5). At other times transitions of H1 (H3/H5) are ignored.
In the pulsed input handshake protocol signal H2 (H4/H6) is cleared in the same way as in the
interlocked input protocol, but never remains low longer than four clock cycles. Typically a four-clock
cycle pulse is generated. But in the case that a subsequent H1 (H3/H5) falling edge occurs before
termination of the pulse, H2 (H4/H6) is set immediately high. Thus, anytime after a falling edge of the
H2 (H4/H6) pulse, new data may be entered in the buffers.

TPMC682 User Manual Issue 1.1 Page 9 of 36
A timeout function can signal when no data was received for a specified timeout period. It is realized
by a counter which is clocked with 1/33 of the PCI clock frequency, normally about 1 MHz (or 1µs
period time). The timeout period is specified by the 16 bit preload value of the timeout (downward-)
counter in the Timeout Counter Preload Registers TCPR0/1/2, i.e.: the maximum timeout period is
about 65ms. The timeout function is started after the first asserted edge on the corresponding
handshake input line after enabling by setting bit TOUT_EN0/1/2 and is retriggered with every following
edge. When data receiving is stopped because of a filled FIFO, no timeout event is generated. An
interrupt is triggered if TOUT_STATUS0/1/2 flag is set and it is enabled by bit 1 of Handshake Status
and Control Register HSCR0/1/2 as well as the global interrupt is enabled: bit 0 of IFCR.
In the figure below “Input Transfer Timing Diagram” a sample timing diagram is given. The H2 (H4/H6)
interlocked and pulse input handshake protocols are shown.
Figure 3-1 : Input Transfer Timing Diagram
Output Transfers:
The peripheral accepts the data by a falling edge on H1 (H3/H5), which causes the next word to be
moved to the corresponding output. H2 (H4/H6) indicates that new data has been moved to the
output.
If H2 (H4/H6) output is used, it may be in the interlocked or pulsed output handshake protocol. The
protocol is set by bit 5 and 6 of the Handshake Status and Control Registers HSCR0/1/2.
In the interlocked output handshake protocol signal H2 (H4/H6) is cleared two clock cycles after data
is transferred to the output. The data remains stable and H2 (H4/H6) remains low until the next falling
edge of the H1 (H3/H5) input. At that time H2 (H4/H6) goes high. As soon as the next data is
available, it is transferred to the output and H2 (H4/H6) is cleared again. When H2 (H4/H6) is high,
transitions on H1 (H3/H5) have no effect.
When H2 (H4/H6) is an output pin in the pulsed output handshake protocol, it is cleared exactly as in
the interlocked output protocol, but never remains low longer than four clock cycles. Typically a four-
clock cycle pulse is generated. But in case that a subsequent H1 (H3/H5) falling edge occurs before
termination of the pulse, H2 (H4/H6) is set immediately high, thus shortening the pulse.
The FIFO_STATUS0/1/2 status bit is high when the fill level of the FIFO falls below the value specified
in the corresponding threshold register.

TPMC682 User Manual Issue 1.1 Page 10 of 36
The typical delay time between a falling edge on H1 (H3/H5) and the next falling edge on H2 (H4/H6)
signaling new valid output data, is about 180ns.
Figure 3-2 : Output Transfer Timing Diagram