Tews Technologies TCP460 User manual

The Embedded I/O Company
TCP460
16 Channel Serial Interface RS232/RS422
Version 1.0
User Manual
Issue 1.1
October 2005
D74460800
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek / Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com
TEWS TECHNOLOGIES LLC
1 E. Liberty Street, Sixth Floor Reno, Nevada 89504 / USA
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TCP460 User Manual Issue 1.1 Page 2 of 32
TCP460-10
16 channel RS232 asynchronous serial interface,
front panel I/O
TCP460-11
16 channel RS422 asynchronous serial interface,
front panel I/O
TCP460-12
8 channel RS232, 8 channel RS422
asynchronous serial interface, front panel I/O
TCP460-13
12 channel RS232, 4 channel RS422
asynchronous serial interface, front panel I/O
TCP460-14
4 channel RS232, 12 channel RS422
asynchronous serial interface, front panel I/O
TCP460-20
16 channel RS232 asynchronous serial interface,
front panel and J2 I/O
TCP460-21
16 channel RS422 asynchronous serial interface,
front panel and J2 I/O
TCP460-22
8 channel RS232, 8 channel RS422
asynchronous serial interface, front panel and
J2 I/O
TCP460-23
12 channel RS232, 4 channel RS422
asynchronous serial interface, front panel and
J2 I/O
TCP460-24
4 channel RS232, 12 channel RS422
asynchronous serial interface, front panel and
J2 I/O
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2005 by TEWS TECHNOLOGIES GmbH
Issue Description Date
1.0 First Issue June 2005
1.1 Configuration EEPROM data & Pinout clarification October 2005

TCP460 User Manual Issue 1.1 Page 3 of 32
Table of Contents
1PRODUCT DESCRIPTION......................................................................................... 5
2TECHNICAL SPECIFICATION................................................................................... 6
3CPCI/PCI INTERFACE ............................................................................................... 8
3.1 Secondary PCI Bus Overview........................................................................................................9
3.2 PCI2050B PCI-to-PCI Bridge General Info ....................................................................................9
4XR17D158 OCTAL PCI-UART ................................................................................. 10
4.1 PCI Configuration Space Registers (PCR) .................................................................................10
4.2 Device Configuration Space ........................................................................................................11
4.2.1 UART Register Sets...........................................................................................................12
4.2.2 Device Configuration Registers .........................................................................................13
4.2.3 UART Configuration Registers...........................................................................................14
4.3 Configuration EEPROM................................................................................................................16
5CONFIGURATION HINTS ........................................................................................ 19
6PROGRAMMING HINTS .......................................................................................... 20
6.1 UART Baud Rate Programming...................................................................................................20
7PIN ASSIGNMENT – I/O CONNECTOR .................................................................. 22
7.1 Front Panel I/O Connector ...........................................................................................................23
7.1.1 TCP460-x0 .........................................................................................................................23
7.1.2 TCP460-x1 .........................................................................................................................24
7.1.3 TCP460-x2 .........................................................................................................................25
7.1.4 TCP460-x3 .........................................................................................................................26
7.1.5 TCP460-x4 .........................................................................................................................27
7.2 CompactPCI Back I/O ...................................................................................................................28
7.2.1 TCP460-20.........................................................................................................................28
7.2.2 TCP460-21.........................................................................................................................29
7.2.3 TCP460-22.........................................................................................................................30
7.2.4 TCP460-23.........................................................................................................................31
7.2.5 TCP460-24.........................................................................................................................32

TCP460 User Manual Issue 1.1 Page 4 of 32
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................5
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7
FIGURE 3-1 : CPCI/PCI INTERFACE...............................................................................................................8
FIGURE 3-2 : SERIAL CHANNEL MAPPING ...................................................................................................8
FIGURE 3-3 : SECONDARY PCI BUS OVERVIEW.........................................................................................9
FIGURE 4-1 : XR17D158 PCI HEADER .........................................................................................................10
FIGURE 4-2 : DEVICE CONFIGURATION SPACE........................................................................................11
FIGURE 4-3 : UART REGISTER SET OFFSET .............................................................................................12
FIGURE 4-4 : UART REGISTER SET ............................................................................................................12
FIGURE 4-5 : DEVICE CONFIGURATION REGISTERS ...............................................................................13
FIGURE 4-6 : UART CHANNEL CONFIGURATION REGISTERS ................................................................14
FIGURE 4-7 : CONFIGURATION EEPROM TCP460-XX ..............................................................................16
FIGURE 4-8 : PHYSICAL CONFIGURATION EEPROM DATA OF UART 1 .................................................17
FIGURE 4-9 : PHYSICAL CONFIGURATION EEPROM DATA OF UART 2 .................................................18
FIGURE 5-1 : UART INTERFACE MAPPING.................................................................................................19
FIGURE 6-1 : UART BAUD RATE PROGRAMMING .....................................................................................20
FIGURE 7-1 : TCP460-X0 PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ......................................23
FIGURE 7-2 : TCP460-X1 PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ......................................24
FIGURE 7-3 : TCP460-X2 PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ......................................25
FIGURE 7-4 : TCP460-X3 PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ......................................26
FIGURE 7-5 : TCP460-X4 PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ......................................27
FIGURE 7-6 : PIN ASSIGNMENT TCP460-20 COMPACTPCI BACK I/O CONNECTOR (J2)......................28
FIGURE 7-7 : PIN ASSIGNMENT TCP460-21 COMPACTPCI BACK I/O CONNECTOR (J2)......................29
FIGURE 7-8 : PIN ASSIGNMENT TCP460-22 COMPACTPCI BACK I/O CONNECTOR (J2)......................30
FIGURE 7-9 : PIN ASSIGNMENT TCP460-23 COMPACTPCI BACK I/O CONNECTOR (J2)......................31
FIGURE 7-10 : PIN ASSIGNMENT TCP460-24 COMPACTPCI BACK I/O CONNECTOR (J2)....................32

TCP460 User Manual Issue 1.1 Page 5 of 32
1 Product Description
The TCP460 is a standard 3U 32 bit CompactPCI module and offers 16 channels of high performance
serial interface.
Five different standard modules are available: The TCP460-10 provides 16 RS232 interfaces. The
TCP460-11 provides 16 RS422 interfaces. The TCP460-12 provides 8 RS232 and 8 RS422
interfaces. The TCP460-13 provides 12 RS232 and 4 RS422 interfaces. The TCP460-14 provides 4
RS232 and 12 RS422 interfaces. Other configurations are available as factory option on a per channel
basis.
All modules offer front panel I/O with a HD68 connector. The TCP460-2x modules offer additional J2
rear I/O. Each RS232 channel supports RxD, TxD, RTS and CTS. Each RS422 supports RxD+/- and
TxD+/-.
A transparent 32 bit / 66 MHz PCI-to-PCI Bridge provides access to the two Exar XR17D158 octal
PCI-UARTs. The PCI-to-PCI Bridge allows 32 bit accesses on the local PCI bus and permits the high
data throughput necessary for the high performance serial interfaces.
Each channel has 64 byte transmit and receive FIFOs to significantly reduce the overhead required to
provide data to and get data from the transmitters and receivers. The FIFO trigger levels are
programmable and the baud rate is individually programmable up to 921.6 kbps for RS232 channels
and 5.5296 Mbps for RS422 channels. The UART offers readable FIFO levels.
Interrupts are supported. For fast interrupt source detection each octal UART provides a special
Global Interrupt Source Register.
All serial channels use ESD protected transceivers up to ±15KV according to IEC 1000-4-2.
The TCP460 can operate with 3.3V and 5.0V PCI I/O signaling voltage.
Figure 1-1 : Block Diagram

TCP460 User Manual Issue 1.1 Page 6 of 32
2 Technical Specification
PMC Interface
Mechanical Interface Standard 3U 32 Bit CompactPCI module conforming to
PICMG 2.0 R3.0
Electrical Interface PCI Rev. 2.3 compliant
33 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI-to-PCI Bridge PCI2050B (Texas Instruments)
Octal UART XR17D158 (Exar)
Transceiver RS232: MAX3225E (or equivalent)
RS422: MAX3087E (or equivalent)
I/O Interface
Interface Type Asynchronous serial interface
Number of Channels 16 (2x 8 channels)
Physical Interface TCP460-x0: 16 RS232
TCP460-x1: 16 RS422
TCP460-x2: 8 RS232, 8 RS422
TCP460-x3: 12 RS232, 4 RS422
TCP460-x4: 4 RS232, 12 RS422
Serial Channel I/O Signals RS232: TxD, RxD, RTS, CTS, GND
RS422: TxD+/-, RxD+/-, GND
Termination RS422: 120Ωbetween RxD+ and RxD- of each channel
Programmable Baud Rates RS232: up to 921.6 kbps
RS422: up to 5.5296 Mbps
ESD Protection RS232:
±15kV—Human Body Model
±8kV—IEC 1000-4-2, Contact Discharge
±15kV—IEC 1000-4-2, Air-Gap Discharge
RS422:
±15kV—Human Body Model
I/O Connector HD68 SCSI-3 type connector (e.g. AMP# 787082)
TCP460-2x: additional 110 pol. CompactPCI back I/O (J2)
Physical Data
Power Requirements TCP460-x0: 80 mA typical @ +3.3V DC (no load)
TCP460-x0: 70 mA typical @ +5V DC
TCP460-x1: 120 mA typical @ +3.3V DC (no load)
TCP460-x1: 70 mA typical @ +5V DC
TCP460-x2: 100 mA typical @ +3.3V DC (no load)
TCP460-x2: 70 mA typical @ +5V DC
TCP460-x3: 90 mA typical @ +3.3V DC (no load)
TCP460-x3: 70 mA typical @ +5V DC
TCP460-x4: 110 mA typical @ +3.3V DC (no load)
TCP460-x4: 70 mA typical @ +5V DC

TCP460 User Manual Issue 1.1 Page 7 of 32
Temperature Range Operating
Storage
-40°C to +85°C
-55°C to +125°C
MTBF TCP460-10: 510 000h
TCP460-11: 390 000h
TCP460-12: 440 000h
TCP460-13: 440 000h
TCP460-14: 390 000h
TCP460-20: 470 000h
TCP460-21: 370 000h
TCP460-22: 410 000h
TCP460-23: 440 000h
TCP460-24: 390 000h
Humidity 5 – 95 % non-condensing
Weight 135 g
Figure 2-1 : Technical Specification

TCP460 User Manual Issue 1.1 Page 8 of 32
3 cPCI/PCI Interface
The TCP460 uses two Exar XR17D158 octal PCI-UARTs to provide and control the 16 serial
channels. A transparent 32 bit / 66 MHz PCI-to-PCI Bridge provides access to the two octal PCI-
UARTs. The PCI-to-PCI Bridge allows 32 bit accesses on the local PCI bus and permits the high data
throughput necessary for the high performance serial interfaces.
Figure 3-1 : cPCI/PCI Interface
The following chart gives information about how the serial channels are assigned to the octal UARTs:
Octal PCI UART Internal UART Serial Channel
UART Channel 1 0
UART Channel 2 1
UART Channel 3 2
UART Channel 4 3
UART Channel 5 4
UART Channel 6 5
UART Channel 7 6
Octal PCI UART 1
UART Channel 8 7
UART Channel 1 8
UART Channel 2 9
UART Channel 3 10
UART Channel 4 11
UART Channel 5 12
UART Channel 6 13
UART Channel 7 14
Octal PCI UART 2
UART Channel 8 15
Figure 3-2 : Serial channel mapping

TCP460 User Manual Issue 1.1 Page 9 of 32
3.1 Secondary PCI Bus Overview
The following chart gives information about the device numbers of the octal PCI UARTs and how their
interrupts are wired to the Primary PCI Bus:
Secondary PCI Bus
Device Number
Primary PCI Bus
Interrupt Line
Octal UART1 4 (AD20 used as IDSEL) INTA#
Octal UART2 5 (AD21 used as IDSEL) INTB#
Figure 3-3 : Secondary PCI Bus Overview
3.2 PCI2050B PCI-to-PCI Bridge General Info
Vendor ID: 0x104C (Texas Instruments)
Device ID: 0xAC28 (PCI2050b)
The general purpose I/O interface is not used. GPIO pins are pulled up.
Only secondary clock outputs 0-1 and 9 are used to clock secondary devices. The host software may
disable clock outputs 2-8 through the secondary clock control register located at PCI offset 0x68 to
save power.
For detailed description of the PCI2050B PCI-to-PCI Bridge refer to the PCI2050B datasheet, which is
available on the Texas Instruments website (www.ti.com). The PCI2050B data sheet is also part of the
TCP460-ED Engineering Documentation.

TCP460 User Manual Issue 1.1 Page 10 of 32
4 XR17D158 Octal PCI-UART
4.1 PCI Configuration Space Registers (PCR)
Write ‘0’ to all unused (Reserved) bitsPCI CFG
Register
Address 31 24 23 16 15 8 7 0
PCI
writeable
Initial Values
(Hex Values)
0x00 Device ID Vendor ID N 21CC 1498
0x04 Status Command Y 0080 0000
0x08 Class Code Revision ID N 070002 ??
0x0C BIST Header Type
PCI Latency
Timer
Cache Line
Size
N 00 00 00 00
0x10 Memory Base Address Register (BAR) Y FFFFF000
0x14 I/O Base Address Register (Unimplemented) N 00000000
0x18 Base Address Register 0 (Unimplemented) N 00000000
0x1C Base Address Register 1 (Unimplemented) N 00000000
0x20 Base Address Register 2 (Unimplemented) N 00000000
0x24 Base Address Register 3 (Unimplemented) N 00000000
0x28 Reserved N 00000000
0x2C Subsystem ID Subsystem Vendor ID N s.b. 1498
0x30 Expansion ROM Base Address (Unimplemented) N 00000000
0x34 Reserved N 00000000
0x38 Reserved N 00000000
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00
Figure 4-1 : XR17D158 PCI Header
Device-ID: 0x21CC TCP460
Vendor-ID: 0x1498 TEWS TECHNOLOGIES
Revision ID: XR17D158 silicon revision
Subsystem-ID: 0x000A
0x000B
0x000C
0x000D
0x000E
0x0014
0x0015
0x0016
0x0017
0x0018
-10
-11
-12
-13
-14
-20
-21
-22
-23
-24
Subsystem
Vendor-ID: 0x1498 TEWS TECHNOLOGIES