Tews Technologies TPMC460 User manual

The Embedded I/O Company
TPMC460
16 Channel Serial Interface RS232/RS422
Version 1.0
User Manual
Issue 1.0.6
August 2014
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany www.tews.com
Phone: [phone]
Fax: [phone]
e-mail: inf[email protected]

TPMC460-10R
16 channel RS232 asynchronous serial interface,
front panel and back I/O
TPMC460-11R
16 channel RS422 asynchronous serial interface,
front panel and back I/O
TPMC460-12R
8 channel RS232, 8 channel RS422
asynchronous serial interface, front panel and
back I/O
TPMC460-13R
12 channel RS232, 4 channel RS422
asynchronous serial interface, front panel and
back I/O
TPMC460-14R
4 channel RS232, 12 channel RS422
asynchronous serial interface, front panel and
back I/O
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
WWrite Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
¤2014 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.
TPMC460 User Manual Issue 1.0.6 Page 2 of 33

Issue Description Date
1.0 First Issue November 2004
1.1 Configuration EEPROM data & Pinout clarification October 2005
1.2 Channel numbering clarification August 2006
1.3 New address TEWS LLC September 2006
1.4 Changed RS422 Transceiver October 2006
1.0.5 Corrected Back-I/O Pinouts
New notation for HW Engineering Documentation Releases
April 2009
1.0.6 General Revision August 2014
TPMC460 User Manual Issue 1.0.6 Page 3 of 33

Table of Contents
1PRODUCT DESCRIPTION......................................................................................... 6
2TECHNICAL SPECIFICATION................................................................................... 7
3PMC/PCI INTERFACE................................................................................................ 9
Secondary PCI Bus Overview......................................................................................................103.1
PCI2050B PCI-to-PCI Bridge General Info ..................................................................................103.2
4XR17D158 OCTAL PCI-UART ................................................................................. 11
PCI Configuration Space Registers (PCR) .................................................................................114.1
Device Configuration Space ........................................................................................................124.2
4.2.1 UART Register Sets............................................................................................................13
4.2.2 Device Configuration Registers ..........................................................................................14
4.2.3 UART Configuration Registers............................................................................................15
Configuration EEPROM ................................................................................................................174.3
5CONFIGURATION HINTS ........................................................................................ 20
6PROGRAMMING HINTS .......................................................................................... 21
UART Baud Rate Programming...................................................................................................216.1
7PIN ASSIGNMENT – I/O CONNECTOR .................................................................. 23
Front Panel I/O Connector ...........................................................................................................247.1
7.1.1 TPMC460-10R ....................................................................................................................24
7.1.2 TPMC460-11R ....................................................................................................................25
7.1.3 TPMC460-12R ....................................................................................................................26
7.1.4 TPMC460-13R ....................................................................................................................27
7.1.5 TPMC460-14R ....................................................................................................................28
Back I/O PMC Connector (P14)....................................................................................................297.2
7.2.1 TPMC460-10R ....................................................................................................................29
7.2.2 TPMC460-11R ....................................................................................................................30
7.2.3 TPMC460-12R ....................................................................................................................31
7.2.4 TPMC460-13R ....................................................................................................................32
7.2.5 TPMC460-14R ....................................................................................................................33
TPMC460 User Manual Issue 1.0.6 Page 4 of 33

List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 3-1 : PMC/PCI INTERFACE ...............................................................................................................9
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................8
TABLE 3-1 : SERIAL CHANNEL MAPPING .....................................................................................................9
TABLE 3-2 : SECONDARY PCI BUS OVERVIEW .........................................................................................10
TABLE 4-1 : XR17D158 PCI HEADER ...........................................................................................................11
TABLE 4-2 : DEVICE CONFIGURATION SPACE ..........................................................................................12
TABLE 4-3 : UART REGISTER SET OFFSET ...............................................................................................13
TABLE 4-4 : UART REGISTER SET...............................................................................................................13
TABLE 4-5 : DEVICE CONFIGURATION REGISTERS .................................................................................14
TABLE 4-6 : UART CHANNEL CONFIGURATION REGISTERS...................................................................15
TABLE 4-7 : CONFIGURATION EEPROM TPMC460-XXR ...........................................................................17
TABLE 4-8 : PHYSICAL CONFIGURATION EEPROM DATA OF UART 1 ...................................................18
TABLE 4-9 : PHYSICAL CONFIGURATION EEPROM DATA OF UART 2 ...................................................19
TABLE 5-1 : UART INTERFACE MAPPING ...................................................................................................20
TABLE 6-1 : UART BAUD RATE PROGRAMMING .......................................................................................21
TABLE 7-1 : TPMC460-10R PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ...................................24
TABLE 7-2 : TPMC460-11R PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ...................................25
TABLE 7-3 : TPMC460-12R PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ...................................26
TABLE 7-4 : TPMC460-13R PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ...................................27
TABLE 7-5 : TPMC460-14R PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR ...................................28
TABLE 7-6 : TPMC460-10R PIN ASSIGNMENT BACK I/O PMC CONNECTOR (P14) ................................29
TABLE 7-7 : TPMC460-11R PIN ASSIGNMENT BACK I/O PMC CONNECTOR (P14) ................................30
TABLE 7-8 : TPMC460-12R PIN ASSIGNMENT BACK I/O PMC CONNECTOR (P14) ................................31
TABLE 7-9 : TPMC460-13R PIN ASSIGNMENT BACK I/O PMC CONNECTOR (P14) ................................32
TABLE 7-10: TPMC460-14R PIN ASSIGNMENT BACK I/O PMC CONNECTOR (P14) ...............................33
TPMC460 User Manual Issue 1.0.6 Page 5 of 33

1 Product Description
The TPMC460 is a standard single-width 32 bit PMC module and offers 16 channels of high
performance serial interface.
Five different standard modules are available: The TPMC460-10R provides 16 RS232 interfaces. The
TPMC460-11R provides 16 RS422 interfaces. The TPMC460-12R provides 8 RS232 and 8 RS422
interfaces. The TPMC460-13R provides 12 RS232 and 4 RS422 interfaces. The TPMC460-14R
provides 4 RS232 and 12 RS422 interfaces. Other configurations are available as factory option on a
per channel basis.
All modules offer front panel I/O with a HD68 connector and P14 I/O. Each RS232 channel supports
RxD, TxD, RTS and CTS. Each RS422 supports RxD+/- and TxD+/-.
A transparent 32 bit / 66 MHz PCI-to-PCI Bridge provides access to the two Exar XR17D158 octal
PCI-UARTs. The PCI-to-PCI Bridge allows 32 bit accesses on the local PCI bus and permits the high
data throughput necessary for the high performance serial interfaces.
Each channel has 64 byte transmit and receive FIFOs to significantly reduce the overhead required to
provide data to and get data from the transmitters and receivers. The FIFO trigger levels are
programmable and the baud rate is individually programmable up to 921.6 kbps for RS232 channels
and 5.5296 Mbps for RS422 channels. The UART offers readable FIFO levels.
Interrupts are supported. For fast interrupt source detection each octal UART provides a special
Global Interrupt Source Register.
All serial channels use ESD protected transceivers up to ±15KV according to IEC 1000-4-2.
The TPMC460 can operate with 3.3V and 5.0V PCI I/O signaling voltage.
Figure 1-1 : Block Diagram
TPMC460 User Manual Issue 1.0.6 Page 6 of 33

2 Technical Specification
PMC Interface
Mechanical Interface PCI Mezzanine Card (PMC) Interface
Single Size
Electrical Interface PCI Rev. 2.2 compliant
33 MHz / 66 MHz, 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI-to-PCI Bridge PCI2050B (Texas Instruments)
Octal UART XR17D158 (Exar)
Transceiver RS232: MAX3225E (or equivalent)
RS422: MAX3077E (or equivalent)
I/O Interface
Interface Type Asynchronous serial interface
Number of Channels 16 (2x 8 channels)
Physical Interface TPMC460-10R: 16 RS232
TPMC460-11R: 16 RS422
TPMC460-12R: 8 RS232, 8 RS422
TPMC460-13R: 12 RS232, 4 RS422
TPMC460-14R: 4 RS232, 12 RS422
Serial Channel I/O Signals RS232: TxD, RxD, RTS, CTS, GND
RS422: TxD+/-, RxD+/-, GND
Termination 56EHWZHHQ RxD+ and RxD- of each channel
Programmable Baud Rates RS232: up to 921.6 kbps
RS422: up to 5.5296 Mbps
ESD Protection RS232:
±15kV—Human Body Model
±8kV—IEC 1000-4-2, Contact Discharge
±15kV—IEC 1000-4-2, Air-Gap Discharge
RS422:
±15kV—Human Body Model
I/O Connector HD68 SCSI-3 type connector (e.g. AMP# 787082)
PMC P14 I/O (64 pin Mezzanine Connector)
Physical Data
Power Requirements TPMC460-10R: 80 mA typical @ +3.3V DC (no load)
70 mA typical @ +5V DC
TPMC460-11R: 120 mA typical @ +3.3V DC (no load)
70 mA typical @ +5V DC
TPMC460-12R: 100 mA typical @ +3.3V DC (no load)
70 mA typical @ +5V DC
TPMC460-13R: 90 mA typical @ +3.3V DC (no load)
70 mA typical @ +5V DC
TPMC460-14R: 110 mA typical @ +3.3V DC (no load)
70 mA typical @ +5V DC
TPMC460 User Manual Issue 1.0.6 Page 7 of 33

Temperature Range Operating
Storage
-40°C to +85°C
-55°C to +125°C
MTBF TPMC460-10R: 580 000 h
TPMC460-11R: 430 000 h
TPMC460-12R: 480 000 h
TPMC460-13R: 530 000 h
TPMC460-14R: 460 000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight 74 g
Table 2-1 : Technical Specification
TPMC460 User Manual Issue 1.0.6 Page 8 of 33

3 PMC/PCI Interface
The TPMC460 uses two Exar XR17D158 octal PCI-UARTs to provide and control the 16 serial
channels. A transparent 32 bit / 66 MHz PCI-to-PCI Bridge provides access to the two octal PCI-
UARTs. The PCI-to-PCI Bridge allows 32 bit accesses on the local PCI bus and permits the high data
throughput necessary for the high performance serial interfaces.
Figure 3-1 : PMC/PCI Interface
The following chart gives information about how the serial channels are assigned to the octal UARTs:
Octal PCI UART Internal UART Serial Channel
Octal PCI UART 1 UART Channel 0 0
UART Channel 1 1
UART Channel 2 2
UART Channel 3 3
UART Channel 4 4
UART Channel 5 5
UART Channel 6 6
UART Channel 7 7
Octal PCI UART 2 UART Channel 0 8
UART Channel 1 9
UART Channel 2 10
UART Channel 3 11
UART Channel 4 12
UART Channel 5 13
UART Channel 6 14
UART Channel 7 15
Table 3-1 : Serial channel mapping
TPMC460 User Manual Issue 1.0.6 Page 9 of 33

Secondary PCI Bus Overview3.1
The following chart gives information about the device numbers of the octal PCI UARTs and how their
interrupts are wired to the Primary PCI Bus:
Secondary PCI Bus
Device Number
Primary PCI Bus
Interrupt Line
Octal UART1 4 (AD20 used as IDSEL) INTA#
Octal UART2 5 (AD21 used as IDSEL) INTB#
Table 3-2 : Secondary PCI Bus Overview
PCI2050B PCI-to-PCI Bridge General Info3.2
Vendor ID: 0x104C (Texas Instruments)
Device ID: 0xAC28 (PCI2050b)
The general purpose I/O interface is not used. GPIO pins are pulled up.
Only secondary clock outputs 0-1 and 9 are used to clock secondary devices. The host software may
disable clock outputs 2-8 through the secondary clock control register located at PCI offset 0x68 to
save power.
For detailed description of the PCI2050B PCI-to-PCI Bridge refer to the PCI2050B data sheet, which is
available on the Texas Instruments website (www.ti.com).
TPMC460 User Manual Issue 1.0.6 Page 10 of 33