Texas Instruments AM1802 User manual

AM1802 ARM Microprocessor
System
Reference Guide
Literature Number: SPRUGX5A
May 2011

2SPRUGX5A–May 2011
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Contents
Preface ...................................................................................................................................... 19
1 Overview .......................................................................................................................... 21
1.1 Introduction ................................................................................................................. 22
1.2 Block Diagram ............................................................................................................. 22
1.3 ARM Subsystem ........................................................................................................... 22
2 ARM Subsystem ................................................................................................................ 23
2.1 Introduction ................................................................................................................. 24
2.2 Operating States/Modes .................................................................................................. 25
2.3 Processor Status Registers .............................................................................................. 25
2.4 Exceptions and Exception Vectors ...................................................................................... 26
2.5 The 16-BIS/32-BIS Concept ............................................................................................. 27
2.6 16-BIS/32-BIS Advantages ............................................................................................... 27
2.7 Co-Processor 15 (CP15) ................................................................................................. 28
2.7.1 Addresses in an ARM926EJ-S System ........................................................................ 28
2.7.2 Memory Management Unit ...................................................................................... 28
2.7.3 Caches and Write Buffer ........................................................................................ 29
3 System Interconnect .......................................................................................................... 31
3.1 Introduction ................................................................................................................. 32
3.2 System Interconnect Block Diagram .................................................................................... 33
4 System Memory ................................................................................................................ 35
4.1 Introduction ................................................................................................................. 36
4.2 ARM Memories ............................................................................................................ 36
4.3 On-Chip RAM Memory .................................................................................................... 36
4.4 External Memories ........................................................................................................ 36
4.5 Internal Peripherals ........................................................................................................ 36
4.6 Peripherals ................................................................................................................. 36
5 Memory Protection Unit (MPU) ............................................................................................ 37
5.1 Introduction ................................................................................................................. 38
5.1.1 Purpose of the MPU ............................................................................................. 38
5.1.2 Features ........................................................................................................... 38
5.1.3 Block Diagram .................................................................................................... 38
5.1.4 MPU Default Configuration ...................................................................................... 39
5.2 Architecture ................................................................................................................. 39
5.2.1 Privilege Levels ................................................................................................... 39
5.2.2 Memory Protection Ranges ..................................................................................... 40
5.2.3 Permission Structures ............................................................................................ 40
5.2.4 Protection Check ................................................................................................. 42
5.2.5 MPU Register Protection ........................................................................................ 42
5.2.6 Invalid Accesses and Exceptions .............................................................................. 42
5.2.7 Reset Considerations ............................................................................................ 42
5.2.8 Interrupt Support .................................................................................................. 43
5.2.9 Emulation Considerations ....................................................................................... 43
5.3 MPU Registers ............................................................................................................. 44
5.3.1 Revision Identification Register (REVID) ...................................................................... 46
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5.3.2 Configuration Register (CONFIG) .............................................................................. 46
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................. 47
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) .......................................................... 48
5.3.5 Interrupt Enable Set Register (IENSET) ....................................................................... 49
5.3.6 Interrupt Enable Clear Register (IENCLR) .................................................................... 49
5.3.7 Fixed Range Start Address Register (FXD_MPSAR) ....................................................... 50
5.3.8 Fixed Range End Address Register (FXD_MPEAR) ........................................................ 50
5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ................................ 51
5.3.10 Programmable Range nStart Address Registers (PROGn_MPSAR) .................................... 52
5.3.11 Programmable Range nEnd Address Registers (PROGn_MPEAR) .................................... 53
5.3.12 Programmable Range nMemory Protection Page Attributes Register (PROGn_MPPA) ............. 54
5.3.13 Fault Address Register (FLTADDRR) ........................................................................ 55
5.3.14 Fault Status Register (FLTSTAT) ............................................................................. 56
5.3.15 Fault Clear Register (FLTCLR) ................................................................................ 57
6 Device Clocking ................................................................................................................ 59
6.1 Overview .................................................................................................................... 60
6.2 Frequency Flexibility ...................................................................................................... 62
6.3 Peripheral Clocking ........................................................................................................ 63
6.3.1 USB Clocking ..................................................................................................... 63
6.3.2 DDR2/mDDR Memory Controller Clocking .................................................................... 64
6.3.3 EMIFA Clocking ................................................................................................... 66
6.3.4 EMAC Clocking ................................................................................................... 67
6.3.5 McASP Clocking .................................................................................................. 68
6.3.6 I/O Domains ....................................................................................................... 69
7 Phase-Locked Loop Controller (PLLC) ................................................................................. 71
7.1 Introduction ................................................................................................................. 72
7.2 PLL Controllers ............................................................................................................ 72
7.2.1 Device Clock Generation ........................................................................................ 74
7.2.2 Steps for Programming the PLLs ............................................................................... 75
7.3 PLLC Registers ............................................................................................................ 77
7.3.1 PLLC0 Revision Identification Register (REVID) ............................................................. 78
7.3.2 PLLC1 Revision Identification Register (REVID) ............................................................. 79
7.3.3 Reset Type Status Register (RSTYPE) ....................................................................... 79
7.3.4 PLLC0 Reset Control Register (RSCTRL) .................................................................... 80
7.3.5 PLLC0 Control Register (PLLCTL) ............................................................................. 81
7.3.6 PLLC1 Control Register (PLLCTL) ............................................................................. 82
7.3.7 PLLC0 OBSCLK Select Register (OCSEL) ................................................................... 83
7.3.8 PLLC1 OBSCLK Select Register (OCSEL) ................................................................... 84
7.3.9 PLL Multiplier Control Register (PLLM) ........................................................................ 85
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV) ............................................................. 85
7.3.11 PLLC0 Divider 1 Register (PLLDIV1) ......................................................................... 86
7.3.12 PLLC1 Divider 1 Register (PLLDIV1) ......................................................................... 86
7.3.13 PLLC0 Divider 2 Register (PLLDIV2) ......................................................................... 87
7.3.14 PLLC1 Divider 2 Register (PLLDIV2) ......................................................................... 87
7.3.15 PLLC0 Divider 3 Register (PLLDIV3) ......................................................................... 88
7.3.16 PLLC1 Divider 3 Register (PLLDIV3) ......................................................................... 88
7.3.17 PLLC0 Divider 4 Register (PLLDIV4) ......................................................................... 89
7.3.18 PLLC0 Divider 5 Register (PLLDIV5) ......................................................................... 89
7.3.19 PLLC0 Divider 6 Register (PLLDIV6) ......................................................................... 90
7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ......................................................................... 90
7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV) ............................................................. 91
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV) ............................................................. 91
7.3.23 PLL Post-Divider Control Register (POSTDIV) .............................................................. 92
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7.3.24 PLL Controller Command Register (PLLCMD) .............................................................. 92
7.3.25 PLL Controller Status Register (PLLSTAT) .................................................................. 93
7.3.26 PLLC0 Clock Align Control Register (ALNCTL) ............................................................. 94
7.3.27 PLLC1 Clock Align Control Register (ALNCTL) ............................................................. 95
7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .............................................. 96
7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .............................................. 97
7.3.30 PLLC0 Clock Enable Control Register (CKEN) ............................................................. 98
7.3.31 PLLC1 Clock Enable Control Register (CKEN) ............................................................. 98
7.3.32 PLLC0 Clock Status Register (CKSTAT) ..................................................................... 99
7.3.33 PLLC1 Clock Status Register (CKSTAT) ................................................................... 100
7.3.34 PLLC0 SYSCLK Status Register (SYSTAT) ............................................................... 101
7.3.35 PLLC1 SYSCLK Status Register (SYSTAT) ............................................................... 102
7.3.36 Emulation Performance Counter 0 Register (EMUCNT0) ................................................ 103
7.3.37 Emulation Performance Counter 1 Register (EMUCNT1) ................................................ 103
8 Power and Sleep Controller (PSC) ..................................................................................... 105
8.1 Introduction ............................................................................................................... 106
8.2 Power Domain and Module Topology ................................................................................. 106
8.2.1 Power Domain States .......................................................................................... 108
8.2.2 Module States ................................................................................................... 108
8.3 Executing State Transitions ............................................................................................ 110
8.3.1 Power Domain State Transitions .............................................................................. 110
8.3.2 Module State Transitions ....................................................................................... 110
8.4 IcePick Emulation Support in the PSC ................................................................................ 111
8.5 PSC Interrupts ............................................................................................................ 111
8.5.1 Interrupt Events ................................................................................................. 111
8.5.2 Interrupt Registers .............................................................................................. 112
8.5.3 Interrupt Handling ............................................................................................... 113
8.6 PSC Registers ............................................................................................................ 114
8.6.1 Revision Identification Register (REVID) .................................................................... 115
8.6.2 Interrupt Evaluation Register (INTEVAL) .................................................................... 115
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) .................................. 116
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) .................................. 116
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 117
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 117
8.6.7 Power Error Pending Register (PERRPR) ................................................................... 118
8.6.8 Power Error Clear Register (PERRCR) ...................................................................... 118
8.6.9 Power Domain Transition Command Register (PTCMD) .................................................. 119
8.6.10 Power Domain Transition Status Register (PTSTAT) ..................................................... 120
8.6.11 Power Domain 0 Status Register (PDSTAT0) ............................................................. 121
8.6.12 Power Domain 1 Status Register (PDSTAT1) ............................................................. 122
8.6.13 Power Domain 0 Control Register (PDCTL0) .............................................................. 123
8.6.14 Power Domain 1 Control Register (PDCTL1) .............................................................. 124
8.6.15 Power Domain 0 Configuration Register (PDCFG0) ...................................................... 125
8.6.16 Power Domain 1 Configuration Register (PDCFG1) ...................................................... 126
8.6.17 Module Status nRegister (MDSTATn)...................................................................... 127
8.6.18 PSC0 Module Control nRegister (modules 0-15) (MDCTLn)............................................ 128
8.6.19 PSC1 Module Control nRegister (modules 0-31) (MDCTLn)............................................ 129
9 Power Management .......................................................................................................... 131
9.1 Introduction ............................................................................................................... 132
9.2 Power Consumption Overview ......................................................................................... 132
9.3 PSC and PLLC Overview ............................................................................................... 132
9.4 Features ................................................................................................................... 133
9.5 Clock Management ...................................................................................................... 134
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9.5.1 Module Clock ON/OFF ......................................................................................... 134
9.5.2 Module Clock Frequency Scaling ............................................................................. 134
9.5.3 PLL Bypass and Power Down ................................................................................. 134
9.6 ARM Sleep Mode Management ........................................................................................ 135
9.6.1 ARM Wait-For-Interrupt Sleep Mode ......................................................................... 135
9.6.2 ARM Clock OFF ................................................................................................. 136
9.6.3 ARM Subsystem Clock ON .................................................................................... 136
9.7 RTC-Only Mode .......................................................................................................... 137
9.8 Dynamic Voltage and Frequency Scaling (DVFS) ................................................................... 137
9.8.1 Frequency Scaling Considerations ........................................................................... 138
9.8.2 Voltage Scaling Considerations ............................................................................... 138
9.9 Deep Sleep Mode ........................................................................................................ 139
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up .............................. 139
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up .................................... 140
9.9.3 Deep Sleep Sequence ......................................................................................... 141
9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ....................................... 142
9.10 Additional Peripheral Power Management Considerations ......................................................... 142
9.10.1 USB PHY Power Down Control .............................................................................. 142
9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ............................... 143
9.10.3 LVCMOS I/O Buffer Receiver Disable ...................................................................... 143
9.10.4 Pull-Up/Pull-Down Disable .................................................................................... 143
10 System Configuration (SYSCFG) Module ............................................................................ 145
10.1 Introduction ............................................................................................................... 146
10.2 Protection ................................................................................................................. 146
10.2.1 Privilege Mode Protection ..................................................................................... 146
10.2.2 Kicker Mechanism Protection ................................................................................ 147
10.3 Master Priority Control ................................................................................................... 147
10.4 SYSCFG Registers ...................................................................................................... 148
10.4.1 Revision Identification Register (REVID) ................................................................... 150
10.4.2 Device Identification Register 0 (DEVIDR0) ................................................................ 150
10.4.3 Boot Configuration Register (BOOTCFG) .................................................................. 151
10.4.4 Kick Registers (KICK0R-KICK1R) ........................................................................... 152
10.4.5 Host 0 Configuration Register (HOST0CFG) ............................................................... 153
10.4.6 Interrupt Registers ............................................................................................. 154
10.4.7 Fault Registers ................................................................................................. 157
10.4.8 Master Priority Registers (MSTPRI0-MSTPRI2) ........................................................... 159
10.4.9 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................. 162
10.4.10 Suspend Source Register (SUSPSRC) ................................................................... 201
10.4.11 Chip Signal Register (CHIPSIG) ........................................................................... 203
10.4.12 Chip Signal Clear Register (CHIPSIG_CLR) ............................................................. 204
10.4.13 Chip Configuration 0 Register (CFGCHIP0) .............................................................. 205
10.4.14 Chip Configuration 1 Register (CFGCHIP1) .............................................................. 206
10.4.15 Chip Configuration 2 Register (CFGCHIP2) .............................................................. 207
10.4.16 Chip Configuration 3 Register (CFGCHIP3) .............................................................. 209
10.4.17 Chip Configuration 4 Register (CFGCHIP4) .............................................................. 210
10.4.18 VTP I/O Control Register (VTPIO_CTL) ................................................................... 210
10.4.19 DDR Slew Register (DDR_SLEW) ......................................................................... 212
10.4.20 Deep Sleep Register (DEEPSLEEP) ...................................................................... 213
10.4.21 Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................... 214
10.4.22 Pullup/Pulldown Select Register (PUPD_SEL) ........................................................... 214
10.4.23 RXACTIVE Control Register (RXACTIVE) ................................................................ 216
11 ARM Interrupt Controller (AINTC) ....................................................................................... 217
11.1 Introduction ............................................................................................................... 218
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11.2 Interrupt Mapping ........................................................................................................ 218
11.3 AINTC Methodology ..................................................................................................... 221
11.3.1 Interrupt Processing ........................................................................................... 221
11.3.2 Interrupt Enabling .............................................................................................. 222
11.3.3 Interrupt Status Checking ..................................................................................... 222
11.3.4 Interrupt Channel Mapping ................................................................................... 222
11.3.5 Host Interrupt Mapping Interrupts ............................................................................ 222
11.3.6 Interrupt Prioritization .......................................................................................... 223
11.3.7 Interrupt Nesting ............................................................................................... 223
11.3.8 Interrupt Vectorization ......................................................................................... 224
11.3.9 Interrupt Status Clearing ...................................................................................... 225
11.3.10 Interrupt Disabling ............................................................................................ 225
11.4 AINTC Registers ......................................................................................................... 225
11.4.1 Revision Identification Register (REVID) ................................................................... 226
11.4.2 Control Register (CR) ......................................................................................... 227
11.4.3 Global Enable Register (GER) ............................................................................... 228
11.4.4 Global Nesting Level Register (GNLR) ..................................................................... 228
11.4.5 System Interrupt Status Indexed Set Register (SISR) .................................................... 229
11.4.6 System Interrupt Status Indexed Clear Register (SICR) .................................................. 229
11.4.7 System Interrupt Enable Indexed Set Register (EISR) ................................................... 230
11.4.8 System Interrupt Enable Indexed Clear Register (EICR) ................................................. 230
11.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) .................................................... 231
11.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) ................................................ 231
11.4.11 Vector Base Register (VBR) ................................................................................ 232
11.4.12 Vector Size Register (VSR) ................................................................................. 232
11.4.13 Vector Null Register (VNR) ................................................................................. 233
11.4.14 Global Prioritized Index Register (GPIR) .................................................................. 233
11.4.15 Global Prioritized Vector Register (GPVR) ................................................................ 234
11.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) .................................................. 234
11.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) .................................................. 235
11.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3) .................................................. 235
11.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4) .................................................. 236
11.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1) ........................................... 236
11.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2) ........................................... 237
11.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3) ........................................... 237
11.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4) ........................................... 238
11.4.24 System Interrupt Enable Set Register 1 (ESR1) ......................................................... 238
11.4.25 System Interrupt Enable Set Register 2 (ESR2) ......................................................... 239
11.4.26 System Interrupt Enable Set Register 3 (ESR3) ......................................................... 239
11.4.27 System Interrupt Enable Set Register 4 (ESR4) ......................................................... 240
11.4.28 System Interrupt Enable Clear Register 1 (ECR1) ....................................................... 240
11.4.29 System Interrupt Enable Clear Register 2 (ECR2) ....................................................... 241
11.4.30 System Interrupt Enable Clear Register 3 (ECR3) ....................................................... 241
11.4.31 System Interrupt Enable Clear Register 4 (ECR4) ....................................................... 242
11.4.32 Channel Map Registers (CMR0-CMR25) ................................................................. 242
11.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1) ..................................................... 243
11.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2) ..................................................... 243
11.4.35 Host Interrupt Nesting Level Register 1 (HINLR1) ....................................................... 244
11.4.36 Host Interrupt Nesting Level Register 2 (HINLR2) ....................................................... 244
11.4.37 Host Interrupt Enable Register (HIER) .................................................................... 245
11.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) ................................................... 246
11.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) ................................................... 246
12 Boot Considerations ........................................................................................................ 247
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12.1 Introduction ............................................................................................................... 248
A Revision History .............................................................................................................. 249
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List of Figures
1-1. AM1802 ARM Microprocessor Block Diagram ........................................................................ 22
3-1. System Interconnect Block Diagram.................................................................................... 33
5-1. MPU Block Diagram....................................................................................................... 38
5-2. Permission Fields.......................................................................................................... 40
5-3. Revision ID Register (REVID) ........................................................................................... 46
5-4. Configuration Register (CONFIG)....................................................................................... 46
5-5. Interrupt Raw Status/Set Register (IRAWSTAT)...................................................................... 47
5-6. Interrupt Enable Status/Clear Register (IENSTAT) ................................................................... 48
5-7. Interrupt Enable Set Register (IENSET)................................................................................ 49
5-8. Interrupt Enable Clear Register (IENCLR)............................................................................. 49
5-9. Fixed Range Start Address Register (FXD_MPSAR) ................................................................ 50
5-10. Fixed Range End Address Register (FXD_MPEAR) ................................................................. 50
5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)......................................... 51
5-12. MPU1 Programmable Range nStart Address Register (PROGn_MPSAR)....................................... 52
5-13. MPU2 Programmable Range nStart Address Register (PROGn_MPSAR)....................................... 52
5-14. MPU1 Programmable Range nEnd Address Register (PROGn_MPEAR)........................................ 53
5-15. MPU2 Programmable Range nEnd Address Register (PROGn_MPEAR)........................................ 53
5-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA).......................... 54
5-17. Fault Address Register (FLTADDRR) .................................................................................. 55
5-18. Fault Status Register (FLTSTAT) ....................................................................................... 56
5-19. Fault Clear Register (FLTCLR).......................................................................................... 57
6-1. Overall Clocking Diagram ................................................................................................ 61
6-2. USB Clocking Diagram ................................................................................................... 63
6-3. DDR2/mDDR Memory Controller Clocking Diagram.................................................................. 65
6-4. EMIFA Clocking Diagram................................................................................................. 66
6-5. EMAC Clocking Diagram................................................................................................. 67
6-6. McASP Clocking Diagram................................................................................................ 68
7-1. PLLC Structure ............................................................................................................ 73
7-2. PLLC0 Revision Identification Register (REVID)...................................................................... 78
7-3. PLLC1 Revision Identification Register (REVID)...................................................................... 79
7-4. Reset Type Status Register (RSTYPE) ................................................................................ 79
7-5. Reset Control Register (RSCTRL) ...................................................................................... 80
7-6. PLLC0 Control Register (PLLCTL)...................................................................................... 81
7-7. PLLC1 Control Register (PLLCTL)...................................................................................... 82
7-8. PLLC0 OBSCLK Select Register (OCSEL)............................................................................ 83
7-9. PLLC1 OBSCLK Select Register (OCSEL)............................................................................ 84
7-10. PLL Multiplier Control Register (PLLM)................................................................................. 85
7-11. PLLC0 Pre-Divider Control Register (PREDIV) ....................................................................... 85
7-12. PLLC0 Divider 1 Register (PLLDIV1)................................................................................... 86
7-13. PLLC1 Divider 1 Register (PLLDIV1)................................................................................... 86
7-14. PLLC0 Divider 2 Register (PLLDIV2) .................................................................................. 87
7-15. PLLC1 Divider 2 Register (PLLDIV2) .................................................................................. 87
7-16. PLLC0 Divider 3 Register (PLLDIV3) .................................................................................. 88
7-17. PLLC1 Divider 3 Register (PLLDIV3) .................................................................................. 88
7-18. PLLC0 Divider 4 Register (PLLDIV4)................................................................................... 89
7-19. PLLC0 Divider 5 Register (PLLDIV5)................................................................................... 89
7-20. PLLC0 Divider 6 Register (PLLDIV6)................................................................................... 90
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7-21. PLLC0 Divider 7 Register (PLLDIV7)................................................................................... 90
7-22. PLLC0 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 91
7-23. PLLC1 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 91
7-24. PLL Post-Divider Control Register (POSTDIV)........................................................................ 92
7-25. PLL Controller Command Register (PLLCMD)........................................................................ 92
7-26. PLL Controller Status Register (PLLSTAT)............................................................................ 93
7-27. PLLC0 Clock Align Control Register (ALNCTL)....................................................................... 94
7-28. PLLC1 Clock Align Control Register (ALNCTL)....................................................................... 95
7-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)........................................................ 96
7-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)........................................................ 97
7-31. PLLC0 Clock Enable Control Register (CKEN) ....................................................................... 98
7-32. PLLC1 Clock Enable Control Register (CKEN) ....................................................................... 98
7-33. PLLC0 Clock Status Register (CKSTAT)............................................................................... 99
7-34. PLLC1 Clock Status Register (CKSTAT) ............................................................................. 100
7-35. PLLC0 SYSCLK Status Register (SYSTAT) ......................................................................... 101
7-36. PLLC1 SYSCLK Status Register (SYSTAT) ......................................................................... 102
7-37. Emulation Performance Counter 0 Register (EMUCNT0).......................................................... 103
7-38. Emulation Performance Counter 1 Register (EMUCNT1).......................................................... 103
8-1. Revision Identification Register (REVID) ............................................................................. 115
8-2. Interrupt Evaluation Register (INTEVAL) ............................................................................. 115
8-3. PSC0 Module Error Pending Register 0 (MERRPR0) .............................................................. 116
8-4. PSC1 Module Error Pending Register 0 (MERRPR0) .............................................................. 116
8-5. PSC0 Module Error Clear Register 0 (MERRCR0).................................................................. 117
8-6. PSC1 Module Error Clear Register 0 (MERRCR0).................................................................. 117
8-7. Power Error Pending Register (PERRPR)............................................................................ 118
8-8. Power Error Clear Register (PERRCR)............................................................................... 118
8-9. Power Domain Transition Command Register (PTCMD)........................................................... 119
8-10. Power Domain Transition Status Register (PTSTAT)............................................................... 120
8-11. Power Domain 0 Status Register (PDSTAT0) ....................................................................... 121
8-12. Power Domain 1 Status Register (PDSTAT1) ....................................................................... 122
8-13. Power Domain 0 Control Register (PDCTL0)........................................................................ 123
8-14. Power Domain 1 Control Register (PDCTL1)........................................................................ 124
8-15. Power Domain 0 Configuration Register (PDCFG0) ................................................................ 125
8-16. Power Domain 1 Configuration Register (PDCFG1) ................................................................ 126
8-17. Module Status nRegister (MDSTATn)................................................................................ 127
8-18. PSC0 Module Control nRegister (MDCTLn)......................................................................... 128
8-19. PSC1 Module Control nRegister (MDCTLn)......................................................................... 129
9-1. Deep Sleep Mode Sequence........................................................................................... 141
10-1. Revision Identification Register (REVID) ............................................................................. 150
10-2. Device Identification Register 0 (DEVIDR0).......................................................................... 150
10-3. Boot Configuration Register (BOOTCFG) ............................................................................ 151
10-4. Kick 0 Register (KICK0R)............................................................................................... 152
10-5. Kick 1 Register (KICK1R)............................................................................................... 152
10-6. Host 0 Configuration Register (HOST0CFG)......................................................................... 153
10-7. Interrupt Raw Status/Set Register (IRAWSTAT)..................................................................... 154
10-8. Interrupt Enable Status/Clear Register (IENSTAT).................................................................. 155
10-9. Interrupt Enable Register (IENSET)................................................................................... 156
10-10. Interrupt Enable Clear Register (IENCLR)............................................................................ 156
10-11. End of Interrupt Register (EOI)......................................................................................... 157
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10-12. Fault Address Register (FLTADDRR)................................................................................. 157
10-13. Fault Status Register (FLTSTAT)...................................................................................... 158
10-14. Master Priority 0 Register (MSTPRI0)................................................................................. 159
10-15. Master Priority 1 Register (MSTPRI1)................................................................................. 160
10-16. Master Priority 2 Register (MSTPRI2)................................................................................. 161
10-17. Pin Multiplexing Control 0 Register (PINMUX0) ..................................................................... 162
10-18. Pin Multiplexing Control 1 Register (PINMUX1) ..................................................................... 164
10-19. Pin Multiplexing Control 2 Register (PINMUX2) ..................................................................... 166
10-20. Pin Multiplexing Control 3 Register (PINMUX3) ..................................................................... 168
10-21. Pin Multiplexing Control 4 Register (PINMUX4) ..................................................................... 170
10-22. Pin Multiplexing Control 5 Register (PINMUX5) ..................................................................... 172
10-23. Pin Multiplexing Control 6 Register (PINMUX6) ..................................................................... 174
10-24. Pin Multiplexing Control 7 Register (PINMUX7) ..................................................................... 176
10-25. Pin Multiplexing Control 8 Register (PINMUX8) ..................................................................... 178
10-26. Pin Multiplexing Control 9 Register (PINMUX9) ..................................................................... 180
10-27. Pin Multiplexing Control 10 Register (PINMUX10) .................................................................. 182
10-28. Pin Multiplexing Control 11 Register (PINMUX11) .................................................................. 184
10-29. Pin Multiplexing Control 12 Register (PINMUX12) .................................................................. 186
10-30. Pin Multiplexing Control 13 Register (PINMUX13) .................................................................. 188
10-31. Pin Multiplexing Control 14 Register (PINMUX14) .................................................................. 190
10-32. Pin Multiplexing Control 15 Register (PINMUX15) .................................................................. 192
10-33. Pin Multiplexing Control 16 Register (PINMUX16) .................................................................. 193
10-34. Pin Multiplexing Control 17 Register (PINMUX17) .................................................................. 195
10-35. Pin Multiplexing Control 18 Register (PINMUX18) .................................................................. 197
10-36. Pin Multiplexing Control 19 Register (PINMUX19) .................................................................. 199
10-37. Suspend Source Register (SUSPSRC)............................................................................... 201
10-38. Chip Signal Register (CHIPSIG)....................................................................................... 203
10-39. Chip Signal Clear Register (CHIPSIG_CLR)......................................................................... 204
10-40. Chip Configuration 0 Register (CFGCHIP0).......................................................................... 205
10-41. Chip Configuration 1 Register (CFGCHIP1).......................................................................... 206
10-42. Chip Configuration 2 Register (CFGCHIP2).......................................................................... 207
10-43. Chip Configuration 3 Register (CFGCHIP3).......................................................................... 209
10-44. Chip Configuration 4 Register (CFGCHIP4).......................................................................... 210
10-45. VTP I/O Control Register (VTPIO_CTL) .............................................................................. 210
10-46. DDR Slew Register (DDR_SLEW)..................................................................................... 212
10-47. Deep Sleep Register (DEEPSLEEP).................................................................................. 213
10-48. Pullup/Pulldown Enable Register (PUPD_ENA)..................................................................... 214
10-49. Pullup/Pulldown Select Register (PUPD_SEL) ...................................................................... 214
10-50. RXACTIVE Control Register (RXACTIVE)............................................................................ 216
11-1. AINTC Interrupt Mapping ............................................................................................... 218
11-2. Flow of System Interrupts to Host ..................................................................................... 221
11-3. Revision Identification Register (REVID) ............................................................................. 226
11-4. Control Register (CR) ................................................................................................... 227
11-5. Global Enable Register (GER) ......................................................................................... 228
11-6. Global Nesting Level Register (GNLR) ............................................................................... 228
11-7. System Interrupt Status Indexed Set Register (SISR) .............................................................. 229
11-8. System Interrupt Status Indexed Clear Register (SICR)............................................................ 229
11-9. System Interrupt Enable Indexed Set Register (EISR) ............................................................. 230
11-10. System Interrupt Enable Indexed Clear Register (EICR)........................................................... 230
11
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11-11. Host Interrupt Enable Indexed Set Register (HEISR)............................................................... 231
11-12. Host Interrupt Enable Indexed Clear Register (HIEICR)............................................................ 231
11-13. Vector Base Register (VBR)............................................................................................ 232
11-14. Vector Size Register (VSR)............................................................................................. 232
11-15. Vector Null Register (VNR)............................................................................................. 233
11-16. Global Prioritized Index Register (GPIR) ............................................................................. 233
11-17. Global Prioritized Vector Register (GPVR) ........................................................................... 234
11-18. System Interrupt Status Raw/Set Register 1 (SRSR1) ............................................................. 234
11-19. System Interrupt Status Raw/Set Register 2 (SRSR2) ............................................................. 235
11-20. System Interrupt Status Raw/Set Register 3 (SRSR3) ............................................................. 235
11-21. System Interrupt Status Raw/Set Register 4 (SRSR4) ............................................................. 236
11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) ...................................................... 236
11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) ...................................................... 237
11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) ...................................................... 237
11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) ...................................................... 238
11-26. System Interrupt Enable Set Register 1 (ESR1)..................................................................... 238
11-27. System Interrupt Enable Set Register 2 (ESR2)..................................................................... 239
11-28. System Interrupt Enable Set Register 3 (ESR3)..................................................................... 239
11-29. System Interrupt Enable Set Register 4 (ESR4)..................................................................... 240
11-30. System Interrupt Enable Clear Register 1 (ECR1) .................................................................. 240
11-31. System Interrupt Enable Clear Register 2 (ECR2) .................................................................. 241
11-32. System Interrupt Enable Clear Register 3 (ECR3) .................................................................. 241
11-33. System Interrupt Enable Clear Register 4 (ECR4) .................................................................. 242
11-34. Channel Map Registers (CMRn)....................................................................................... 242
11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) ................................................................ 243
11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) ................................................................ 243
11-37. Host Interrupt Nesting Level Register 1 (HINLR1) .................................................................. 244
11-38. Host Interrupt Nesting Level Register 2 (HINLR2) .................................................................. 244
11-39. Host Interrupt Enable Register (HIER)................................................................................ 245
11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) .............................................................. 246
11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) .............................................................. 246
12 List of Figures SPRUGX5A–May 2011
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List of Tables
2-1. Exception Vector Table for ARM ........................................................................................ 26
2-2. Different Address Types in ARM System .............................................................................. 28
3-1. AM1802 ARM Microprocessor System Interconnect Matrix ......................................................... 32
5-1. MPU Memory Regions.................................................................................................... 39
5-2. MPU Default Configuration............................................................................................... 39
5-3. Device Master Settings ................................................................................................... 40
5-4. Request Type Access Controls.......................................................................................... 41
5-5. MPU_BOOTCFG_ERR Interrupt Sources ............................................................................. 43
5-6. Memory Protection Unit 1 (MPU1) Registers.......................................................................... 44
5-7. Memory Protection Unit 2 (MPU2) Registers.......................................................................... 44
5-8. Revision ID Register (REVID) Field Descriptions ..................................................................... 46
5-9. Configuration Register (CONFIG) Field Descriptions................................................................. 46
5-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................ 47
5-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions............................................. 48
5-12. Interrupt Enable Set Register (IENSET) Field Descriptions ......................................................... 49
5-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions....................................................... 49
5-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions .................. 51
5-15. MPU1 Programmable Range nStart Address Register (PROGn_MPSAR) Field Descriptions ................ 52
5-16. MPU2 Programmable Range nStart Address Register (PROGn_MPSAR) Field Descriptions ................ 52
5-17. MPU1 Programmable Range nEnd Address Register (PROGn_MPEAR) Field Descriptions ................. 53
5-18. MPU2 Programmable Range nEnd Address Register (PROGn_MPEAR) Field Descriptions ................. 53
5-19. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions ... 54
5-20. Fault Address Register (FLTADDRR) Field Descriptions ............................................................ 55
5-21. Fault Status Register (FLTSTAT) Field Descriptions................................................................. 56
5-22. Fault Clear Register (FLTCLR) Field Descriptions.................................................................... 57
6-1. Device Clock Inputs....................................................................................................... 60
6-2. System Clock Domains................................................................................................... 60
6-3. Example PLL Frequencies .............................................................................................. 63
6-4. USB Clock Multiplexing Options......................................................................................... 63
6-5. DDR2/mDDR Memory Controller MCLK Frequencies................................................................ 65
6-6. EMIFA Frequencies....................................................................................................... 66
6-7. EMAC Reference Clock Frequencies................................................................................... 68
6-8. Peripherals ................................................................................................................. 69
7-1. System PLLC Output Clocks............................................................................................. 74
7-2. PLL Controller 0 (PLLC0) Registers .................................................................................... 77
7-3. PLL Controller 1 (PLLC1) Registers .................................................................................... 78
7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions................................................ 78
7-5. PLLC1 Revision Identification Register (REVID) Field Descriptions................................................ 79
7-6. Reset Type Status Register (RSTYPE) Field Descriptions .......................................................... 79
7-7. Reset Control Register (RSCTRL) Field Descriptions................................................................ 80
7-8. PLLC0 Control Register (PLLCTL) Field Descriptions................................................................ 81
7-9. PLLC1 Control Register (PLLCTL) Field Descriptions................................................................ 82
7-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions...................................................... 83
7-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions...................................................... 84
7-12. PLL Multiplier Control Register (PLLM) Field Descriptions .......................................................... 85
7-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................. 85
7-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions............................................................. 86
13
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7-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions............................................................. 86
7-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions............................................................. 87
7-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions............................................................. 87
7-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions............................................................. 88
7-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions............................................................. 88
7-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions............................................................. 89
7-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions............................................................. 89
7-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions............................................................. 90
7-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions............................................................. 90
7-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................. 91
7-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................. 91
7-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions.................................................. 92
7-27. PLL Controller Command Register (PLLCMD) Field Descriptions.................................................. 92
7-28. PLL Controller Status Register (PLLSTAT) Field Descriptions...................................................... 93
7-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions................................................. 94
7-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions................................................. 95
7-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions.................................. 96
7-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions.................................. 97
7-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................. 98
7-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................. 98
7-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions ........................................................ 99
7-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions....................................................... 100
7-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions................................................... 101
7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions................................................... 102
7-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions.................................... 103
7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions.................................... 103
8-1. PSC0 Default Module Configuration................................................................................... 106
8-2. PSC1 Default Module Configuration................................................................................... 107
8-3. Module States ............................................................................................................ 109
8-4. IcePick Emulation Commands ......................................................................................... 111
8-5. PSC Interrupt Events.................................................................................................... 111
8-6. Power and Sleep Controller 0 (PSC0) Registers .................................................................... 114
8-7. Power and Sleep Controller 1 (PSC1) Registers .................................................................... 114
8-8. Revision Identification Register (REVID) Field Descriptions ....................................................... 115
8-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions....................................................... 115
8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions........................................ 116
8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ........................................... 117
8-12. Power Error Pending Register (PERRPR) Field Descriptions ..................................................... 118
8-13. Power Error Clear Register (PERRCR) Field Descriptions......................................................... 118
8-14. Power Domain Transition Command Register (PTCMD) Field Descriptions .................................... 119
8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................ 120
8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions................................................. 121
8-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions................................................. 122
8-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions.................................................. 123
8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions.................................................. 124
8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions.......................................... 125
8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions.......................................... 126
8-22. Module Status nRegister (MDSTATn) Field Descriptions ......................................................... 127
8-23. PSC0 Module Control nRegister (MDCTLn) Field Descriptions .................................................. 128
14 List of Tables SPRUGX5A–May 2011
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8-24. PSC1 Module Control nRegister (MDCTLn) Field Descriptions .................................................. 129
9-1. Power Management Features.......................................................................................... 133
10-1. Master IDs ................................................................................................................ 147
10-2. Default Master Priority................................................................................................... 148
10-3. System Configuration Module 0 (SYSCFG0) Registers ............................................................ 148
10-4. System Configuration Module 1 (SYSCFG1) Registers ............................................................ 149
10-5. Revision Identification Register (REVID) Field Descriptions ....................................................... 150
10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions ................................................... 150
10-7. Boot Configuration Register (BOOTCFG) Field Descriptions...................................................... 151
10-8. Kick 0 Register (KICK0R) Field Descriptions......................................................................... 152
10-9. Kick 1 Register (KICK1R) Field Descriptions......................................................................... 152
10-10. Host 0 Configuration Register (HOST0CFG) Field Descriptions .................................................. 153
10-11. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions .............................................. 154
10-12. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ........................................... 155
10-13. Interrupt Enable Register (IENSET) Field Descriptions............................................................. 156
10-14. Interrupt Enable Clear Register (IENCLR) Field Descriptions ..................................................... 156
10-15. End of Interrupt Register (EOI) Field Descriptions .................................................................. 157
10-16. Fault Address Register (FLTADDRR) Field Descriptions........................................................... 157
10-17. Fault Status Register (FLTSTAT) Field Descriptions................................................................ 158
10-18. Master Priority 0 Register (MSTPRI0) Field Descriptions .......................................................... 159
10-19. Master Priority 1 Register (MSTPRI1) Field Descriptions .......................................................... 160
10-20. Master Priority 2 Register (MSTPRI2) Field Descriptions .......................................................... 161
10-21. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions............................................... 162
10-22. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions............................................... 164
10-23. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions............................................... 166
10-24. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions............................................... 168
10-25. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions............................................... 170
10-26. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions............................................... 172
10-27. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions............................................... 174
10-28. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions............................................... 176
10-29. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions............................................... 178
10-30. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions............................................... 180
10-31. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions............................................ 182
10-32. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions............................................ 184
10-33. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions............................................ 186
10-34. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions............................................ 188
10-35. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions............................................ 190
10-36. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions............................................ 192
10-37. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions............................................ 193
10-38. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions............................................ 195
10-39. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions............................................ 197
10-40. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions............................................ 199
10-41. Suspend Source Register (SUSPSRC) Field Descriptions......................................................... 201
10-42. Chip Signal Register (CHIPSIG) Field Descriptions................................................................. 203
10-43. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions................................................... 204
10-44. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ................................................... 205
10-45. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ................................................... 206
10-46. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ................................................... 207
10-47. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ................................................... 209
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10-48. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ................................................... 210
10-49. VTP I/O Control Register (VTPIO_CTL) Field Descriptions........................................................ 211
10-50. DDR Slew Register (DDR_SLEW) Field Descriptions .............................................................. 212
10-51. Deep Sleep Register (DEEPSLEEP) Field Descriptions ........................................................... 213
10-52. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions............................................... 214
10-53. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions................................................ 214
10-54. Pullup/Pulldown Select Register (PUPD_SEL) Default Values.................................................... 215
10-55. RXACTIVE Control Register (RXACTIVE) Field Descriptions ..................................................... 216
11-1. AINTC System Interrupt Assignments ................................................................................ 219
11-2. ARM Interrupt Controller (AINTC) Registers ......................................................................... 225
11-3. Revision Identification Register (REVID) Field Descriptions ....................................................... 226
11-4. Control Register (CR) Field Descriptions ............................................................................. 227
11-5. Global Enable Register (GER) Field Descriptions................................................................... 228
11-6. Global Nesting Level Register (GNLR) Field Descriptions ......................................................... 228
11-7. System Interrupt Status Indexed Set Register (SISR) Field Descriptions........................................ 229
11-8. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions ..................................... 229
11-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions....................................... 230
11-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions..................................... 230
11-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions......................................... 231
11-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions ..................................... 231
11-13. Vector Base Register (VBR) Field Descriptions ..................................................................... 232
11-14. Vector Size Register (VSR) Field Descriptions ...................................................................... 232
11-15. Vector Null Register (VNR) Field Descriptions....................................................................... 233
11-16. Global Prioritized Index Register (GPIR) Field Descriptions....................................................... 233
11-17. Global Prioritized Vector Register (GPVR) Field Descriptions..................................................... 234
11-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions....................................... 234
11-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions....................................... 235
11-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions....................................... 235
11-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions....................................... 236
11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions ................................ 236
11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions ................................ 237
11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions ................................ 237
11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions ................................ 238
11-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions .............................................. 238
11-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions .............................................. 239
11-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions .............................................. 239
11-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions .............................................. 240
11-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions............................................ 240
11-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions............................................ 241
11-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions............................................ 241
11-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions............................................ 242
11-34. Channel Map Registers (CMRn) Field Descriptions................................................................. 242
11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions.......................................... 243
11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions.......................................... 243
11-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ............................................ 244
11-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions ............................................ 244
11-39. Host Interrupt Enable Register (HIER) Field Descriptions.......................................................... 245
11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions........................................ 246
11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions........................................ 246
16 List of Tables SPRUGX5A–May 2011
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A-1. Document Revision History............................................................................................. 249
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Preface
SPRUGX5A–May 2011
Read This First
About This Manual
Describes the System-on-Chip (SoC) system. This document provides an overview of the system and the
following considerations associated with it:
•ARM subsystem
•System interconnect
•System memory
•Memory protection unit (MPU)
•Device clocking
•Phase-locked loop controller (PLLC)
•Power and sleep controller (PSC)
•Power management
•System configuration (SYSCFG) module
•ARM interrupt controller (AINTC)
•Boot considerations
Notational Conventions
This document uses the following conventions.
•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
•Registers in this document are shown in figures and described in tables.
–Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
–Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the AM18x ARM Microprocessors. Copies of these documents are
available on the Internet at www.ti.com.Tip: Enter the literature number in the search box provided at
www.ti.com.
The current documentation that describes the related peripherals, and other technical collateral, is
available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFU0 —AM17x/AM18x ARM Microprocessors Peripherals Overview Reference Guide.
Provides an overview and briefly describes the peripherals available on the AM17x/AM18x ARM
Microprocessors.
19
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