Texas Instruments PCI7620 User manual

Application Report
SCPU019 - July 2003
1
PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
Computer Connectivity Solutions
ABSTRACT
This document is provided to assist platform designers using the PCIXX20 (PCI7620,
PCI7420, PCI6620, or PCI6420) dual-socket CardBus and SmartCard controller with
integrated 1394a and dedicated Secure Digital/Multimedia Card and Memory
Stick/Memory Stick-Pro sockets. Detailed information can be found in the PCIXX20 data
manual. However, this document provides design suggestions for the various options
when designing in the PCIXX20 controller.
HOW TO USE THIS DOCUMENT
This document covers implementation guidance for all four PCIXX20 controllers. In order
to efficiently utilize this document, each controller with its relevant sections is listed below:
Section PCI7620 PCI7420 PCI6620 PCI6420
1 1.1 1.2 1.3 1.4
2 All All All All
3 All All All All
4 All All All All
5 All All All All
6 All - All -
7 All All All All
8 All All 8.3 8.3
9 All All All All
10 All All All All
11 All All All All
12 All All All All
13 All - All -

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2PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
Contents
1PCIXX20 Implementation Configuration ..................................................................................... 6
1.1 PCI7620 Implementation Configuration .................................................................................. 6
1.2 PCI7420 Implementation Configuration .................................................................................. 6
1.3 PCI6620 Implementation Configuration .................................................................................. 7
1.4 PCI6420 Implementation Configuration .................................................................................. 8
2Power Considerations ................................................................................................................. 9
2.1 Power Pin Description and Internal Voltage Regulator ........................................................... 9
2.2 Device Power Sequence ........................................................................................................ 9
2.3 Bypass Capacitors.................................................................................................................. 9
2.3.1 V
CC
, V
CCP
, V
CCA
, and V
CCB
............................................................................................ 9
2.3.2 VR_PORT................................................................................................................. 10
2.3.3 VDPLL and AVDx ..................................................................................................... 10
2.3.4 Flash Media Socket Power ....................................................................................... 10
3Power Switch Implementation................................................................................................... 11
3.1 CardBus Power Switch......................................................................................................... 11
3.2 Flash Media Power Switch ................................................................................................... 12
4PCI Bus Interface ....................................................................................................................... 13
5PC Card Interface ....................................................................................................................... 15
5.1 Operation Modes.................................................................................................................. 15
5.2 Implementing the PCIXX20 Controller as Single CardBus Socket Device ............................ 15
6UltraMedia™ Smart Card Interfaces ......................................................................................... 16
6.1.1 Socket V
CC
................................................................................................................ 17
6.1.2 CLK, RST, and I/O .................................................................................................... 18
6.1.3 General Layout Recommendations........................................................................... 18
7Flash Media Interfaces............................................................................................................... 20
7.1 Dedicated Flash Media Socket ............................................................................................. 20
7.1.1 Universal Power Switch Implementation ................................................................... 20
7.1.2 Dedicated Secure Digital/Multimedia Card Socket .................................................... 22
7.1.3 Dedicated Memory Stick/Memory Stick-Pro Card Socket.......................................... 24
7.1.4 Flash Media Support With 2-In-1 Socket Connector.................................................. 26
8PHY Port Cable Connection ...................................................................................................... 29
8.1 Crystal Selection .................................................................................................................. 30
8.2 EMI Guidelines ..................................................................................................................... 32
8.3 Disabling IEEE1394 Ports .................................................................................................... 33
8.3.1 Pin Strapping of the Unused 1394 Terminals ............................................................ 33
9Miscellaneous Pin Interface ...................................................................................................... 34
9.1 Multifunction Terminals.........................................................................................................34
9.2 SPKROUT............................................................................................................................ 34
9.3 SUSPEND ......................................................................................................................... 34
10 Interrupt Configurations ............................................................................................................ 35
10.1 Parallel PCI Interrupts Only .................................................................................................. 35
10.2 Serial IRQ and Parallel PCI Interrupts .................................................................................. 35
10.3 Serial IRQ and Serial PCI Interrupts ..................................................................................... 36
11 Software Considerations ........................................................................................................... 37
11.1 CardBus and UltraMedia
TM
................................................................................................... 37
11.2 EEPROM Configuration........................................................................................................ 37
11.3 EEPROM Programming Guide ............................................................................................. 40

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 3
11.3.1 Serial ROM Offset 00h – CardBus Function Indicator ............................................... 40
11.3.2 Serial ROM Offset 01h – Number of Bytes in EEPROM Map .................................... 40
11.3.3 Serial ROM Offset 02h – Command Register (Function 0)........................................ 40
11.3.4 Serial ROM Offset 03h – Command Register (Function 1)........................................ 41
11.3.5 Serial ROM Offset 04h – Subsystem Vendor ID (Byte 0)........................................... 41
11.3.6 Serial ROM Offset 05h – Subsystem Vendor ID (Byte 1)........................................... 41
11.3.7 Serial ROM Offset 06h – Subsystem ID (Byte 0)....................................................... 42
11.3.8 Serial ROM Offset 07h – Subsystem ID (Byte 1)....................................................... 42
11.3.9 Serial ROM Offset 08h – PC Card Legacy-Mode Base Address Register (Byte 0).... 42
11.3.10 Serial ROM Offset 09h – PC Card Legacy-Mode Base Address Register (Byte 1) 42
11.3.11 Serial ROM Offset 0Ah – PC Card Legacy-Mode Base Address Register (Byte 2) 42
11.3.12 Serial ROM Offset 0Bh – PC Card Legacy-Mode Base Address Register (Byte 3) 43
11.3.13 Serial ROM Offset 0Ch – System Control Register Byte 0 (Function 0) ................ 43
11.3.14 Serial ROM Offset 0Dh – System Control Register Byte 0 (Function 1) ................ 44
11.3.15 Serial ROM Offset 0Eh – System Control Register Byte 1 .................................... 45
11.3.16 Serial ROM Offset 0Fh – System Control Register Byte 2..................................... 45
11.3.17 Serial ROM Offset 10h – System Control Register Byte 3..................................... 46
11.3.18 Serial ROM Offset 11h – Multifunction Routing Register Byte 0............................ 47
11.3.19 Serial ROM Offset 12h – Multifunction Routing Register Byte 1............................ 47
11.3.20 Serial ROM Offset 13h – Multifunction Routing Register Byte 2............................ 48
11.3.21 Serial ROM Offset 14h – Multifunction Routing Register Byte 3............................ 48
11.3.22 Serial ROM Offset 15h – Retry Status Register..................................................... 48
11.3.23 Serial ROM Offset 16h – Card Control Register.................................................... 49
11.3.24 Serial ROM Offset 17h – Device Control Register................................................. 49
11.3.25 Serial ROM Offset 18h – Diagnostic Register ....................................................... 50
11.3.26 Serial ROM Offset 19h – Power Management Capabilities Register (Function 0) . 50
11.3.27 Serial ROM Offset 1Ah – Power Management Capabilities Register (Function 1) . 51
11.3.28 Serial ROM Offset 1Dh – ExCA Identification and Revision Register .................... 51
11.3.29 Serial ROM Offset 1Eh – General Control Register............................................... 52
11.3.30 Serial ROM Offset 1Fh – General Control Register............................................... 52
11.3.31 Serial ROM Offset 20h – General-Purpose Event Enable Register ....................... 53
11.3.32 Serial ROM Offset 21h – General-Purpose Output Register.................................. 53
11.3.33 Serial ROM Offset 22h – 1394 OHCI Function Indicator ....................................... 54
11.3.34 Serial ROM Offset 23h – Number of Bytes in the 1394 EEPROM Map ................. 54
11.3.35 Serial ROM Offset 24h – Minimum Grant and Maximum Latency Register ........... 54
11.3.36 Serial ROM Offset 25h - Subsystem Identification Register................................... 55
11.3.37 Serial ROM Offset 26h - Subsystem Identification Register................................... 55
11.3.38 Serial ROM Offset 27h - Subsystem Identification Register (Byte 0) ..................... 55
11.3.39 Serial ROM Offset 28h - Subsystem Identification Register (Byte 1) ..................... 56
11.3.40 Serial ROM Offset 29h - Link Enchancement Register and Host Controller Control
Register .................................................................................................................... 56
11.3.41 Serial ROM Offset 2Ah - Mini-ROM Offset in EEPROM Map ................................ 57
11.3.42 Serial ROM Offset 2Bh - GUID High Register (Byte 0) .......................................... 57
11.3.43 Serial ROM Offset 2Ch - GUID High Register (Byte 1).......................................... 57
11.3.44 Serial ROM Offset 2Dh - GUID High Register (Byte 2).......................................... 57
11.3.45 Serial ROM Offset 2Eh - GUID High Register (Byte 3) .......................................... 58
11.3.46 Serial ROM Offset 2Fh - GUID Low Register (Byte 0)........................................... 58
11.3.47 Serial ROM Offset 30h - GUID Low Register (Byte 1) ........................................... 58
11.3.48 Serial ROM Offset 31h - GUID Low Register (Byte2) ............................................ 58

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4PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
11.3.49 Serial ROM Offset 32h - GUID Low Register (Byte 3) ........................................... 59
11.3.50 Serial ROM Offset 34h - Link Enchancement Control Register ............................. 59
11.3.51 Serial ROM Offset 35h - PCI Miscellaneous Configuration Register (Byte 0) ........ 60
11.3.52 Serial ROM Offset 36h - PCI Miscellaneous Configuration Register (Byte 1) ........ 61
11.3.53 Serial ROM Offset 3Ah - PCI PHY Layer Control Register .................................... 61
11.3.54 Serial ROM Offset 3Bh - Flash Media Core Function Indicator ............................. 62
11.3.55 Serial ROM Offset 3Ch - Number of Bytes in EEPROM Map (FlashMedia)........... 62
11.3.56 Serial ROM Offset 3Dh - Subsystem Vendor Identification Register (Byte 0) ........ 62
11.3.57 Serial ROM Offset 3Eh - Subsystem Vendor Identification Register (Byte 1) ........ 62
11.3.58 Serial ROM Offset 3Fh - Subsystem Identification Register (Byte 0)..................... 62
11.3.59 Serial ROM Offset 40h - Subsystem Vendor Identification Register (Byte 1)......... 63
11.3.60 Serial ROM Offset 41h - General Control Register (Function 3) 63
11.3.61 Serial ROM Offset 42h - End-of-list Indicator ........................................................ 63
11.4 Socket Power Lock...............................................................................................................64
11.5 V
CC
Protection ...................................................................................................................... 64
11.6 BIOS Considerations ............................................................................................................ 64
12 Power Management Considerations......................................................................................... 65
12.1 D3 Wake Information............................................................................................................ 65
12.1.1 GRST -Only Registers ............................................................................................. 66
12.1.2 PME Context Registers ........................................................................................... 68
12.2 PME /RI_OUT Behavior .................................................................................................... 68
12.3 CLKRUN Protocol .............................................................................................................. 70
12.4 SUSPEND ......................................................................................................................... 70
13 Migration to PCIXX20 From PCI7X10 ........................................................................................ 71
13.1 Hardware and Pin Assignment Changes .............................................................................. 71
13.2 Software Changes................................................................................................................71
13.3 Configuration Register Changes........................................................................................... 72
13.3.1 Function 0 and Function 1 - CardBus........................................................................ 72
13.3.2 Function 2 – 1394 ..................................................................................................... 74
13.3.3 Function 3 – Flash Media.......................................................................................... 74
14 Migration to PCIXX20 from PCI1620 ......................................................................................... 75
14.1 Hardware and Pin Assignment Changes .............................................................................. 75
14.2 Software Changes................................................................................................................75
14.3 Configuration Register Changes........................................................................................... 76
14.3.1 Function 0 and Function 1 - CardBus........................................................................ 76
14.3.2 Function 2 – 1394 (PCI7X20 Only) ........................................................................... 78
14.3.3 Function 3 – Flash Media.......................................................................................... 78
15 Dedicated SmartCard Implementation Schematic ................................................................... 79
16 Reference Schematics ............................................................................................................... 80
17 References.................................................................................................................................. 80

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 5
Tables
Table 1. Document Sections by Interfaces .................................................................................. 8
Table 2. Power Terminal Description............................................................................................ 9
Table 3. Requirements for Internal/External 1.8-V Core Power Supply.................................... 10
Table 4. Typical Power Switch Configuration............................................................................ 11
Table 5. Card Detect and Voltage Sense Connection for UltraMedia
TM
.................................... 16
Table 6. Query Terminals – Voltage............................................................................................ 16
Table 7. Query Terminals – Smart Card Interface Implementation........................................... 16
Table 8. Smart Card Terminals ................................................................................................... 17
Table 9. SD/MMC Terminals ........................................................................................................ 23
Table 10. MS/MSPRO Terminals ................................................................................................... 25
Table 11. Pin Strapping of the Unused 1394 Terminals .............................................................. 33
Table 12. Interrupt Pin Register Cross Reference ....................................................................... 35
Table 13. PCIXX20 EEPROM Loading Map................................................................................... 38
Table 14. CardBus CSTSCHG and Wake-Up Signals Truth Table .............................................. 69
Table 15. 16 Bit Card RI/STSCHG and Wake-Up Signals Truth Table ........................................ 69
Figures
Figure 1. PCI7620 Typical System Implementation....................................................................... 6
Figure 2. PCI7420 Typical System Implementation....................................................................... 7
Figure 3. PCI6620 Typical System Implementation....................................................................... 7
Figure 4. PCI6420 Typical System Implementation....................................................................... 8
Figure 5. Power Switch Implementation ...................................................................................... 11
Figure 6. Universal Flash Media Power Switch Implementation ................................................ 20
Figure 7. Universal Flash Media Power Switch Implementation (SD/MMC Option) .................. 21
Figure 8. Universal Flash Media Power Switch Implementation (MS/MSPRO Option) ............. 21
Figure 9. Universal Flash Media Power Switch Implementation (2-In-1 Option) ....................... 22
Figure 10. SD/MMC Socket Connector Implementation................................................................ 23
Figure 11. SD/MMC Power Switch Implementation....................................................................... 24
Figure 12. SD/MMC FET Power Switch Implementation ............................................................... 24
Figure 13. MS/MSPRO Socket Connector Implementation........................................................... 25
Figure 14. MS/MSPRO Power Switch Implementation.................................................................. 26
Figure 15. MS/MSPRO FET Power Switch Implementation .......................................................... 26
Figure 16. 2-In-1 Socket Connector Implementation..................................................................... 27
Figure 17. 2-In-1 Power Switch Implementation............................................................................ 27
Figure 18. 2-In-1 FET Power Switch Implementation .................................................................... 28
Figure 19. TP Cable Connections................................................................................................... 29
Figure 20. Typical Compliant DC Isolated Outer Shield Termination .......................................... 29
Figure 21. Non–DC Isolated Outer Shield Termination................................................................. 30
Figure 22. Load Capacitance for the PCI7X20 PHY....................................................................... 31
Figure 23. Recommended Crystal and Capacitor Layout............................................................. 31
Figure 24. Suggested Array at VDPLL and AVDx in Order to Minimize EMI................................ 32
Figure 25. EEPROM Implementation.............................................................................................. 37

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6PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
1 PCIXX20 Implementation Configuration
The PCIXX20 controllers include four different controllers to accommodate a diversity of system
implementations.
•PCI7620 controller
•PCI7420 controller
•PCI6620 controller
•PCI6420 controller
1.1 PCI7620 Implementation Configuration
The PCI7620 (device ID 0xAC8Dh) controller supports five functions (CardBus, Smart Card,
Secure Digital/Multimedia Card, Memory Stick/Memory Stick-Pro, and IEEE 1394a), all of which
can be individually enabled or disabled. For more product information, please refer to the
PCI7620 data manual at http://www.ti.com. Please refer to Table 1 for interface-related
sections.
PCI BUS
Smart Card
NCN 6000 NCN 6000
Smart Card
PCI7620
1394
1394
PC
Card
PC
Card
SD/MMC
MS/MSPRO
EEPROM
(Optional)
Power Switch
Power Switch
Figure 1. PCI7620 Typical System Implementation
1.2 PCI7420 Implementation Configuration
The PCI7420 (device ID 0xAC8Eh) controller supports four functions (CardBus, Secure
Digital/Multimedia Card, Memory Stick/Memory Stick-Pro, and IEEE 1394a), all of which can be
individually enabled or disabled. For more product information, please refer to the PCI7420 data
manual at http://www.ti.com. Please refer to Table 1 for interface-related sections.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 7
PCI BUS
PCI7420
1394
1394
PC
Card
PC
Card
SD/MMC
MS/MSPRO
EEPROM
(Optional)
Power Switch
Power Switch
Figure 2. PCI7420 Typical System Implementation
1.3 PCI6620 Implementation Configuration
The PCI6620 (device ID 0xAC8Dh) controller supports four functions (CardBus, Smart Card,
Secure Digital/Multimedia Card, and Memory Stick/Memory Stick-Pro), all of which can be
individually enabled or disabled. For more product information, please refer to the PCI6620 data
manual at http://www.ti.com. Please refer to Table 1 for interface-related sections.
PCI BUS
Smart Card
NCN
6000 NCN 6000
Smart Card
PCI6620
PC
Card
PC
Card
SD/MMC
MS/MSPRO
EEPROM
(Optional)
Power Switch
Power Switch
Figure 3. PCI6620 Typical System Implementation

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8PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
1.4 PCI6420 Implementation Configuration
The PCI6420 (device ID 0xAC8Eh) controller supports three functions (CardBus, Secure
Digital/Multimedia Card, and Memory Stick/Memory Stick-Pro), all of which can be individually
enabled or disabled. For more product information, please refer to the PCI6420 data manual at
http://www.ti.com. Please refer to Table 1 for interface-related sections.
PCI BUS
PCI6420
PC
Card
PC
Card
SD/MMC
MS/MSPRO
EEPROM
(Optional)
Power Switch
Power Switch
Figure 4. PCI6420 Typical System Implementation
Table 1. Document Sections by Interfaces
Interfaces Section
Device Power 2
Power Switch 3
PCI 4
CardBus 5
EEPROM 11
Smart Card 6
Flash Media 7
1394 8

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 9
2 Power Considerations
2.1 Power Pin Description and Internal Voltage Regulator
The PCIXX20 controller contains different types of power terminals; system designers must pay
close attention to the connections and power-up sequences of these terminals:
Table 2. Power Terminal Description
Terminal Description
AVD2, AVD3, AVD4 Analog circuit power terminals
V
CC
Power supply terminal for I/O and internal voltage regulator. These terminals must all be tied to
system-supplied 3.3-V power source.
V
CCA
, V
CCB
Clamp voltage for PC Card interfaces. Matches socket signaling environment, 5 V or 3.3 V.
V
CCP
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
VR_PORT 1.8-V output from internal voltage regulator when
VR_EN is high, 1.8-V input when VR_EN is
low.
VDPLL PLL circuit power terminal
The PCIXX20 controller uses an internal voltage regulator to power the core logic at 1.8 V. The
voltage regulator is enabled using the
VR_EN terminal. If VR_EN is high, then the voltage
regulator is disabled and VR_PORT serves as a 1.8-V external input to power the core. If
VR_EN is low, then the internal voltage regulator is enabled, VR_PORT serves as a 1.8-V
output.
2.2 Device Power Sequence
Depending on the host platform, different device power sequences are required. For 5-V
tolerant systems, V
CCP
(5 V) must be supplied first, then V
CC
, VDPLL, and AVDx (3.3 V), finally
VR_PORT (1.8 V – only if internal voltage regulator is disabled). For 3-V tolerant systems, V
CC
,
V
CCP
, VDPLL, and AVDx (3.3 V) must be supplied before supplying VR_PORT (1.8 V – only if
internal voltage regulator is disabled).
2.3 Bypass Capacitors
Standard design rules for the power supply bypass must be followed. The following sections are
bypass capacitors recommended by Texas Instruments.
2.3.1 V
CC
, V
CCP
, V
CCA
, and V
CCB
A 0.1-µF bypass capacitor is recommended for each of these power terminals.

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10 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
2.3.2 VR_PORT
A 0.1-µF bypass capacitor is required on the VR_PORT terminal for decoupling.
Table 3. Requirements for Internal/External 1.8-V Core Power Supply
Supply V
CC
VR_EN VR_PORT Note
Internal 3.3 V GND 1.8-V output Internal 1.8-V LDO-VR is enabled. This output is not for external use.
External 3.3 V V
CC
1.8-V input Internal 1.8-V LDO-VR is disabled. An external 1.8-V power supply, of
minimum 50-mA capacity, is required.
2.3.3 VDPLL and AVDx
A parallel combination of high frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended.
2.3.4 Flash Media Socket Power
A parallel combination of a 0.01-µF capacitor and a 10-µF capacitor placed on the power source
close to the flash media socket is recommended.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 11
3 Power Switch Implementation
3.1 CardBus Power Switch
The PCIXX20 controller can be used with any of the dual-slot TPS2228 and TPS222x
(TPS2226, TPS2226A, TPS2224, TPS2224A, TPS2223, and TPS2223A) family of power
switches. As shown in Table 4, bit 10 (12_SW_SEL) in the general control register at PCI
configuration offset 86h can be configured to select the power switch that is implemented. The
TPS222x dual-slot power switch is available in a pin-compatible (30-pin) package that allows
system designers the ability to provide for either voltage level in a single design.
\CLOCK
R1 47K
C9
10uF
SYSTEM3.3V
CLOCK
C4
0.1uF
SYSTEM5V
SOCKETB_Vpp
LATCH
C5
10uF
1. R1 is used only if CLOCK is
generated internally, CLOCK generation
is determined by P2CCLK bit in the
System Control Register (PCI offset 80h,
it 27)
SYSTEM12V
SOCKETA_Vcc
U2
TPS2228 (DB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
5VIN
5VIN
DATA
CLOCK
LATCH
1.8VIN
NC
AVPP/AVCORE
AVCC
AVCC
AVCC
GND
NC
RESET#
3.3VIN 3.3VIN
3.3VIN
OC#
NC
BVCC
BVCC
BVCC
BVPP/BVCORE
NC
SHDN#
NC
NC
1.8VIN
NC
5VIN
DATA
CLOCK
SOCKETB_Vcc
C10
0.1uF
C6
0.1uF
C2
0.1uF
SYSTEM1.8V
DATA
C1
10uF
C3
10uF
SOCKETA_Vpp
LATCH
Figure 5. Power Switch Implementation
Table 4. Typical Power Switch Configuration
Voltage Requirement Power Switch 12V_SW_SEL
1.8 V, 3.3 V, 5 V TPS2228
(recommended)
0
3.3 V, 5 V, 12 V TPS222x 1

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12 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
A power switch is necessary in order to control power to the PC Card sockets. When the
PCIXX20 controller receives a socket power request, it sends the appropriate data across the
P
2
C interface (CLOCK, DATA, and LATCH). In turn, the power switch turns on the appropriate
levels for V
CC
and V
PP
for that socket. CLOCK can be provided either internally or externally
depending on bit 27 (PSCCLK) in the system control register at PCI configuration offset 80h. If
an external clock is used, then the frequency must be between 32 kHz and 100 kHz. If the
internal clock is used, then a 43-k
Ω pulldown resistor is necessary.
3.2 Flash Media Power Switch
Details on Flash Media power switch implementation are described in Section 7.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 13
4 PCI Bus Interface
PCLK, AD31-AD0, C/ BE3 -C/BE0 , PAR, DEVSEL , and FRAME , STOP , TRDY ,
IRDY , GNT , REQ
These terminals can be connected directly to the system PCI bus. GNT and REQ are
dedicated signals from the PCI bus arbitrator. PCLK is a peer-to-peer signal.
o PERR , SERR , and LOCK
PERR and SERR are required signals. LOCK is an optional signal and is available on
the MFUNC terminals.
o IDSEL
IDSEL selects the PCIXX20 controller during configuration space accesses. IDSEL can
be connected to 1 of the upper 21 PCI address lines on the PCI bus.
Please refer to the implementation note:
System Generation of IDSEL in the PCI Local
Bus Specification
, Revision 2.3 (Section 3.2.2.3.5). PCI Local Bus Specification ,
Revision 2.3 (Section 4.2.6, footnote 31) recommends resistive coupling. A 100-
Ω
resistor is recommended.
o PRST and GRST
GRST initializes all registers and state machines of the PCIXX20 controller and PRST
does not. GRST must be asserted during power-on and rebooting. It places the
PCIXX20 controller into the initialized state. PRST does not initialize the global-rest-only
bits or, if PME is enabled, the PME context bits.
o INTA , INTB , INTC , and INTD
For more detailed information concerning these four interrupts, please refer to
Section 10.
o CLKRUN
This signal is optional. However, if saving power is a concern, this signal may be
implemented. Refer to Section 2 of the
PCI Mobile Design Guide Revision 1.1.
o PME
This signal is required for ACPI systems. In a notebook PC, this signal is usually
connected to the south bridge or embedded controller (EC). The PME terminal uses an
open-drain type buffer.

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14 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
o Pullup resistors
Pullup resistors are needed on the following PCI terminals: IRDY , TRDY , FRAME ,
STOP , DEVSEL , PERR , SERR , LOCK , INTA , INTB , INTC , INTD , CLKRUN , and
PME . GRST requires a pullup resistor if the controlling output does not drive high.
Please refer to
PCI Local Bus Specification , Revision 2.3 for precise values of pullup
resistors.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 15
5 PC Card Interface
5.1 Operation Modes
There are two different modes on the PC Card interface. The first is 16-bit mode which is
analogous to the legacy ISA bus. The second is 32-bit CardBus mode which is very similar
to a PCI Bus. The terminal functions for these two modes are multiplexed and routed to the
PC Card socket. The following suggestions apply to the PC Card interface:
o Pullup resistors for the PC Card interface have been integrated into the PCIXX20
controller. These include: A14// CPERR , A15// CIRDY , A19// CBLOCK ,
A20// CSTOP , A21// CDEVSEL , A22// CTRDY , BVD2( SPKR )//CAUDIO,
CD1// CCD1, CD2 // CCD2 , INPACK // CREQ , READY// CINT , RESET// CRST ,
VS1//CVS1, VS2 //CVS2, WAIT // CSERR , and WP(IOIS16 )// CCLKRUN .
o Damping resistor on the CCLK terminal
A series-damping resistor is recommended on the CCLK signal. The damping
resistor is system dependent. If the line impedance is in the 60- to 90-
Ω range, then
a 47-
Ω resistor is recommended (see PC Card Standard , Revision 8).
o CD line filtering
The PCIXX20 controller features the advanced CDx line filtering circuit. It provides
90 ms of noise immunity.
o Socket power supply
For more detailed information concerning the socket power supply, please refer to
Section 3.
o Three PC Card terminals on the socket are not necessary for CardBus mode but are
necessary for 16-bit mode. These terminals are: CRSVD//D14, CRSVD//A18, and
CRSVD//D2. These terminals must be connected to the PC Card socket according to
their 16-bit designations. By default, when in CardBus mode, these terminals are
driven low. They can be placed in a high-impedance state by clearing bit 22
(CBRSVD) in the system control register at PCI configuration offset 80h.
5.2 Implementing the PCIXX20 Controller as Single CardBus Socket Controller
The PCIXX20 controller can be used as a single socket controller simply by leaving the
socket B interface unconnected. The DISABLE_SKTB bit (general control register, PCI
offset 86h, bit 4) must be set to disable function 1 (CardBus socket B). This bit can be set
via EEPROM or BIOS. Unused CardBus socket terminals must be left floating (no
connection).

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16 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
6 UltraMedia™ Smart Card Interfaces
In order to configure one or both of the PCIX620 (PCI7620 or PCI6620) UltraMedia™ CardBus
sockets to be a Smart Card (SC) compatible socket, an SC socket connector (AMP 145300-1 or
equivalent) and an SC electrical interface (NCN6000 or equivalent) must be used. An SC
socket connector mechanically supports and recognizes a PCIX620-supported Smart Card. The
NCN6000 power switch provides the electrical interface between the ICC (Smart Card) and the
PCIX620 controller. The SC socket connector and the NCN6000 power switch function on a
per-socket basis.
Once an SC insertion is detected, the PCIX620 controller asserts the socket query driver signal
(SQRYDRV) high and monitors the SQRY [6:1] signals to determine the UltraMedia
TM
interface
type and its corresponding voltage requirements. The query signal assignments are given in
Tables 5, 6, and 7.
Table 5. Card Detect and Voltage Sense Connection for UltraMedia
TM
CD2 // CCD2 CD1 // CCD1
VS2 //CVS2 VS1 //CVS1 Key Interface Voltage
GND CVS1 GND
CCD1 LV UltraMedia
TM
Per Query terminals
Table 6. Query Terminals – Voltage
SQRY2 SQRY1 Card Voltage
0 1 V
CC
= 5 V, V
PP
= 3.3 V
Table 7. Query Terminals – Smart Card Interface Implementation
SQRY6 SQRY5 SQRY4 SQRY3 Interface Implementation
0 1 0 0 Smart Card interface
Note:
If a 1 value is needed for a query terminal, then that terminal is connected
to the query driver terminal through a 10-kΩresistor. If a 0 value is
needed for a query terminal, then that terminal is connected to ground.
For the Smart Card socket implementation, please follow the guidelines in Dedicated Smart
Card Socket Implementation Schematics in Section 15. In this particular implementation, an
AMP 145300-1 socket connector was used.
All non-Smart Card related terminals can be left unconnected.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 17
Table 8. Smart Card Terminals
SLOT A SLOT BNAME
GHK GHK
MC_CD C08 H13
SC_CLK B08 H17
SC_FCB E08 G18
SC_GPIO0 C07 F19
SC_GPIO1 B06 F17
SC_GPIO2 A05 G15
SC_GPIO3 B05 E18
SC_GPIO4 C05 F15
SC_GPIO5 E06 C19
SC_GPIO6 A03 D17
SC_IO B07 H15
SC_RFU E09 H19
SC_RST A07 G17
SQRYDR A06 H14
SQRY1 B08 H17
SQRY2 C06 E19
SQRY3 B02 B18
SQRY4 F06 E17
SQRY5 B04 D18
SQRY6 B01 C17
SQRY7 C03 A18
SQRY8 D03 B16
SQRY9 D01 A16
SQRY10 E03 E13
The electrical interface between the Smart Card and the reader is provided via the NCN6000
power switch. Due to the stringent voltage requirements for the socket V
CC
and the three
interface signals, there are some strict implementation requirements as well as several optional
recommendations that help meet the level 1 type approval requirements.
6.1.1 Socket V
CC
The V
CC
to the socket is provided via an integrated switching regulator in the NCN6000 power
switch. A 22-µH inductor (L2) with an ESR less than 2
Ω is recommended to optimize the dc/dc
conversion efficiency. The Murata LQH3C220K04 or equivalent is suggested.

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18 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
Capacitor C14 stores the energy at the CRD_VCC output. To minimize ripple, which is critical in
meeting the Europay, MasterCard, and Visa specification 2000 (EMV) V
CC
output requirements,
ceramic X7R capacitors are recommended for C14 and C15.
In addition, it has been found that placement of a 0.1-µF capacitor (C20) on SC_VCC near the
socket is critical to minimize the voltage transients introduced during the V
CC
transient tests.
The reference implementation includes a 10-k
Ω resistor (R16) from SC_VCC to ground to
provide a fixed load. This component also allows the output voltage to be modified based on the
loading, for example, if the output on the implementation is regulating too high.
6.1.2 CLK, RST, and I/O
EMV 2000 specifies requirements for V
OH
, V
OL
, rise/fall time, and perturbation limits for the three
interface signals. Design options have been implemented to address these requirements.
Previous level one testing has indicated that resistor and capacitor components on CLK (R18,
C18) and RST (R19, C19) have been necessary to adjust the rise and fall times to reduce the
overshoot and undershoot perturbations due to fast rise and fall times. In addition, the load
provided by the resistor can allow for adjustment of the output high and low voltages.
It is also recommended that option pads for R17 and C17 be placed for I/O. These components,
like those on CLK and RST, allow for adjustment of the rise and fall time which can affect the
perturbations as well as the loading which can affect the V
OH
/V
OL
measurements. Past
experience has shown that a 100-pF capacitor may be necessary to reduce perturbations on I/O
due to fast rise and fall times. The resistor is typically not necessary. Evaluation of the V
OH
, V
OL
,
t
r
/t
f
, and perturbations as well as the input requirements can determine if these components are
required.
6.1.3 General Layout Recommendations
To meet the V
OH
/V
OL
and perturbation requirements care must be taken to avoid noise coupling
on the CLK, RST, and I/O signals. If possible, it is recommended to route parallel ground traces
beside CLK to reduce noise coupling of the CLK onto the RST and I/O signals.
The coupling of other signals in the system must be considered based on proximity to other
noise sources such as switching regulators, high-speed clocks, etc. If the trace length between
the NCN6000 power switch and the socket exceeds 1.5", then 15-mil spacing is recommended
for the CLK, RST, and I/O traces (assuming a 5-mil trace width). This is to prevent noise
coupling due to long parallel runs to adjacent signals. Otherwise, 2-mil spacing must be
maintained.
The bulk and decoupling capacitor (C14, C15, and C16) as well as the inductor L2 must be
placed near the NCN6000 power switch. Ceramic X7R capacitors are suggested for C14, C15,
and C16 to minimize the ripple on the output voltage. L2 must be 22 µH with an ESR < 2
Ω .
Murata LQH3C220K04 or equivalent is recommended.
Placement of C20 on SC_VCC must be near the socket to prevent large transients on the socket
V
CC
during the switched load tests.
The placement of components R17, R18, R19, C17, C18, and C19 are not as critical and can be
placed near the NCN6000 power switch or the socket, whichever is convenient.

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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide 19
An optional ferrite (Murata BLM15AG121SN1 or equivalent) may be included to minimize V
CC
noise to the NCN6000 power switch. If an option is included, then a 0-
Ω resistor may be
populated by default and populated with the ferrite only if it is found that the supply voltage input
is excessively noisy.

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20 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
7 Flash Media Interfaces
7.1 Dedicated Flash Media Socket
The PCIXX20 controller has two dedicated flash media sockets: one dedicated to support
Secure Digital/Multimedia Card (SD/MMC), and the other to support Memory Stick/Memory
Stick-Pro (MS/MSPRO). The two dedicated flash media sockets can be used concurrently.
7.1.1 Universal Power Switch Implementation
Due to the cross-platform consideration for many system designers, Texas Instruments has
implemented a power switch implementation that maximizes the configurability and minimizes
routing and layout changes for the flash media implementation.
R8
0
SD / MMC _VC C
R5
0-NF
MS/MSPRO_VCC
MC_PWR_CTRL_0
R9
100K
R4
0 - NF
R11 0-NF
MC_PWR_CTRL_1
Single Input Inverter Gate
U1-1
SN74AUC1GU04
2
3 4
5
1
EVM3.3V
R7
0
R3 0
R6
0-NF
Q1
P-Channel Transistor BSO 203P
1
2
3
4 5
6
7
8
S1
G1
S2
G2 D2
D2
D1
D1
Single Input Inverter Gate
U2-1
SN74AUC1GU04
2
3 4
5
1
R10
100K
Figure 6. Universal Flash Media Power Switch Implementation
The implementation in Figure 6 allows for concurrent operation between SD/MMC and
MS/MSPRO. In this implementation, a dual P-channel transistor (BSO 203P or equivalent) and
two single inverting gates (SN74AUC1GU04 or equivalent) are used. Please see Sections
7.2.2.2 and 7.2.3.2 for socket connector connection.